Cypress CY62128L-70ZC 128k x 8 static ram Datasheet

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1CY 621 28
CY62128
PRELIMINARY
128K x 8 Static RAM
Features
• 4.5V − 5.5V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
• Low standby power (70 ns, LL version)
— 110 µW (max.) (20 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE1) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through
I/O7) is then written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Logic Block Diagram
Pin Configurations
Top View
SOJ / SOIC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O4
A11
A9
A8
A13
I/O5
CE1
CE2
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
62128-1
OE
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A0
A1
A2
A3
62128-2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
July 1996 - Revised November 1996
CY62128
PRELIMINARY
Selection Guide
CY62128–55
CY62128–70
55
70
Maximum Access Time (ns)
Maximum Operating Current
Commercial
Maximum CMOS Standby Current
115 mA
110 mA
L
70 mA
60 mA
LL
70 mA
60 mA
10 mA
10 mA
L
100 µA
100 µA
LL
20 µA
20 µA
Commercial
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] .....................................–0.5V to VCC +0.5V
Range
Commercial
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 10%
DC Input Voltage[1]..................................–0.5V to VCC +0.5V
Electrical Characteristics Over the Operating Range[3]
62128–55
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = – 1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1mA
VIH
Input HIGH Voltage
2.2
VCC +
0.3
VIL
Input LOW Voltage[1]
–0.3
IIX
Input Load Current
GND ≤ VI ≤ VCC
IOZ
Output Leakage Current
GND ≤ VI ≤ VCC, Output Disabled
IOS
Output Short Circuit Current[4]
ICC
VCC Operating
Supply Current
VCC = Max., VOUT = GND
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
2.4
Com’l
Automatic CE
Power-Down Current
— CMOS Inputs
Max. VCC,
CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f=0
Com’l
Unit
V
0.4
V
2.2
VCC +
0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–5
+5
–5
+5
µA
–300
–300
mA
115
110
mA
L
70
60
mA
LL
70
60
mA
25
25
mA
10
10
mA
Com’l
Max. VCC, CE1 ≥ VIH
or CE2 < VIL,
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
Max.
2.4
0.4
Automatic CE
Power-Down Current
— TTL Inputs
L
LL
2
2
mA
10
10
mA
L
100
100
µA
LL
20
20
µA
Shaded areas contain advance information
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
62128–70
Min.
CY62128
PRELIMINARY
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
9
pF
9
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
R1 1800 Ω
R1 1800 Ω
5V
ALL INPUT PULSES
5V
OUTPUT
3.0V
90%
OUTPUT
R2
990 Ω
100 pF
R2
990 Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
GND
10%
≤ 5ns
≤ 5 ns
62128-3
62128-4
Equivalent to:
THÉVENIN EQUIVALENT
639 Ω
1.77V
OUTPUT
Switching Characteristics[3,6] Over the Operating Range
62128–55
Parameter
Description
Min.
Max.
62128–70
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
OE HIGH to High
55
5
20
5
Z[7, 8]
CE1 HIGH to High Z, CE2 LOW to High
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
WRITE
ns
35
ns
ns
25
20
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
70
5
0
ns
ns
25
0
55
ns
ns
0
20
tHZCE
tPD
5
0
Z[8]
ns
70
55
Z[7, 8]
CE1 LOW to Low Z, CE2 HIGH to Low
70
55
ns
ns
70
ns
CYCLE[9]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tSD
Data Set-Up to Write End
45
55
ns
Shaded areas contain advance information
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
3
CY62128
PRELIMINARY
Switching Characteristics[3,6] Over the Operating Range (continued)
62128–55
Parameter
tHD
Description
Min.
Data Hold from Write End
WE HIGH to Low
tHZWE
WE LOW to High Z[7,8]
Max.
0
Z[8]
tLZWE
62128–70
Min.
Max.
0
5
Unit
ns
5
ns
20
25
ns
Shaded area contains advanced information.
Switching Waveforms
Read Cycle No.1[10,11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62128-5
Read Cycle No. 2 (OE Controlled)[11,12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
62128-6
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4
CY62128
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
62128-7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
62128-8
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
5
CY62128
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13,14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 15
DATAI/O
tHD
DATA VALID
tLZWE
tHZWE
62128-9
Truth Table
CE1
CE2
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
X
High Z
Power-Down
Standby (I SB)
X
L
X
X
High Z
Power-Down
L
H
L
H
Data Out
Read
Standby (I SB)
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
55
70
Ordering Code
Package
Name
Package Type
CY62128–55VC
V33
32-Lead (400-Mil) Molded SOJ
CY62128–55SC
S34
32-Lead (450-Mil) Molded SOIC
CY62128−55ZC
Z32
32-Lead TSOP TypeI
CY62128–70VC
V33
32-Lead (400-Mil) Molded SOJ
CY62128–70SC
S34
32-Lead (450-Mil) Molded SOIC
CY62128−70ZC
Z32
32-Lead TSOP Type I
CY62128L−70SC
S34
32-Lead (450-Mil) Molded SOIC
CY62128L−70ZC
Z32
32-Lead TSOP Type I
CY62128LL−70SC
S34
32-Lead (450-Mil) Molded SOIC
CY62128LL−70ZC
Z32
32-Lead TSOP Type I
Shaded area contains advanced information.
Document #: 38–00524
6
Operating
Range
Commercial
Commercial
PRELIMINARY
Package Diagrams
32-Lead (450 Mil) Molded SOIC S34
32-Lead Thin Small Outline Package Z32
7
CY62128
PRELIMINARY
CY62128
Package Diagrams (continued)
32-Lead (400-Mil) Molded SOJ V33
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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