TI1 ADS5521IPAPR 12-bit, 105msps analog-to-digital converter Datasheet

ADS5521
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12-Bit, 105MSPS
Analog-To-Digital Converter
FEATURES
THS9001, OPA695, OPA847
1
•
•
•
•
•
•
•
•
•
•
•
2
12-Bit Resolution
105MSPS Sample Rate
High SNR: 70 dBFS at 100 MHz fIN
High SFDR: 86 dBc at 100 MHz fIN
2.3-VPP Differential Input Voltage
Internal Voltage Reference
3.3-V Single-Supply Voltage
Analog Power Dissipation: 571 mW
Serial Programming Interface
TQFP-64 PowerPAD™ Package
Recommended Op Amps:
THS3201, THS3202, THS4503, THS4509,
APPLICATIONS
•
•
•
•
•
•
Wireless Communication
– Communication Receivers
– Base Station Infrastructure
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
– Radar
– Infrared
Video and Imaging
Medical Equipment
DESCRIPTION
The ADS5521 is a high-performance, 12-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
Designed for applications demanding the highest speed and highest dynamic performance in little space, the
ADS5521 has excellent power consumption of 571 mW at 3.3-V single-supply voltage. This allows an even
higher system integration density. The provided internal reference simplifies system design requirements. Parallel
CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5521 is available in a 64-pin TQFP PowerPAD package and in an industrial temperature grade device.
Table 1. ADS5500 Product Family
80MSPS
105MSPS
125MSPS
12 Bit
ADS5522
ADS5521
ADS5520
14 Bit
ADS5542
ADS5541
ADS5500
AVDD
CLK+
CLK−
Timing Circuitry
VIN+
S&H
VIN−
CM
DRVDD
12-Bit
Pipeline
ADC
Core
Internal
Reference
Digital
Error
Correction
Output
Control
SEN
SDATA
SCLK
D0
.
.
.
D11
OVR
DFS
Control Logic
Serial Programming Register
AGND
CLKOUT
ADS5521
DRGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
ADS5521
SBAS309D – MAY 2004 – REVISED OCTOBER 2008 ...................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
ADS5521
HTQFP-64 (2)
PowerPAD
(1)
(2)
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PAP
–40°C to 85°C
ADS5521I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5521IPAP
Tray, 160
ADS5521IPAPR
Tape and Reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper
trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
ADS5521
UNIT
–0.3 to 3.7
V
±0.1
V
–0.3 to minimum (AVDD + 0.3, 3.6)
V
Logic input to DRGND
–0.3 to DRVDD
V
Digital data output to DRGND
–0.3 to DRVDD
V
Operating temperature range
–40 to 85
°C
105
°C
–65 to 150
°C
Analog input to AGND (2) (3)
Junction temperature
Storage temperature range
(1)
(2)
(3)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 W should be added in series with each of the analog
input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle
of the overshoot should be limited to less than 5% for inputs up to 3.9 V.
The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurrences over the lifetime of the device.
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3
3.3
3.6
V
Output driver supply voltage, DRVDD
3
3.3
3.6
V
Supplies
Analog input
Differential input range
Input common-mode voltage, VCM
2.3
(1)
1.45
VPP
1.55
1.65
V
Digital Output
Maximum output load
10
pF
Clock Input
ADCLK input sample rate (sine wave) 1/tC
DLL ON
60
105
DLL OFF
2
80
Clock amplitude, sine wave, differential (2)
1
3
Clock duty cycle (3)
VPP
50%
Open free-air temperature range
(1)
(2)
(3)
MSPS
–40
85
°C
Input common-mode should be connected to CM.
See Figure 49 for more information.
See Figure 48 for more information.
ELECTRICAL CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
12
Bits
Analog Inputs
Differential input range
2.3
VPP
Differential input impedance
See Figure 39
6.6
kΩ
Differential input capacitance
See Figure 39
4
pF
250
µA
750
MHz
Analog input common-mode current
(per input)
Analog input bandwidth
Source impedance = 50 Ω
Voltage overload recovery time
4
Clock
cycles
1
V
Internal Reference Voltages
Reference bottom voltage, VREFM
Reference top voltage, VREFP
2.15
Reference error
–4%
±0.9%
V
4%
1.55
±0.05
Common-mode voltage output, VCM
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
Differential nonlinearity error, DNL
fIN = 55 MHz
–0.5
±0.25
+0.5
LSB
Integral nonlinearity error, INL
fIN = 55 MHz
–1.5
±0.5
+1.5
LSB
–11
±1.5
11
mV
Offset error
Offset temperature coefficient
DC power-supply rejection ratio, DC PSRR
Gain error
Δoffset error/ΔAVDD from AVDD = 3 V to
AVDD = 3.6 V
(1)
–2
Gain temperature coefficient
(1)
0.02
mV/°C
0.25
mV/V
±0.3
2
–0.02
%FS
Δ%/°C
Gain error is specified by design and characterization; it is not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
68
70.5
MAX
UNIT
Dynamic AC Characteristics
fIN = 10 MHz
fIN = 55 MHz
Signal-to-noise ratio. SNR
RMS idle channel noise
71
25°C to 85°C
Full temp range
66.8
fIN = 70 MHz
fIN = 100 MHz
70
fIN = 150 MHz
69.3
fIN = 220 MHz
67.8
Input tied to common-mode
0.32
fIN = 10 MHz
fIN = 55 MHz
Spurious-free dynamic range, SFDR
25°C
78
86
Full temp range
76
85
81
fIN = 100 MHz
86
fIN = 150 MHz
75
fIN = 220 MHz
72
fIN = 10 MHz
90
25°C
78
86
Full temp range
76
85
fIN = 70 MHz
81
fIN = 100 MHz
88
fIN = 150 MHz
75
fIN = 220 MHz
72
Third-harmonic, HD3
Worst-harmonic/spur (other than HD2 and
HD3)
Signal-to-noise + distortion, SINAD
4
dBc
dBc
88
25°C
78
88
Full temp range
76
87
fIN = 70 MHz
87
fIN = 100 MHz
86
fIN = 150 MHz
80
fIN = 220 MHz
78
fIN = 55 MHz
87
fIN = 10 MHz
70.7
fIN = 55 MHz
LSB
83
fIN = 10 MHz
fIN = 55 MHz
dBFS
83
fIN = 70 MHz
fIN = 55 MHz
Second-harmonic, HD2
69
70.3
25°C
Full temp range
67
70
65.8
68.5
fIN = 70 MHz
69.6
fIN = 100 MHz
69.3
fIN = 150 MHz
68.2
fIN = 220 MHz
65.8
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dBc
dBc
dBFS
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1dBFS differential
input, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
fIN = 10 MHz
Effective number of bits, ENOB
Two-tone intermodulation distortion, IMD
AC power supply rejection ratio, ACPSRR
UNIT
79
fIN = 55 MHz
Total harmonic distortion, THD
MAX
25°C
76
83
Full temp range
74
82
fIN = 70 MHz
78
fIN = 100 MHz
84
fIN = 150 MHz
74
fIN = 220 MHz
70.3
fIN = 55 MHz
11.3
f = 10.1 MHz, 15.1 MHz (-7dBFS each tone)
94.6
f = 50.1 MHz, 55.1 MHz (-7dBFS each tone)
96.6
f = 150.1 MHz, 155.1 MHz (-7dBFS each tone)
84.7
Supply noise frequency ≤ 100 MHz
dBc
Bits
dBFS
35
dB
Power Supply
Total supply current, ICC
fIN = 55 MHz
223
250
mA
Analog supply current, IAVDD
fIN = 55 MHz
173
185
mA
Output buffer supply current, IDRVDD
fIN = 55 MHz
50
65
mA
Analog only
571
611
Power dissipation
Output buffer power with 10-pF load on digital
output to ground
165
215
Standby power
With clocks running
180
250
mW
mW
DIGITAL CHARACTERISTICS
Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage, VIH
2.4
V
Low-level input voltage, VIL
0.8
V
High-level input current, IIH
10
µA
-10
µA
Low-level input current, IIL
Input current for RESET
Input capacitance
–20
µA
4
pF
Digital Outputs
Low-level output voltage, VOL
CLOAD = 10 pF
High-level output voltage, VOH
CLOAD = 10 pF
Output capacitance
0.3
2.4
0.4
V
3
pF
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V
3
5
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TIMING CHARACTERISTICS (1) (2)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless
otherwise noted (1)
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Aperture delay, tA
Input CLK falling edge to data sampling point
Aperture jitter (uncertainty)
Uncertainty in sampling instant
(3)
Data setup time, tSETUP
Data valid
Data hold time, tHOLD
50% of CLKOUT rising edge to data becoming
invalid (3)
to 50% of CLKOUT rising edge
Input clock to output data valid start,
tSTART (4) (5)
Input clock rising edge to data valid start delay
Input clock to output data valid end,
tEND (4) (5)
Input clock rising edge to data valid end delay
Output clock jitter, tJIT
Uncertainty in CLKOUT rising edge, peak-to-peak
Output clock rise time, tr
Rise time of CLKOUT from 20% to 80% of DRVDD
Output clock fall time, tf
Fall time of CLKOUT from 80% to 20% of DRVDD
Input clock to output clock delay, tPDI
Input clock rising edge, zero crossing, to output
clock rising edge 50%
Data rise time, tr
1
ns
300
fs
2.2
2.8
ns
2.2
2.5
ns
1.9
5.8
2.8
7.3
ns
ns
175
250
psPP
2
2.2
ns
1.7
1.8
ns
4.7
5.5
ns
Data rise time measured from 20% to 80% of
DRVDD
4.4
5.1
ns
Data fall time, tf
Data fall time measured from 80% to 20% of
DRVDD
3.3
3.8
ns
Output enable(OE) to data output delay
Time required for outputs to have stable timings
with regard to input clock (6) after OE is activated
1000
Time to valid data after coming out of software
power down
1000
Time to valid data after stopping and restarting the
clock
1000
Wakeup time
Latency
(1)
(2)
(3)
(4)
(5)
(6)
6
4
Time for a sample to propagate to the ADC outputs
17.5
Clock
cycles
Clock
cycles
Clock
cycles
Timing parameters are ensured by design and characterization, and not tested in production.
See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies.
Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
See the Output Information section for details on using the input clock for data capture.
These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
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Analog
Input
Signal
Sample
N
N + 1
N + 2
N + 3
N + 4
N + 14
N + 15
N + 16
N + 17
tA
Input Clock
tSTART
Output Clock
tPDI
tsu
Data Out
(D0−D11)
N − 17
N − 16
N − 15
N − 13
N−3
N−2
N−1
Data Invalid
tEND
A.
N − 14
17.5 Clock Cycles
N
th
It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
RESET TIMING CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD =
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Power-on delay, t1
Delay from power-on of AVDD and
DRVDD to RESET pulse active
10
ms
Reset pulse width, t2
Pulse width of active RESET signal
2
µs
Register write delay, t3
Delay from RESET disable to SEN
active
2
µs
Power-up time
Delay from power-up of AVDD and
DRVDD to output stable
Power Supply
(AVDD, DRVDD)
40
ms
t1 10 ms
t2 2 ms
t3 2 ms
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5521 has a three-wire serial interface. The ADS5521 latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
• Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
• Minimum width of data stream for a valid loading is 16 clocks.
• Data is loaded at every 16th SCLK falling edge while SEN is low.
• In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
• Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
• The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
A3
SDATA
A2
A1
A0
D11
D10
ADDRESS
D9
D0
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
SEN
tSLOADS
tSLOADH
tWSCLK tWSCLK
tSCLK
SCLK
tsu(D)
SDATA
th(D)
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 2. Serial Programming Interface Timing Characteristics
(1)
8
MIN (1)
TYP (1)
MAX (1)
50%
75%
SYMBOL
PARAMETER
tSCLK
SCLK period
tWSCLK
SCLK duty cycle
tSLOADS
SEN to SCLK setup time
8
ns
tSLOADH
SCLK to SEN hold time
6
ns
tDS
Data setup time
8
ns
tDH
Data hold time
6
ns
50
25%
UNIT
ns
Typ, min, and max values are characterized, but not production tested.
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Table 3. Serial Register Table (1)
A3 A2 A1 A0
D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DLL
CTRL
DESCRIPTION
Clock DLL
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Internal DLL is on; recommended for 60MSPS to 105MSPS
clock speeds.
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
Internal DLL is off; recommended for 2MSPS to 80MSPS
clock speeds.
TP<1>
TP<0>
1
1
1
0
0
0
0
0
0
0
0
0
0
0
X
0
Normal mode of operation
1
1
1
0
0
0
1
0
0
0
0
0
0
0
X
0
All outputs forced to 0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
X
0
All outputs forced to 1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
X
0
Each output bit toggles between 0 and 1.
Test Mode
PDN
(2) (3)
Power Down
1
1
1
1
0
0
0
0
0
0
0
0
0
0
X
0
Normal mode of operation
1
1
1
1
1
0
0
0
0
0
0
0
0
0
X
0
Device is put in power-down (low-current) mode.
(1)
(2)
(3)
The register contents default to the appropriate setting for normal operation up on RESET.
The patterns given are applicable to the straight offset binary output format. If 2's complement output format is selected, the test mode
outputs will be the binary 2's complement equivalent of these patterns as described in the Output Information section.
While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 4. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS)
V DFS t
2
12
AV DD
DATA FORMAT
CLOCK OUTPUT POLARITY
Straight Binary
Data valid on rising edge
4
12
5
AV DD t V DFS t
12
AV DD
2's complement
Data valid on rising edge
7
12
AV DD t V DFS t
8
12
AV DD
Straight Binary
Data valid on falling edge
2's complement
Data valid on falling edge
V DFS u
10
12
AV DD
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PIN CONFIGURATION
10
55
54
53
52
51
50
DRVDD
56
DRGND
D2
57
D3
58
D4
59
D5
60
D6
D8
61
D7
D9
62
DRGND
D10
63
DRVDD
D11 (MSB)
64
DRGND
OVR
PAP PACKAGE
HTQFP-64
(TOP VIEW)
49
DRGND
1
48 DRGND
SCLK
2
47 D1
SDATA
3
46 D0 (LSB)
SEN
4
45 NC
AVDD
5
44 NC
AGND
6
43 CLKOUT
AVDD
7
AGND
8
AVDD
9
42 DRGND
ADS5521
PowerPAD
41 OE
40 DFS
(Connected to Analog Ground)
19
20
21
22
23
24
25
26
27
28
29
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30
31
32
AGND
18
IREF
17
REFM
33 AVDD
REFP
AGND 16
AVDD
34 AVDD
AGND
AVDD 15
AVDD
35 RESET
AGND
AGND 14
AVDD
36 AGND
AGND
AGND 13
AVDD
37 AVDD
AGND
AGND 12
INM
38 AGND
INP
CLKM 11
AGND
39 AVDD
CM
CLKP 10
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PIN ASSIGNMENTS (1)
TERMINAL
NO. OF
PINS
I/O
AVDD
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
12
I
Analog power supply
AGND
6, 8, 12, 13,
14, 16, 18, 21,
23, 25, 27, 32,
36, 38
14
I
Analog ground
DRVDD
49, 58
2
I
Output driver power supply
DRGND
1, 42, 48, 50,
57, 59
6
I
Output driver ground
NC
44, 45
2
—
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive); 1-µF capacitor in series with a 1-Ω resistor to GND
REFM
30
1
O
Reference voltage (negative); 1-µF capacitor in series with a 1-Ω resistor to GND
IREF
31
1
I
Current set; 56-kΩ resistor to GND; do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), 200-kΩ resistor to AVDD (2)
OE
41
1
I
Output enable (active high) (3)
DFS
40
1
I
Data format and clock out polarity select (4) (3)
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select (3)
SDATA
3
1
I
Serial interface data (3)
SCLK
2
1
I
Serial interface clock (3)
46, 47, 51-56,
60-63
14
O
Parallel data output
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
NAME
NO.
D0 (LSB) to
D11 (MSB)
(1)
(2)
(3)
(4)
DESCRIPTION
Not connected
PowerPAD is connected to analog ground.
If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.
Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
Table 4 defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty
cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSBs.
Integral Nonlinearity (INL)
The offset error is the difference, given in number of
LSBs, between the ADC's actual average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
DC and the first eight harmonics.
P
SNR + 10Log 10 S
PN
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
DC.
PS
SINAD + 10Log 10
PN ) PD
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSBs.
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Gain Error
Effective Number of Bits (ENOB)
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Specifications section for limits on the
variation of VREFP and VREFM).
The ENOB is a measure of a converter's performance
as compared to the theoretical limit based on
quantization noise.
ENOB + SINAD * 1.76
6.02
12
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Total Harmonic Distortion (THD)
Two-Tone Intermodulation Distortion (IMD3)
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
P
THD + 10Log 10 S
PD
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or
2f2 –f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to Full-Scale)
when the power of the fundamental is extrapolated to
the converter's full-scale range.
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
DC Power Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
Reference Error
The reference error is the variation of the actual
reference voltage (VREFP - VREFM) from its ideal
value. The reference error is typically given as a
percentage.
Voltage Overload Recovery Time
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 4 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16 MHz Input Signal)
0
0
SFDR = 92.6dBc
SNR = 71.3dBFS
THD = 88.2dBc
SINAD = 71.2dBFS
−40
−60
−80
−100
−60
−80
20
30
40
50
f − Frequency − MHz
0
10
30
40
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70 MHz Input Signal)
0
50
0
SFDR = 90.4dBc
SNR = 71.0dBFS
THD = 85.4dBc
SINAD = 70.8dBFS
−20
Magnitude − dB
−40
SFDR = 81.7dBc
SNR = 70.6dBFS
THD = 80.3dBc
SINAD = 70.2dBFS
−20
−60
−80
−100
−40
−60
−80
−100
−120
20
30
40
50
f − Frequency − MHz
0
10
20
30
40
50
f − Frequency − MHz
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 80 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 100 MHz Input Signal)
0
52.5
10
52.5
−120
0
0
SFDR = 84.5dBc
SNR = 70.4dBFS
THD = 83.3dBc
SINAD = 70.2dBFS
−40
SFDR = 86.2dBc
SNR = 70.1dBFS
THD = 85.2dBc
SINAD = 70.0dBFS
−20
Magnitude − dB
−20
−60
−80
−100
−40
−60
−80
−100
10
20
30
f − Frequency − MHz
40
50
0
Figure 9.
10
20
30
f − Frequency − MHz
40
50
52.5
−120
0
52.5
−120
14
20
f − Frequency − MHz
52.5
10
52.5
−120
0
Magnitude − dB
−40
−100
−120
Magnitude − dB
SFDR = 88.9dBc
SNR = 71.1dBFS
THD = 86.9dBc
SINAD = 71.0dBFS
−20
Magnitude − dB
Magnitude − dB
−20
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 150 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220 MHz Input Signal)
0
0
SFDR = 75.3dBc
SNR = 69.4dBFS
THD = 75.0dBc
SINAD = 68.1dBFS
−40
−60
−80
−100
−60
−80
20
30
40
50
f − Frequency − MHz
0
10
20
30
40
50
f − Frequency − MHz
Figure 11.
Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal)
TWO-TONE
INTERMODULATION
52.5
10
52.5
−120
0
0
0
SFDR = 65.6dBc
SNR = 66.6dBFS
THD = 64.9dBc
SINAD = 62.7dBFS
−40
f1 = 10.1MHz (−7dBFS)
f2 = 15.1MHz (−7dBFS)
2−Tone IMD = 94.1dBFS
−20
Magnitude − dB
−20
−60
−80
−100
−40
−60
−80
−100
10
20
30
40
50
f − Frequency − MHz
0
10
20
30
40
50
52.5
−120
0
52.5
−120
40
50
52.5
Magnitude − dB
−40
−100
−120
f − Frequency − MHz
Figure 13.
Figure 14.
TWO-TONE
INTERMODULATION
TWO-TONE
INTERMODULATION
0
0
f1 = 45.1MHz (−7dBFS)
f2 = 50.1MHz (−7dBFS)
2−Tone IMD = 94.0dBc
−20
f1 = 150.1MHz (−7dBFS)
f2 = 155.1MHz (−7dBFS)
2−Tone IMD = 85.1dBFS
−20
−40
Magnitude − dB
Magnitude − dB
SFDR = 73.1dBc
SNR = 68.2dBFS
THD = 71.9dBc
SINAD = 66.6dBFS
−20
Magnitude − dB
Magnitude − dB
−20
−60
−80
−100
−40
−60
−80
−100
−120
10
20
30
f − Frequency − MHz
40
50
52.5
−120
0
0
Figure 15.
10
20
30
f − Frequency − MHz
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
0.25
1.0
fIN = 10MHz
AIN = −0.5dBFS
0.15
0.6
0.10
0.4
0.05
0
−0.05
0.2
0
−0.2
−0.10
−0.4
−0.15
−0.6
−0.20
−0.8
−0.25
−1.0
0
1024
2048
3072
4096
0
1024
3072
Code
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
95
76
90
74
4096
72
SNR − dBFS
80
75
70
70
68
66
64
65
62
60
60
0
50
100
150
200
250
300
0
50
Frequency − MHz
100
150
200
250
300
Frequency − MHz
Figure 19.
Figure 20.
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
76
95
fIN = 150MHz
SFDR − dBc
SFDR − dBc
2048
Code
85
SFDR − dBc
f IN = 10MHz
AIN = −0.5dBFS
0.8
INL − LSB
DNL − LSB
0.20
75
SFDR
74
73
fIN = 70MHz
90
85
SFDR
80
SNR − dBFS
SNR − dBFS
72
71
70
SNR
69
68
SNR
70
65
60
3.0
16
75
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
AVDD − Analog Supply Voltage − V
AVDD − Analog Supply Voltage − V
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
88
fIN = 150MHz
SFDR − dBc
SFDR − dBc
78
76
SFDR
74
SFDR
80
76
SNR
SNR − dBFS
SNR − dBFS
72
fIN = 70MHz
84
70
68
66
SNR
72
68
64
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
DVDD − Digital Supply Voltage − V
DVDD − Digital Supply Voltage − V
Figure 23.
Figure 24.
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
800
800
fIN = 70MHz
fIN = 150MHz
750
700
Power Dissipation − mW
Power Dissipation − mW
750
DLL On
650
DLL Off
600
550
DLL On
650
DLL Off
600
550
20
30
40
50
60
70
80
90
100
450
10
20
30
40
50
60
70
80
Sample Rate − MSPS
Sample Rate − MSPS
Figure 25.
Figure 26.
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
90
90
100
105
10
105
450
90
fIN = 70MHz
80
70
85
SFDR
AC Performance − dB
SFDR − dBc
700
500
500
80
75
SNR − dBFS
3.6
SNR
70
65
60
−40
−15
+10
+35
+60
+85
SNR (dBFS)
60
50
40
30
SFDR (dBc)
20
10
0
−10
SNR (dBc)
−20
−30
−100 −90 −80 −70 −60 −50 −40
Temperature − _C
fIN = 70MHz
−30 −20
−10
0
Input Amplitude − dBFS
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, sampling rate = 105MSPS,
DLL On,
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs INPUT AMPLITUDE
100
90
80
SNR (dBFS)
70
60
50
40
SFDR (dBc)
30
20
SNR (dBc)
10
0
−10
−20
f IN = 150MHz
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
90
80
70
AC Performance − dB
AC Performance − dB
AC PERFORMANCE
vs INPUT AMPLITUDE
SFDR (dBc)
30
20
SNR (dBc)
10
0
−10
f IN = 220MHz
−30 −20
Input Amplitude − dBFS
Figure 29.
Figure 30.
OUTPUT
NOISE HISTOGRAM
AC PERFORMANCE
vs CLOCK AMPLITUDE
−10
0
95
SFDR − dBc
80
70
60
fIN = 70MHz
90
SFDR
85
80
50
40
SNR − dBFS
Occurrence − %
50
40
Input Amplitude − dBFS
90
30
20
75
SNR
70
65
60
2059
2057
2058
2055
2056
2053
2054
2051
2052
2049
2050
2047
2048
2045
0
2046
10
0
0.5
1.0
1.5
2.0
2.5
Code
Differential Clock Amplitude − V
Figure 31.
Figure 32.
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
0
3.0
−40
−60
SFDR − dBc
100
fS = 92.16MSPS
fIN = 170MHz
−20
fIN = 20MHz
95
90
SFDR
85
80
−80
SNR − dBFS
Magnitude − dB
60
−20
−30
−100 −90 −80 −70 −60 −50 −40
100
−100
−120
−140
75
SNR
70
65
60
0
18
SNR (dBFS)
5
10
15
20
25
30
35
40
45
50
35
40
45
50
55
f − Frequency − MHz
Clock Duty Cycle − %
Figure 33.
Figure 34.
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65
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR)
(DLL On)
125
69
71
120
70.5
71
69.5
70
115
70.5
110
70.5
105
70
100
71
68.5
69
70.5
95
69.5
69.5
70.5
90
69
SNR − dBFS
Sample Rate − MSPS
70.5
85
71.5
70
68.5
80
75
68.5
68
69
71
68
71
70
70.5
65
20
40
60
80
100
120
67.5
69.5
70
140
160
180
200
220
Input Frequency − MHz
Figure 35.
SIGNAL-TO-NOISE RATIO (SNR)
(DLL Off)
100
71
69
90
70
71
69
70
68
70
67
66
60
69
71
68
70
50
69
40
64
71
68
70
71
69
67
68
30
65
67
65
66
66
SNR − dBFS
Sampe Rate − MSPS
80
63
62
64
61
20
70
69
10
20
40
67
66
68
60
80
100
63
65
120
64
140
62
61
63
160
180
200
63
60
220
Input Frequency − MHz
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
(DLL On)
81
120
115
83
87
85
89
85
81
79
77
90
79
83
75
110
Sample Rate − MSPS
85
105
90
89
87
87
85
93
83
80
85
89
83
89
79
80
70
81
87
73
79
85
85
79
65
40
60
70
75
77
81
20
75
81
83
89
75
77
81
87
75
85
81
81
85
91
77
79
83
87
95
75
81
91
100
79
77
SFDR − dBc
125
80
100
120
140
160
180
200
220
Input Frequency − MHz
Figure 37.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
(DLL Off)
80
82
84
88 86
78
80
74
78
88
72
82 80
86
86
70
68
66
84
88
88
82
76
86
50
76
74
86
40
88
86
84
60
90
66
84
SFDR − dBc
84
86
88
90
70 68
84
86
86
78
72
88
80
Sample Rate − MSPS
84
90
86 88
90
82
86
84
70
76 74
80
100
72
84
86
30
88
68
84
80
86
20
86
82
80
84
10
20
40
60
70
78
82
76
74
70
68
72
66
78
80
100
120
140
Input Frequency − MHz
160
66
180
200
64
64
220
Figure 38.
20
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5521 is a low-power, 12-Bit, 105MSPS, CMOS, switched capacitor, pipeline ADC that operates from a
single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a data
latency of 17.5 clock cycles, after which the output data is available as a 12-Bit parallel word, coded in either
straight offset binary or binary 2's complement format.
INPUT CONFIGURATION
The analog input for the ADS5521 consists of a differential sample-and-hold architecture implemented using the
switched capacitor technique shown in Figure 39.
S3a
L1
R1a
C1a
INP
S1a
CP1
CP3
S2
R3
CA
L2
R1b
INM
S1b
C1b
VINCM
1V
CP2
CP4
L1, L2: 6 nH − 10 nH effective
R1a, R1b: 5W − 8W
C1a, C1b: 2.2 pF − 2.6 pF
CP1, CP2: 2.5 pF − 3.5 pF
CP3, CP4: 1.2 pF − 1.8 pF
CA: 0.8 pF − 1.2 pF
R3: 80 W − 120 W
Swithches: S1a, S1b: On Resistance: 35 W − 50 W
S2: On Resistance: 7.5 W − 15 W
S3a, S3b: On Resistance: 40 W − 60 W
All switches OFF Resistance: 10 GW
A.
S3b
All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 39. Analog Input Stage
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This differential input topology produces a high level of ac-performance for high sampling rates. It also results in
a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling
applications. The ADS5521 requires each of the analog inputs (INP, INM) to be externally biased around the
common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential
lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This
means that each input is driven with a signal of up to CM + 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM,
pin 30).
The ADS5521 obtains optimum performance when the analog inputs are driven differentially. The circuit shown
in Figure 40 illustrates one possible configuration using an RF transformer.
R0
Z0
50 W
50 W
25 W
IN P
1:1
R
A C S igna l
50 W
S ource
ADS5521
25 W
IN M
AD T 1−1 W T
CM
1 0W
1nF
0.1 m F
Figure 40. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Placing a 25-Ω resistor in series with
INP and INM is recommended to dampen ringing due to ADC kickback.
Since the input signal must be biased around the common-mode voltage of the internal circuitry, the
common-mode voltage (VCM) from the ADS5521 is connected to the center-tap of the secondary winding.
To ensure a steady low-noise VCM reference, best performance is attained when the CM output (pin 17) is filtered
to ground with a 10-Ω series resistor and parallel 0.1-µF and 0.001-µF low-inductance capacitors, as illustrated in
Figure 39.
Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware
that the input structure of the ADC sinks a common-mode current in the order of 500 µA (250 µA per input).
Equation 1 describes the dependency of the common-mode current and the sampling frequency:
500mA f S (in MSPS)
105 MSPS
(1)
Where:
fS > 2MSPS.
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a
transformer, to drive the input of the ADS5521. Texas Instruments offers a wide selection of single-ended
operational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selected
depending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also be
used with an RF transformer for high input frequency applications. The THS4503 is a recommended differential
input/output amplifier. Table 5 lists the recommended amplifiers.
22
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Table 5. Recommended Amplifiers to Drive the Input of the ADS5521
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
DC to 20 MHz
THS4503
Differential In/Out Amp
No
DC to 50 MHz
OPA847
Operational Amp
Yes
DC to 100 MHz
THS4509
Differential In/Out Amp
No
OPA695
Operational Amp
Yes
THS3201
Operational Amp
Yes
THS3202
Operational Amp
Yes
THS9001
RF Gain Block
Yes
10 MHz to 120 MHz
Over 100 MHz
USE WITH TRANSFORMER?
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) to
provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer
and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5521. These
three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain block amplifier can
be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of
the ADS5521 directly, as shown in Figure 40, or with the addition of the filter circuit shown in Figure 41.
Figure 41 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these
components be included in the ADS5521 circuit layout when any of the amplifier circuits discussed previously are
used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines
of the ADS5521 input produces a degradation in performance at high input frequencies, mainly characterized by
an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical
symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations
(see Figure 42), such amplifiers can be used for single-ended-to-differential conversion signal amplification.
+5V -5V
RS
100W
VIN
0.1 mF
1:1
OPA695
1000 pF
R1
400W
RIN
25 W
INP
RT
100 W RIN
CIN
ADS5521
25 W
INM
CM
R2
57.5 W
AV = 8V/V
(18dB)
10 W
0.1 mF
Figure 41. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
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RS
RG
RF
+5V
RT
+3.3V
10 mF
0.1 mF
RIN
INP
VCOM
1 mF
RIN
INM
THS4503
10 mF
RG
ADS5521
12-Bit / 105MSPS
-5V
0.1 mF
CM
10W
RF
0.1 mF
Figure 42. Using the THS4503 with the ADS5521
POWER-SUPPLY SEQUENCE
The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of
AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD
ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as
shown in Figure 43. This helps to make the device more robust to power supply ramp-up timings.
28
AVDD
29
REFP
2 kW
1W
1 mF
Figure 43.
POWER-DOWN
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit
through the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock
frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and
only the internal reference remains on to reduce the power-up time. The power-down mode reduces power
dissipation to approximately 180 mW.
24
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REFERENCE CIRCUIT
The ADS5521 has built-in internal reference generation, requiring no external circuitry on the printed circuit board
(PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF decoupling
capacitor (the 1-Ω resistor shown in Figure 44 is optional). In addition, an external 56.2-kΩ resistor should be
connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in
Figure 44. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor should be
used.
1W
29
R EF P
30
R EF M
31
IR EF
1 mF
1W
1 mF
56.2 kW
Figure 44. REFP, REFM, and IREF Connections for Optimum Performance
CLOCK INPUT
The ADS5521 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. The common-mode voltage of the clock inputs
is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM
(pin 17), as shown in Figure 45.
CM
CM
5 kW
5 kW
CLKM
CLKP
6 pF
3 pF
3 pF
Figure 45. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-µF
capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 46.
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Square Wave
or Sine Wave
(3 VPP)
CLKP
0.01 mF
ADS5521
CLKM
0.01 mF
Figure 46. AC-Coupled, Single-Ended Clock Input
The ADS5521 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this
case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as shown
in Figure 47.
0.01 mF
CLKP
Differential Square Wave
or Sine Wave
(3 VPP)
ADS5521
0.01 mF
CLKM
Figure 47. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the
internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty
cycle should be provided. Figure 48 shows the performance variation of the ADC versus clock duty cycle.
SFDR − dBc
100
fIN = 20MHz
95
90
SFDR
85
SNR − dBFS
80
75
SNR
70
65
60
35
40
45
50
55
60
65
Clock Duty Cycle − %
Figure 48. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When
using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a
differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute
maximum ratings of the ADC clock input. Figure 49 shows the performance variation of the device versus input
clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the
ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.
26
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SFDR − dBc
95
fIN = 70MHz
90
SFDR
85
SNR − dBFS
80
75
SNR
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude − V
Figure 49. AC Performance vs Clock Amplitude
INTERNAL DLL
In order to obtain the fastest sampling rates achievable with the ADS5521, the device uses an internal digital
delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance
at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be
shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical
Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL
OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The
limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz.
OUTPUT INFORMATION
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the
full-scale limits.
Two different output formats (straight offset binary or 2's complement) and two different output clock polarities
(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one
of four different voltages. Table 4 details the four modes. In addition, output enable control (OE, pin 41, active
high) is provided to put the outputs into a high-impedance state.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 0xFFF in straight offset binary output format and 0x7FF in 2's complement output
format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x800
in 2's complement output format. These outputs to an overdrive signal are ensured through design and
characterization.
The output circuitry of the ADS5521, by design, minimizes the noise produced by the data switching transients,
and, in particular, its coupling to the ADC analog circuitry. Output D2 (pin 51) senses the load capacitance and
adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in
the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have
nearly the same load as D2 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply
voltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 105MSPS maximum
sampling frequency. Table 6 and Table 7 show the setup, hold, input clock to output data delays, and rise and
fall times for different sampling frequencies with the DLL on and off, respectively.
Table 8 and Table 9 show the rise and fall times at additional sampling frequencies with DLL on and off,
respectively.
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To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either of the following equations to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN
TYP
MIN
TYP
TYP
MAX
MIN
TYP
TYP
MAX
TYP
MAX
80
2.8
3.7
2.8
3.3
0.5
1.7
5.3
7.9
5.8
6.6
4.4
5.3
65
3.8
4.6
3.6
4.1
–0.5
0.8
5.3
8.5
6.7
7.2
5.5
6.4
MAX
MAX
MIN
MAX
MIN
MIN
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN
TYP
MIN
TYP
TYP
MAX
MIN
TYP
TYP
MAX
TYP
MAX
80
3.2
4.2
1.8
3
3.8
5
8.4
11
5.8
6.6
4.4
5.3
65
4.3
5.7
2
3
2.8
4.5
8.3
11.8
6.6
7.2
5.5
6.4
40
8.5
11
2.6
3.5
–1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17
25.7
2.5
4.7
–9.8
2
9.5
21.6
7.5
8
7.6
8
10
27
51
4
6.5
-30
-3
11.5
31
2
284
370
8
19
185
320
515
576
50
82
75
150
MAX
MAX
MIN
MAX
MIN
MIN
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
fS
(MSPS)
CLKOUT, Rise Time
tr (ns)
MIN
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
CLKOUT, Fall Time
tf (ns)
MIN
MIN
Input-to-Output
Clock Delay
tPDI (ns)
TYP
MAX
TYP
MAX
TYP
MAX
MIN
TYP
MAX
80
2.5
2.8
2.1
2.3
210
315
3.7
4.3
5.1
65
3.1
3.5
2.6
2.9
260
380
3.5
4.1
4.8
Table 9. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
fS
(MSPS)
CLKOUT, Rise Time
tr (ns)
MIN
TYP
MAX
80
2.5
65
3.1
40
20
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
CLKOUT, Fall Time
tf (ns)
MIN
TYP
MAX
2.8
2.1
3.5
2.6
4.8
5.3
8.3
9.5
MIN
Input-to-Output Clock Delay
tPDI (ns)
TYP
MAX
MIN
TYP
MAX
2.3
210
315
2.9
260
380
7.1
8
8.9
7.8
8.5
4
4.4
445
9.4
650
9.5
10.4
11.4
7.6
8.2
800
1200
13
15.5
18
16
20.7
25.5
537
551
567
10
2
28
31
52
36
65
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SERIAL PROGRAMMING INTERFACE
The ADS5521 has internal registers for the programming of some of the modes described in the previous
sections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin
35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup
resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register
setting in the Serial Programing Interface section describe the programming of this register.
Table 3 shows the different modes and the bit values to be written to the register to enable them.
Note that some of these modes may modify the standard operation of the device and possibly vary the
performance with respect to the typical data shown in this data sheet.
Applying a RESET signal is absolutely essential to set the internal registers to their default states for normal
operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and
it is necessary to write the default values to the internal registers through the serial programming interface. The
following registers must be written in this order.
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse is not provided to the device.
PowerPAD PACKAGE
The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of
the IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermal
pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a
heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm.
2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
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For more detailed information regarding the PowerPAD package and its thermal properties, see either the
application brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD Thermally
Enhanced Package).
Table 10. Revision History
Added notes regarding the input voltage overstress requirements in the absolute maximum ratings table.
Changed offset temperature coefficient to units of mV/°C.
Clarified output capture test modes in Table 3.
Updated the definitions section.
Updated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate.
Added footnotes in the Pin Assignements table or pins RESET,OE, SEN, SDATA and SCLK pins.
Removed the input voltage stress section in the Application Information section.
Tpdi parameter was added to the timing Table 8 and Table 9.
Added note in the Serial Programming section about mandatory RESET.
Added latency specification in the Timing Characteristics table.
Rev C
Added min/max specs for Offset and Gain errors.
Rev D
Output Information Section, p. 27.
Changed - From: binary output format and 0x4FFF To: binary output format and 0x7FF.
Changed From: binary output format and 0x2000 To: binary output format and 0x800.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS5521IPAP
ACTIVE
HTQFP
PAP
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5521I
ADS5521IPAPG4
ACTIVE
HTQFP
PAP
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5521I
ADS5521IPAPR
OBSOLETE
HTQFP
PAP
64
TBD
Call TI
Call TI
-40 to 85
ADS5521IPAPRG4
OBSOLETE
HTQFP
PAP
64
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Nov-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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