TI CY74FCT16952CTPACT 16-bit registered transceiver Datasheet

1CY74FCT162H952
T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
16-Bit Registered Transceivers
SCCS065A - August 1994 - Revised March 2000
Features
• Eliminates the need for external pull-up or pull-down
resistors
• FCT-E speed at 3.7 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16952T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at
VCC = 5V, TA = 25˚C
Functional Description
These 16-bit registered transceivers are high-speed,
low-power devices. 16-bit operation is achieved by connecting
the control lines of the two 8-bit registered transceivers
together. For data flow from bus A-to-B, CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when OEAB is LOW. Control of data from B-to-A is similar and
is controlled by using the CEBA, CLKBA, and OEBA inputs.
The output buffers are designed with a power-off disable
feature to allow for live insertion of boards.
The CY74FCT16952T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162952T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162952T is ideal for driving transmission lines.
CY74FCT162952T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at
VCC = 5V, TA= 25˚C
The CY74FCT162H952T is a 24-mA balanced output part that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
CY74FCT162H952T Features:
• Bus hold retains last active state
Pin Configuration
Logic Block Diagrams
SSOP/TSSOP
Top View
1 OEAB
2 CEBA
1 CEBA
1 CLKBA
2 CLKBA
1 OEAB
2 OEAB
1 CEAB
2 CEAB
1 CLKAB
2 CLKAB
1 OEBA
1A1
1
2
56
55
1 OEBA
3
4
54
53
1 CEBA
5
52
1B1
1A2
VCC
6
51
1B2
7
50
VCC
1A3
8
9
49
48
1B3
47
46
45
1B5
GND
1A6
10
11
12
1A7
13
44
1B7
1A8
14
43
1B8
2A1
15
42
2B1
2A2
16
17
41
40
2B2
GND
2A4
18
39
GND
19
38
2B4
2A5
20
21
37
36
2B5
2A6
VCC
22
35
VCC
2A7
23
34
2B7
2A8
24
25
33
32
2B8
GND
2 CEAB
26
31
2 CEBA
2 CLKAB
27
30
2 CLKBA
2 OEAB
28
29
2 OEBA
1 CLKAB
1 CEAB
GND
1A1
2 OEBA
C
CE
D
1B1
C
CE
D
2A1
1A4
1A5
C
CE
D
2B
C
CE
D
FCT16952–1
TO 7 OTHER CHANNELS
FCT16952–2
TO 7 OTHER CHANNELS
1
2A3
1 CLKBA
GND
1B4
GND
1B6
2B3
2B6
GND
FCT16952–3
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Maximum Ratings[5, 6]
Pin Description
Name
Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
Storage Temperature ................................. –55°C to +125°C
CEAB
A-to-B Clock Enable Input (Active LOW)
CEBA
B-to-A Clock Enable Input (Active LOW)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
DC Input Voltage ........................................... –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ........................–60 to +120 mA
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Function Table[2, 3]
For A-to-B (Symmetric with B-to-A)
Operating Range
Inputs
Outputs
CEAB
CLKAB
OEAB
A
B
H
X
L
X
B[4]
X
L
L
X
B[4]
L
L
L
L
L
L
H
H
H
X
Z
X
X
Range
Industrial
Ambient
Temperature
VCC
–40°C to +85°C
5V ± 10%
Notes:
1. On the CY74FCT162H952T these pins have bus hold.
2. A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA.
3. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
4.
5.
6.
= LOW-to-HIGH Transition.
Z = HIGH Impedance.
Level of B before the indicated steady-state input conditions were established.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Electrical Characteristics Over the Operating Range
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
Min.
Input Hysteresis
VIK
Input Clamp Diode Voltage
IIH
Input HIGH Current
100
VCC=Min., IIN= –18 mA
Standard
Input LOW Current
Unit
V
0.8
–0.7
VCC=Max., VI=VCC
V
mV
–1.2
V
±1
µA
±100
Bus Hold
IIL
Max.
2.0
[8]
VH
Typ.[7]
Standard
VCC=Max., VI=GND
Bus Hold
[9]
VCC=Min.
±1
µA
±100
µA
VI=2.0V
–50
µA
VI=0.8V
+50
µA
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold Input
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[9]
VCC=Max., VI=1.5V
IOZH
High Impedance Output Current (Three-State
Output pins)
IOZL
IOS
TBD
mA
VCC=Max., VOUT=2.7V
±1
µA
High Impedance Output Current (Three-State
Output pins)
VCC=Max., VOUT=0.5V
±1
µA
Short Circuit Current[10]
VCC=Max., VOUT=GND
–80
–200
mA
Current[10]
VCC=Max., VOUT=2.5V
–50
–180
mA
±1
µA
Max.
Unit
IO
Output Drive
IOFF
Power-Off Disable
–140
VCC=0V, VOUT≤4.5V[11]
Output Drive Characteristics for CY74FCT16952T
Parameter
VOH
VOL
Min.
Typ.[7]
VCC=Min., IOH= –3 mA
2.5
3.5
V
VCC=Min., IOH= –15 mA
2.4
3.5
V
VCC=Min., IOH= –32 mA
2.0
3.0
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC=Min., IOL=64 mA
V
0.2
0.55
V
Typ.[7]
Max.
Unit
Output Drive Characteristics for CY74FCT162952T, CY74FCT162H952T
Parameter
Description
Test Conditions
Min.
IODL
Output LOW
Current[10]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
60
115
150
mA
IODH
Output HIGH Current[10]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
–60
–115
–150
mA
VOH
Output HIGH Voltage
VCC=Min., IOH= –24 mA
2.4
3.3
VOL
Output LOW Voltage
VCC=Min., IOL=24 mA
V
0.3
0.55
V
Typ.[7]
Max.
Unit
4.5
6.0
pF
Capacitance[8] (TA = +25˚C, f = 1.0 MHz)
Parameter
CIN
Description
Input Capacitance
Test Conditions
VIN = 0V
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Note:
7. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
8. This parameter is specified but not tested.
9. Pins with bus hold are described in the Pin Description.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a
high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests,
IOS tests should be performed last.
11. Tested at +25˚C.
3
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Power Supply Characteristics
Parameter
Test Conditions[12]
Description
Typ.[7]
Max.
Unit
5
500
µA
0.5
1.5
mA
ICC
Quiescent Power Supply Current VCC=Max.
VIN<0.2V
VIN>VCC–0.2V
∆ICC
Quiescent Power Supply Current VCC=Max.
(TTL inputs HIGH)
VIN=3.4V[13]
ICCD
Dynamic Power Supply
Current[14]
VCC=Max., One Input Toggling, VIN=VCC or
50% Duty Cycle, Outputs Open, VIN=GND
OEAB or OEBA=GND
75
120
µA/MHz
IC
Total Power Supply Current[15]
VCC=Max., F1=5 MHz,
F0 = 10 MHz (CLKAB)
OEAB = CEAB = GND
OEBA = VCC 50% Duty Cycle,
Outputs Open, One Bit Toggling
VIN=VCC or
VIN=GND
0.8
1.7
mA
VIN=3.4V or
VIN=GND
1.3
3.2
VIN=VCC or
VIN=GND
3.8
6.5[16]
VIN=3.4V or
VIN=GND
8.3
20.0[16]
VCC=Max., f0=10 MHz (CLKAB)
f1=2.5 MHz,
OEAB = CEAB = GND
OEBA = VCC 50% Duty Cycle,
Outputs Open,
Sixteen Bit Toggling
Notes:
12. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= IQUIESCENT + IINPUTS + IDYNAMIC
15. IC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Switching Characteristics Over the Operating Range[17]
CY74FCT16952AT
CY74FCT162952AT
CY74FCT162H952AT
Parameter
Description
CY74FCT162952BT
Min.
Max.
Min.
Max.
Unit
Fig. No.[18]
tPLH
tPHL
Propagation Delay
CLKAB, CLKBA to B, A
2.0
10.0
2.0
7.5
ns
1, 5
tPZH
tPZL
Output Enable Time
OEBA, OEAB to A, B
1.5
10.5
1.5
8.0
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
OEBA, OEAB to A, B
1.5
10.0
1.5
7.5
ns
1, 7, 8
tSU
Set-Up Time, HIGH or LOW
A, B to CLKAB, CLKBA
2.5
—
2.5
—
ns
4
tH
Hold Time, HIGH or LOW
A, B to CLKAB, CLKBA
2.0
—
1.5
—
ns
4
tSU
Set-Up Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
3.0
—
3.0
—
ns
4
tH
Hold Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
2.0
—
2.0
—
ns
4
tW
Pulse Width HIGH or LOW
CLKAB or CLKBA[19]
3.0
—
3.0
—
ns
5
tSK(O)
Output Skew[20]
—
0.5
—
0.5
ns
—
CY74FCT16952CT
CY74FCT162H952CT
Parameter
Description
CY74FCT16952ET
CY74FCT162952ET
CY74FCT162H952ET
Min.
Max.
Min.
Max.
Unit
Fig. No.[18]
tPLH
tPHL
Propagation Delay
CLKAB, CLKBA to B, A
2.0
6.3
1.5
3.7
ns
1, 5
tPZH
tPZL
Output Enable Time
OEBA, OEAB to A, B
1.5
7.0
1.5
4.4
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
OEBA, OEAB to A, B
1.5
6.5
1.5
3.6
ns
1, 7, 8
tSU
Set-Up Time, HIGH or LOW
A, B to CLKAB, CLKBA
2.5
—
1.5
—
ns
4
tH
Hold Time, HIGH or LOW
A, B to CLKAB, CLKBA
1.5
—
0
—
ns
4
tSU
Set-Up Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
3.0
—
2.0
—
ns
4
tH
Hold Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
2.0
—
0
—
ns
4
tW
Pulse Width HIGH or LOW
CLKAB or CLKBA[19]
3.0
—
3.0
—
ns
5
tSK(O)
Output Skew[20]
—
0.5
—
0.5
ns
—
Notes:
17. Minimum limits are specified but not tested on Propagation Delays.
18. See “Parameter Measurement Information” in the General Information section.
19. This parameter is specified but not tested.
20. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
5
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Ordering Information CY74FCT16952
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
3.7
CY74FCT16952ETPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
6.3
CY74FCT16952CTPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
10.0
CY74FCT16952ATPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
Ordering Information CY74FCT162952
Speed
(ns)
3.7
7.5
10.0
Ordering Code
Package
Name
Package Type
74FCT162952ETPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162952ETPVC
O56
56-Lead (300-Mil) SSOP
74FCT162952ETPVCT
O56
56-Lead (300-Mil) SSOP
CY74FCT162952BTPVC
O56
56-Lead (300-Mil) SSOP
74FCT162952BTPVCT
O56
56-Lead (300-Mil) SSOP
74FCT162952ATPACT
Z56
56-Lead (240-Mil) TSSOP
Operating
Range
Industrial
Industrial
Industrial
Ordering Information CY74FCT162H952
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
3.7
74FCT162H952ETPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
6.3
74FCT162H952CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
10.0
74FCT162H952ATPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
6
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
7
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Copyright  2000, Texas Instruments Incorporated
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