EM EM6124 Digitally programmable 8 to 25 multiplex lcd controller & driver Datasheet

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EM MICROELECTRONIC - MARIN SA
EM6124
Digitally Programmable 8 to 25 Multiplex
LCD Controller & Driver
Description
The EM6124 is a low power CMOS LCD controller and
driver. The 8, 16, 20 and 24 way multiplex are digitally
programmable by the command byte. One additional line
can be added for Icons or Inverted Video by programming
9, 17, 21 or 25 way multiplex. The display refresh is
handled on chip by an internal RC oscillator via one
selectable 25 x 116 RAM which holds the LCD content
driven by the driver. LCD pixels (or segments) are
addressed on a one to one basis with the 25 x 116 bit
RAM (a set bit corresponds to an activated LCD pixel).
The EM6124 has very low dynamic current consumption,
typically 70 µA at VDD = 2 V, VLCD = 7 V making it
particularly attractive for portable and battery powered
products. The wide operating range on supply voltages
and temperature offers much application flexibility. The
LCD voltage, bias generation and frame frequency are
generated on chip. The clock signal can be used to shift
and to latch the data into the RAM.
Applications
• Mobile phones (GSM, DECT)
• Smart cards
• Automotive displays
• Portable, battery operated products
• Balances and scales, utility meters
Features
• Slim IC for chip-on-board, with gold bumps for Chip-OnGlass and Chip-On-Flex technologies
• Very simple 2-wire interface
• Digitally programmable multiplex rates:
8 x 113, 9 x 112, 16 x 105, 17 x 104, 20 x 101, 21 x 100,
24 x 97, 25 x 96
• No lost pads while row driver from 8 up to 25
• On chip: Voltage multiplier, VLCD up to 7 V (3 to 6 V at
25 °C), 64 VLCD digitally programming steps, 4 VLCD
temperature compensation factors, bias generation, VON
/ VOFF generation, frame frequency, display refresh RAM
• No busy state
• High noise immunity in inputs
• No external components needed, except a VLCD
capacitor
• Digitally reversing row data
• Digitally reversing column data
• Inverting data function
• Blank function
• Set function
• Checker and Inverted Checker functions
• Sleep modes
• Low LCD operating current consumption
• Wide VDD voltage supply range, 2 to 5 V
• Wide temperature range: -40 to + 85 °C
• Direct display of RAM data through the display data
RAM
(To cascade ICs, please see Fig. 19 and contact EM
Microelectronic-Marin S.A.)
Typical Operating Configuration
Pad Assignment
Slim Form Chip
Fig. 1
(To
contact
Power
Supplies, please see
Fig. 20)
Fig. 2
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EM6124
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage range
VDD1,2
Supply high voltage range
VHV
Internal generated VLCD
VLCD
Voltage at DI, DO, CLK, FR,
VLOGIC
RES
Voltage at S1 to S121
VDISP
Storage temperature range
Electrostatic discharge max. to
MIL-STD-883C method 3015.7
with ref. to VSS
Maximum soldering conditions
TSTO
Conditions
-0.3V to 6V
-0.3V to 6V
7V
-0.3V to
VDD+0.3V
-0.3V to
VLCD+0.3V
-65 to +150°C
VSmax
1000V
TSmax
250°C x 10s
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter
Symbol Min
Operating
TA
-40
Temperature
Logic supply voltage VDD1,2
2
Supply high voltage
VHV
2.5
Typ
Max Unit
+85 °C
3
3
5.5
5.5
V
V
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
Electrical Characteristics
VDD1 = VDD2 = 3V, VHV = 2.5 to 5V and TA = -40 to +85°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Min.
Standby supply current
IDD
See note 1
Standby supply current
IHV
See note 1, VLCD step 30 (hexa)
Dynamic supply current
IDD
See note 2
Standby supply current
IHV
See note 3, VLCD Step 00 (hexa)
Sleep mode supply current IDD
Sleep mode supply current IHV
Control Signals DI, CLK,
FR, RES1, RES2
Input leakage
IIN
VDD1,2 or VSS
-1
Input capacitance
CIN
at TA = 25°C
Low level input voltage
VIL
0
High level input voltage
VIH
0.7 VDD1,2
DC output component
±VDC
See table 4
VLCD (internally generated)
VLCD
See note 4
VLCD
VLCD
See note 5
VLCDstep
Typ.
16
65
57
35
0.1
0.1
Max.
22
170
75
140
Units
1
µA
pF
V
V
mV
8
30
6.15
3.15-7.09
62.5
0.3 VDD1,2
VDD1,2
100
µA
µA
µA
µA
µA
µA
V
mV
Table 3
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
All outputs open, DI and CLK at VSS, mux ratio = 24, checker pattern.
All outputs open, DI at VSS, fCLK = 1 MHz, mux ratio = 24, checker pattern.
DI and CLK at VSS, checker pattern, mux ratio = 8.
Initialization bits 18 to 23 = 110000 and initialization bits 10, 11 = 00; laser trimming on request.
Initialization bits 18 to 23 = 000000/111111.
DC Output Component
Output
Row Driver
Column Driver
Frame
n
n+1
n
n+1
Logic Data
0L
0L
0L
0L
⏐
⏐
⏐
⏐
Measured*
VLCD - V2 ⏐
V4 - VSS ⏐
VLCD - V2 ⏐
V3 - VSS ⏐
Guaranteed
V1 = 0.83 x VLCD ± 100 mV
V2 = 0.66 x VLCD ± 100 mV
V3 = 0.34 x VLCD ± 100 mV
V4 = 0.17 x VLCD ± 100 mV
Table 4
*Vx =
Vx (load = +1µA) + Vx (load = -1µA)
2
, mux 24 or 25 programmed, VLCD = 6V, TA = 25°C
Test is performed for multiplex rate = 25. All multiplex rate ≠ 25 are guaranteed by design. If multiplex rate ≠ 25, test will be
performed on request.
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EM6124
Timing Characteristics
VDD1 = VDD2 = 2 to 3V, VHV = 2.5 to 5V and TA = -40 to +85°C
Parameter
Symbol
Test Conditions
Clock high pulse width
tCH
Clock low pulse width
tCL
Clock period
tper
Min.
70
110
550
Typ.
Max.
Units
ns
ns
ns
Reset1 pulse width
t RES1
10
µs
Reset2 pulse width
Clock and FR rise time
Clock and RF fall time
Data input setup time
Data input hold time
FR (internal frame frequency)
t RES2
130
ns
tCR
tCF
tDS
tDH
fFR (note 1)
200
200
20
260
75
ns
ns
ns
ns
Hz
Table 5a
Note 1: EM6124 (n), FR = n times the desired LCD refresh rate where n is the EM6124 mux mode number;
laser trimming on request
See Fig. 17.01 and 17.02 for more details concerning the frame frequency
VDD1 = VDD2 = 3 to 5V, VHV = 2.5 to 5V and TA = -40 to +85°C
Parameter
Symbol
Test Conditions
Clock high pulse width
tCH
Clock low pulse width
tCL
Clock period
tper
Min.
50
55
350
Typ.
Max.
Units
ns
ns
ns
Reset1 pulse width
t RES1
10
µs
Reset2 pulse width
Clock and FR rise time
Clock and RF fall time
Data input setup time
Data input hold time
FR (internal frame frequency)
t RES2
80
ns
tCR
tCF
tDS
tDH
fFR (note 1)
200
200
20
140
75
ns
ns
ns
ns
Hz
Table 5b
Note 1: EM6124 (n), FR = n times the desired LCD refresh rate where n is the EM6124 mux mode number;
laser trimming on request
Timing Waveforms
Fig. 3
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EM6124
1 Bit Interface Description
This 1 bit interface is very simple to use. There are three
modes to load data into the EM6124.
Command byte only mode
To validate this mode, 8 bits must be shifted with bit 3 to
bit 7 set to 1L. This mode is used for blank, set or sleep
mode functions.
Command byte and initialization mode
To validate this mode, 32 bits must be shifted with bit 0
and bit 1 set to 1L. Bit 2 (sleep) can be active or inactive.
Bit 3 to bit 7 (RAM address) can be in any state but it is
important that they are not all simultaneously set to 1L,
otherwise the chip will be in command byte only mode.
Command byte and display information mode
To validate this mode, 128 bits must be shifted, eight first
bits are for command byte, all the other are RAM data
depending of col bit mode and multiplex ratio. There are
also x bits don’t care in each loading depending on the
programming of the chip (see Fig. 4 for more details).
In each RAM’s data loading, the command byte has to be
introduced for the RAM address. Before loading any data
into the RAM the chip has to be initialized.
Command Byte
0
Blank
1
Set
Command Bits 0 to 7
2
3
4
5
6
Sleep
RAM address
7
Table 6
Cmdbit 0: Blank bit forces all column outputs off.
Cmdbit 1: Set bit forces all column output on.
Note: If bit 0 and bit 1 are both to 1L, the chip will be in
initialization mode. See remarks below.
Cmdbit 2: Sleep mode bit, stops the voltage booster and the
internal oscillator, active bit col forces all outputs to VSS.
Cmdbits 3-7: RAM address bits. See table 6.
If Cmdbits 3-7 are set to 1L, EM6124 is in Cmd byte only mode.
Initialization Bits
8
9
Mux Mode
16
M/LSB
17
Video
24
Icon
25
Sleep 2
8
0
0
1
1
Initialization Bits 8 to 15
10
11
12
13
14
15
Temp. Coeff.
Checker Inv.
Col Inv.Row
Checker
Initialization Bits 16 to 23
18
19
20
21
22
23
Step 1 Step 2 Step 3 Step 4 Step 5 Step 6
Initialization Bits 24 to 31
26
27
28
29
30
31
Test 6 Test 5 Test 4 Test 3 Test 2 Fr_ext
Table 7
Mux ratio (Init. bit 8, 9)
9
mux mode
0
8
1
16
0
20
1
24
Table 8
Init.bit 8-9: Mux mode bits. The multiplex ratio is selected by
these two bits. Table 8 shows the corresponding values.
Init.bit 10-11: VLCD temperature coefficient is selected by these
two bits. Table 11 shows the corresponding values.
Init.bit 12: Checker bit gives the possibility to force all outputs
segments in checked form (see Fig. 10 and Fig. 18.14).
Init.bit 13: Inverse Checker bit gives the possibility to force all
outputs segments in inverse checked form (see Fig. 10 and Fig.
18.15).
Init.bit 14: Col bit configures the EM6124 on row and column
driver or column driver only. In this mode the frame frequency
must be external.
Init.bit 15: Row inversion, possibility to inverse the order of the
row outputs (see Table 10 and Fig. 18.12).
Init.bit 16: M/LSB, possibility to inverse the order loading for
RAM data (see Fig. 4).
Init.bit 17: Video bit, possibility to inverse the content of the
RAM. All the 0L pass to 1L and all the 1L pass to 0L (see Fig.
18.11).
Init.bit 18-23: VLCD 64 steps programmation bits. See Fig. 8.
Bit 18 (step 1) for MSB and bit 23 (step 6) for LSB.
Init.bit 24: Icon bit adds one line more to the selected mux mode
ratio for icon segments outputs.
Init.bit 25: Sleep 2. Set all outputs at VSS.
Init.bit 26-30: Must be setted to 0L.
Init.bit 31: Fr_ext give the possibility to supply frame to EM6124
externally. If Fr_ext=1L then FR is input pin and user must
supply signal frame. If Fr_ext=0L then FR is output pin, the
signal frame is internally generated. (Init.bit 14: has the priority)
Reset 1
Power-up: Must be followed by a RESET cycle. After the
reset 1 pulse the LCD controller driver is set to the
following status:
- All outputs at VSS
- Blank & Set (cmdbits 0,1) = 0L
- Sleep mode (cmdbit 2) = 0L
- RAM address (cmdbits 3 to 7) = 0L
- Multiplex ratio (init.bits 8, 9) = 0L
- Temperature coefficient (init.bits 10,11) = 0L
- Checker & Inv.Checker (init.bits 12, 13) = 0L
- Col Mode (init.bit 14) = 1L
- Inv. Row (init.bit 15) = 0L
- M/LSB (init.bit 16) = 1L
- Video (init.bit 17) = 1L
- VLCD step (init.bits 18 to 23) = 0L
- Icon (init.bit 24) = 0L
- Sleep 2 (init.bit 25) = 1L
- The content of the RAM remains unchanged
- Frame internally generated (init.bit 31) = 0L
An initialization should take place after reset (32 bits
sent).
Pin Assignment
Name
S1..S121
FR
DI
DO
CLK
Function
LCD outputs, see Fig.4
AC I/O signal for LCD driver output
Serial data input
Serial data output
Data clock input
RES1
General reset
RES2
VLCD
VDD1
VDD2
VHV
VSS
Reset the serial interface counter
Internal generated voltage output
Power supply for logic
Power supply for analogic
Power supply for high voltage
Supply GND
Table 9
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EM6124
Data Transfer Cycle
Fig. 4
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EM6124
Output Row Assignments
Row
RAM Address
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Mu 8
Inv. Row
Bit
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Bit
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
Bit
5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Bit
6
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Bit
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Mux 8
+ Icon
Inv. Row
Mux Mode
Mux 16
Mux 20
+ Icon
Inv. Row
Inv. Row
Mux 16
Inv. Row
Mux 20
+ Icon
Inv. Row
Mux 24
Inv. Row
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1
S2
S3
S4
S13
S14
S15
S16
S16
S15
S14
S13
S4
S3
S2
S1
S1
S2
S3
S4
S13
S14
S15
S16
S17
S17
S16
S15
S14
S13
S4
S3
S2
S1
S1
S2
S3
S4
S5
S6
S7
S8
S13
S14
S15
S16
S17
S18
S19
S20
S20
S19
S18
S17
S16
S15
S14
S13
S8
S7
S6
S5
S4
S3
S2
S1
S1
S2
S3
S4
S5
S6
S7
S8
S13
S14
S15
S16
S17
S18
S19
S20
S21
S21
S20
S19
S18
S17
S16
S15
S14
S13
S8
S7
S6
S5
S4
S3
S2
S1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
Mux 24
+ Icon
Inv. Row
0
1
S1
S25
S24
S2
S23
S3
S22
S4
S21
S5
S20
S6
S19
S7
S18
S8
S17
S9
S16
S10
S15
S11
S14
S12
S13
S13
S12
S14
S11
S15
S10
S16
S9
S17
S8
S18
S7
S19
S6
S20
S5
S21
S4
S22
S3
S23
S2
S24
S1
S25
Table 10
Command Byte Only Mode
time
In this mode only 8 bits have to be shifted
into the EM6124 with address bits to logic 1.
Fig. 5
Fr_ext
Temp. Coef
Mux mode
Command Byte and Initialization Mode
Fig. 6
Command Byte and Display Information Mode
Fig. 7
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EM6124
Typical VLCD Programming
Checker and Checker Inverse
A fast check display can be easily created setting
initialization bits 12 and 13 (called “Checker” and “Inv.
Checker”). The display is completely checked with only 2
initialization sequences, one “Checker” and one “Inv.
Checker”. For Checker, the pattern fills the display with
alternately ON and OFF pixels as shown in Fig. 10. For
Inv. Checker, everything is inverted (see Fig.18.14 and
18.15).
Pattern of Checker Mode
Fig. 10
Internally Generated VLCD versus Temperature
Fig. 8
Temperature Control
Due to the temperature dependency of liquid cristals
viscosity the LCD controlling voltage VLCD must be
increased for lower temperatures to maintain optimal
contrast. The EM6124 is available with 4 different
temperature coefficients (see Fig. 9). The coefficient is
selected by 2 bits in the initialization code TC bits 10 and
11. Table 11 shows the typical values of the different
temperature coefficients. They are proportional to the
programmed VLCD.
Typical Values of the Temperature Coefficients
Bit 10, Bit 11
Value
Unit
00
mV/°C
-0.2 x VLCD
01
-0.52 x VLCD
mV/°C
-1.16 x VLCD
10
mV/°C
-1.82 x VLCD
11
mV/°C
Fig. 11
Table 11
Temperature Coefficients
Fig. 9
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EM6124
Display Functions
Bit
State
Logic 0
8 - 9: Mux Mode
10 -11:Temp.Coeff.
12: Checker
13: Inv. Checker
14: Col
15: Inv. Row
16: M/ LSB
17: Video
18 - 23: VLCD step
24: Icon
25: Sleep
26 - 30:
31: Fr_ext
Logic 1
See table 8
See table 11
Inactive
Inactive
Column driver only
Chess display
Inverse chess display
Row and column driver
Increment rows
(example for mux 24:
row 1, 2, 3, ... , 24, 1, 2, ...)
Loading in LSB mode
Decrement rows
(example for mux 24:
row 24, 23, 22, ... ,2 ,1, 24, 23, ...)
Loading in MSB mode
Inverse content of RAM
Inactive
See Fig. 8
Add one line more to selected mux mode
All outputs at VSS
Must be at 0L
External frame to be supplied
Inactive
Inactive
Frame internally generated
Table 12
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EM6124
Block Diagram
Fig. 12
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EM6124
LCD Voltage Bias Levels
LCD Drive
LCD Bias
Type
Configuration
EM6124 (24)
n=24
1:24 MUX
6 Levels
n n +1
EM6124 (20)
n=20
1:20 MUX
6 Levels
n n +1
EM6124 (16)
n=16
1:16 MUX
1/5 Bias
6 Levels
EM6124 (8)
n=8
1:8 MUX
1/4 Bias
6 Levels
VOP
VOFF (rms)
VON (rms)
VOFF (rms)
( )
2( n − 1)
= 4.68
( )
2( n − 1)
= 4.39
( )
2( n − 1)
= 4.08
n n +1
4
1+
3
n
2
n +1
n −1
2
n +1
n −1
2
n +1
n −1
= 3.4
= 1.230
= 1.255
= 1.291
n − 15
= 1.446
n+3
Table 13
Optimum LCD Bias Voltages
Multiplex
Rate
1:24
1:20
1:16
1:8
V1
VLCD
1
1
1
1
V2
V3
0.930
0.660
0.340
0.817
0.634
0.366
0.800
0.600
0.400
0.750
0.500
0.250
VLCD > V1 > V2 > V3 > V4 > VSS
V4
VSS
0.170
0.183
0.200
-
0
0
0
0'
The values in the above table are given in reference to VLCD eg. 0.5 means 0.5 x VLCD
Table 14
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EM6124
Row and Column Multiplexing Waveform EM6124 (8)
VCP = VLCD - VSS, VSTATE = VCOL - VROW
Frame n
V LCD
1
2
3
4
5
Frame n+1
6
7
8
1
2
3
4
5
6
7
8
State 1
State 2
V1
Row 1
V2=V3
V4
V SS
V LCD
V1
Row 2
V2=V3
V4
V SS
V LCD
V1
Col 1 V2=V3
V4
V SS
V LCD
V1
Col 2 V2=V3
V4
V SS
V OP
0.75 VOP
0.5 V OP
0.25 V OP
State 1
0
-0.25 VOP
-0.5 VOP
-0.75 V OP
-V OP
V OP
0.75 VOP
0.5 V OP
0.25 V OP
State 2
0
-0.25 VOP
-0.5 VOP
-0.75 V OP
-V OP
Fig. 13
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EM6124
Row and Column Multiplexing Waveform EM6124 (16)
VCP = VLCD - VSS, VSTATE = VCOL - VROW
Frame n
VLCD
1
2
3
4
... 14 15 16 1
Frame n+1
2
3
4
... 14 15 16
State 1
(ON)
State 2 (OFF)
V1
Row 1
V2
V3
V4
VSS
VLCD
V1
Row 2
V2
V3
V4
VSS
VLCD
V1
Col 1
V2
V3
V4
VSS
VLCD
V1
Col 2
V2
V3
V4
VSS
VOP
0.8 VOP
0.6 VOP
0.4 VOP
0.2 VOP
State 1
0
-0.2 VOP
-0.4 VOP
-0.6 VOP
-0.8 VOP
-VOP
VOP
0.8 VOP
0.6 VOP
0.4 VOP
0.2 VOP
State 2
0
-0.2 VOP
-0.4 VOP
-0.6 VOP
-0.8 VOP
-VOP
Fig. 14
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EM6124
Row and Column Multiplexing Waveform EM6124 (20)
VCP = VLCD - VSS, VSTATE = VCOL - VROW
Frame n
VLCD
1
2
3
4
5
... 17 18 19 20
Frame n+1
1
2
3
4
... 17 18 19 20
State 1
(OFF)
V1
Row 1
5
State 2 (ON)
V2
V3
V4
VSS
VLCD
V1
Row 2
V2
V3
V4
VSS
VLCD
V1
Col 1
V2
V3
V4
VSS
VLCD
V1
Col 2
V2
V3
V4
VSS
VOP
0.635 VOP
0.183 VOP
State 1
0
-0.183 VOP
-0.635 VOP
-VOP
VOP
0.635 VOP
0.183 VOP
State 2
0
-0.183 VOP
-0.635 VOP
-VOP
Fig. 15
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EM6124
Row and Column Multiplexing Waveform EM6124 (24)
VCP = VLCD - VSS, VSTATE = VCOL - VROW
Frame n
V LCD
1
2
3
4
5
6
... 20 21 22 23 24
Frame n+1
1
2
3
4
5
... 20 21 22 23 24
State 1
(OFF)
V1
Row 1
6
State 2 (ON)
V2
V3
V4
V SS
V LCD
V1
Row 2
V2
V3
V4
V SS
V LCD
V1
Col 1
V2
V3
V4
V SS
V LCD
V1
Col 2
V2
V3
V4
V SS
V OP
0.661 VOP
0.170 VOP
State 1
0
-0.170 V OP
-0.661 VOP
-V OP
V OP
0.661 VOP
0.170 VOP
State 2
0
-0.170 V OP
-0.661 VOP
-V OP
Fig. 16
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EM6124
Functional Description
Supply Voltage VDD1, VDD2, VHV, VLCD, VSS
The voltage between VDD1 and VSS is the supply voltage
for the logic and the interface. The voltage between VDD2
and VSS is the supply voltage for the analogic. VDD1 and
VDD2 must be the same voltage and, in order to guarantee
the best functioning, VDD1 and VDD2 have to be separately
connected to the PCB (see Fig. 19). The voltage VLCD is
internally generated for the supply voltage of the LCD and
is used for the generation of the internal LCD bias level.
An external capacitor of 1 µF must be connected between
VLCD and VSS. Table 15 shows the relationship between
V1, V2, V3, V4 for a programmed multiplex rate. Note that
VLCD > V1 > V2 > V3 > VSS for the EM6124 8 mux
programmed, and for the EM6124 16, 20, 24 mux
programmed VLCD > V1 > V2 > V3 > V4 > VSS. The
voltage between VHV and VSS is the supply voltage for
high voltage part of the EM6124. An external VLCD may
also be used by connecting a power supply and
programming a lower VLCD voltage during initialization.
Data Input
The data input pin, DI, is used to load serial data into the
EM6124. The normal serial data word length is 128 bits.
32 and 8 bits are also available in a special mode (see 1
Bit Interface Description). The command byte is loaded
first and then the segment data bits (see Fig. 4).
RES1 Input
Reset is accomplished by applying an external RES1
pulse (active low). When reset occurs within the specified
time, all internal register are reset however the content of
the RAM is still unchanged. The state after reset is
described on page 4.
RES2 Input
Reset is accomplished by applying an external RES2
pulse (active low). When reset occurs within the specified
time, the internal counter for serial interface is reset. The
counter of the serial interface for data inputs is ready for a
new loading of data. This reset 2 does not change the
content of the RAM neither the content of the command
and the initialization bits. To avoid trouble in case of
software interrupt of the MPU during data loading, this
function can be used.
On power up the data in the shift registers, the display
RAM, the sequencer driving the 8/16/20/24 rows and the
121 bit display latches are undefined.
CLK Input
The clock input is used to clock the DI serial data into the
EM6124.
FR Input / Output
The frame frequency is realized by an internal oscillator
with a typical value of 75 Hz. The internal row frequency
changes with the number of rows (Frow = 75 x n, where n =
8, 16, 20, 24). When bit 14 ( Col ) is inactive (active low),
the frame frequency is given by the internal oscillator. This
frequency can be measured on the I/O FR. When bit 14
( Col ) is active (active low) or bit 31 (Fr_ext) is active
(active high), the frame frequency is external then the
frequency is given directly by the FR input to the row and
column driver (see Fig. 16 and 17 for more details
concerning the frame frequency).
Col
0
0
1
1
Fr_ext
0
1
0
1
Pad Frame
input - ext frame
input - ext frame
output - int frame
input - ext frame
Driver Outputs S1 to S116
There are 121 LCD driver outputs on the EM6124. The
output assignments depend on the chosen mux mode
ratio (init. bits 8, 9) and the Col function (init. bit 14).
When init. bit 14 ( Col ) is active, all 116 outputs function
as column drivers. Table “Output Row Assignments” and
Fig. 4 describe exactly the correspondent data to the
output of the chip. There is one to one relationship
between the display RAM and the LCD driver outputs.
Each pixel (segment) driven by the EM6124 on the LCD
has a display RAM bit which corresponds to it. Setting the
bit turns the pixel “on” and Clearing it turns “off”.
For chip-on-glass better performances can be obtained by covering the
backside of the chip.
Typical Frame Frequency at TA = 25°C
Typical Frame Frequency at VDD = 3V
Fig. 17.02
Fig. 17.01
Power-Up
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EM6124
Functional Description for Versions
EM6124 is available in two different versions “V1” and “V2”:
• EM6124V1
• EM6124V2
The difference is the effect of 32 bits initialization procedure. Basically the sequencer block (see block diagram page 9) is
used for refresh the rows of the display RAM block, depending of the version (“V1” or “V2”) the sequencer block could be
reset or not by the 32 bits initialization procedure.
Functional description EM6124V1
The block sequencer is reset when 32 bits initialization is sent to EM6124V1. Internal signal named “RES32” reset the
sequencer, the row1 will be selected during next frame period.
FR
Sequencer
Display RAM
RES32 signal
*reset sequencer in “V1” version
CLK
DI
Interface
CMD REGISTERS
INI REGISTERS
Internal “RES32” signal is used to synchronise the sequencer in cascaded applications.
Functional description EM6124V2
Disable “RES32” in the sequencer block
FR
Sequencer
Display RAM
RES32 signal
*reset disable in “V2” version
CLK
DI
Interface
CMD REGISTERS
INI REGISTERS
Internal “RES32” signal is disabled, this version is not recommended for cascaded applications.
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EM6124
Application Example
These tables/figures show how to use the EM6124 with a given initialization. Rows “Data” show the logical value to affect
pad DI for each falling edge of pad CLK. A reset cycle pad RES1 at OL is required before sending data.
0
1
1
1
2
0
3
0
4
0
5
0
6
0
7
0
8
1
Bits 0,1 = 1,1:
initialization is programmed
Bit 2 = 0:
no sleep mode
Bits 3 to 7:
don't care in this case
(not 11111)
9
1
10
0
11
1
12
0
13
0
14
1
15
0
16
0
17
1
18
1
19
1
20
0
21
0
22
0
23
0
24
1
25
0
26
0
27
0
28
0
29
0
30
0
31
0
Bits 8,9,24 = 1,1,1: mux mode 24 + icon; 25 rows driven
Bits 10,11 = 0,1: temperature coefficient = -(0.52•VLCD) mV/°C
Bits 12,13 = 0,0: no checker or inv. checker functions
Bit 14 = 1: row and column driver configuration
Bit 15 = 0: row 1 of the RAM displayed on S1, row 2 on S2, … and row 25 on S25
Bit 16 = 0: first data sent displayed on S26, last one on S121
Bit 17 = 1: 1L in the RAM corresponds to a pixel "ON"
Bit 18 to 23 = 1,1,0,0,0,0 :
programmed VLCD = 3.15 + (1 • 32 + 1 • 16 + 0 • 8+0 • 4 + 0 • 2 + 0 • 1) • 0.0625 = 6.150V
Bit 25 = 0: no sleep
Bit 26 to 31 = 0,0,0,0,0,0,0: every test bit must be set to 0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Result
Description
Bit No
Data
Initialization bits or display data
= undefined
First Initialization
Command byte
= pixel "OFF"
= pixel "ON"
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S118
S119
S120
S121
S23
S24
S25
Fig. 18.01
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
16
0
17
0
18
0
19
0
20
0
21
0
22
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
Bits 8 to 103 = 0,0,…,0: first row of the RAM is loaded with 0,0,…,0
Bits 104 to 127 = don't care
no set, no blank, no sleep
Bits 3 to 7 = 0,0,0,0,0:
data sent to row 1 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
23
0
Write Row 1
Description
Bit No
Data
Fig. 18.02
Table 15
(continued on next pages)
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EM6124
Application Example continued
Command byte
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
8
0
9
1
10
1
11
1
12
1
13
0
14
0
15
1
16
0
17
0
18
0
19
1
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
2nd row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,0,0,1:
data sent to row 2 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 2
Description
Bit No
Data
Initialization bits or display data
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
Fig. 18.03
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
0
8
0
9
1
10
0
11
0
12
0
13
0
14
0
15
1
16
1
17
0
18
1
19
1
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
3rd row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,0,1,0:
data sent to row 3 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 3
Description
Bit No
Data
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
Fig. 18.04
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
1
8
0
9
1
10
0
11
0
12
0
13
0
14
0
15
1
16
0
17
1
18
0
19
1
20
0
21
0
22
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
4th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,0,1,1:
data sent to row 4 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
23
0
Write Row 4
Description
Bit No
Data
Fig. 18.05
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EM6124
Command byte
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
0
8
0
9
1
10
1
11
1
12
1
13
0
14
0
15
1
16
0
17
0
18
0
19
1
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
5th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,1,0,0:
data sent to row 5 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 5
Description
Bit No
Data
Initialization bits or display data
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
Fig. 18.06
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
1
8
0
9
1
10
0
11
0
12
0
13
0
14
0
15
1
16
0
17
0
18
0
19
1
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
6th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,1,0,1:
data sent to row 6 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 6
Description
Bit No
Data
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
Fig. 18.07
0
0
1
0
2
0
3
0
4
0
5
1
6
1
7
0
8
0
9
1
10
0
11
0
12
0
13
0
14
0
15
1
16
0
17
0
18
0
19
1
20
0
21
0
22
0
24
0
25
0
---
125 126 127
0
0
0
Bits 0,1,2 = 0,0,0:
7th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,1,1,0:
data sent to row 7 of the RAM
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
23
0
Write Row 7
Description
Bit No
Data
Fig. 18.08
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EM6124
Command byte
Bit No
Data
0
0
1
0
2
0
3
0
4
0
5
1
Initialization bits or display data
6
1
7
1
8
0
9
1
10
1
11
1
12
1
13
0
14
0
15
1
16
0
17
0
18
0
19
1
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 8
Description
Bits 0,1,2 = 0,0,0:
8th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,0,1,1,1:
data sent to row 8 of the RAM
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
Fig. 18.09
Bit No
Data
0
0
1
0
2
0
3
0
4
1
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
16
0
17
0
18
0
19
0
20
0
21
0
22
0
23
0
24
0
25
0
---
125 126 127
0
0
0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Write Row 9
Description
Bits 0,1,2 = 0,0,0:
9th row of the RAM is loaded
no set, no blank, no sleep
Bits 3 to 7 = 0,1,0,0,0:
data sent to row 9 of the RAM
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S23
S24
S25
1
1
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
10
0
11
1
12
0
13
0
14
1
15
0
16
0
17
0
18
1
19
1
20
0
21
0
22
0
23
0
24
1
25
0
26
0
27
0
28
0
29
0
30
0
31
0
Bit 17 = 0: 1L in the RAM corresponds to a pixel "OFF"
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S23
S24
S25
Initialization in Video Inverse Mode
Bits 0,1 = 1,1:
no set, no blank, no sleep
Bit 2 = 0
Bits 3 to 7 = don't care in this
case (not 1,1,1,1,1)
Result
0
1
Description
Fig. 18.10
Bit No
Data
Fig. 18.11
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EM6124
0
1
1
1
2
0
3
0
4
0
5
0
6
0
7
0
Bits 0,1 = 1,1:
no set, no blank, no sleep
Bit 2 = 0: no sleep mode
Bits 3 to 7 = don't care in this
case (not 1,1,1,1,1)
Initialization bits or display data
8
1
9
1
10
0
11
1
12
0
13
0
14
1
15
1
16
0
17
1
18
1
19
1
20
0
21
0
22
0
23
0
24
1
25
0
26
0
27
0
28
0
29
0
30
0
29
0
30
0
31
0
Bit 17 = 1: 1L in the RAM corresponds to a pixel "ON"
Bit 15 = 1: row 1 (address "00000") displayed on S25
row 2 (address "00001") displayed S24
….,row 25 (address "11000") displayed on S1
Initialization in Inverse Row Mode
Bit No
Data
Description
Command byte
S1
S2
S3
= undefined
= pixel "OFF"
S118
S119
S120
S121
= pixel "ON"
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
1
1
2
0
3
0
4
0
5
0
6
0
7
0
Bits 0,1 = 1,1:
initialization is programmed
Bit 2 = 0: no sleep mode
Bits 3 to 7 = don't care in this
case (not 1,1,1,1,1)
8
1
9
1
10
0
11
1
12
0
13
0
14
1
15
1
16
0
17
1
18
1
19
0
20
1
21
0
22
0
23
0
24
1
25
0
26
0
27
0
28
0
31
0
Bit 15 = 1: row 1 (address '00000') displayed on S25, row 2 (address '00001') displayed S24,
…, and row 25 (address '11000') displayed on S1
Bit 17 = 1: 1L in the RAM corresponds to a pixel "ON"
Bits 18 to 23 = 1,0,1,0,0,0 :
programmed VLCD = 3.15 + (1 • 32 + 0 • 16 + 1 • 8 + 0 • 4 + 0 • 2 + 0 • 1) • 0.0625 = 5.650V
S1
S2
S3
= undefined
= pixel "OFF"
S118
S119
S120
S121
= pixel "ON"
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
Result
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
Initialization to change VLCD (Contrast)
0
1
Description
Fig. 18.12
Bit No
Data
1
1
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
10
0
11
1
12
1
13
0
14
1
15
0
16
0
17
1
18
1
19
1
20
0
21
0
22
0
23
0
24
1
25
0
26
0
27
0
28
0
29
0
30
0
31
0
Bit 12 = 1 : checker pattern on the LCD, don't care for the RAM
Bit 17 = 1 : 1L in the RAM corresponds to a pixel "ON"
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S23
S24
S25
Initialization in Checker Mode
Bits 0,1 = 1,1:
initialization is programmed
Bit 2 = 0
Bits 3 to 7 = don't care in this
case (not 1,1,1,1,1)
Result
0
1
Description
Fig. 18.13
Bit No
Data
Fig. 18.14
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EM6124
0
1
1
1
2
0
3
0
4
0
5
0
6
0
7
0
Bits 0,1 = 1,1:
initialization is programmed
Bit 2 = 0
Bits 3 to 7 = don't care in this
case (not 1,1,1,1,1)
Initialization bits or display data
8
1
9
1
10
0
11
1
12
0
13
1
14
1
15
0
16
0
17
1
18
1
19
1
20
0
21
0
22
0
23
0
25
0
26
0
27
0
28
0
29
0
30
0
31
0
Bit 13 = 1 : checker pattern on the LCD, don't care for the RAM
Bit 17 = 1 : 1L in the RAM corresponds to a pixel "ON"
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
Result
24
1
= undefined
= pixel "OFF"
= pixel "ON"
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S23
S24
S25
Initialization in Inverse Checker Mode
Bit No
Data
Description
Command byte
1
1
2
0
3
1
4
1
5
1
6
1
Bits 0,1 = 0,1:
blank is programmed
Bit 2 = 0
Bits 3 to 7 = 1,1,1,1,1:
command byte only mode
7
1
Result
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
Command Byte only: Set
0
0
Description
Fig. 18.15
Bit No
Data
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S23
S24
S25
1
0
2
0
3
1
4
1
5
1
6
1
7
1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
= undefined
= pixel "OFF"
= pixel "ON"
Command Byte only: Blank
Bits 0,1 = 1,0:
blank is programmed
Bit 2 = 0
Bits 3 to 7 = 1,1,1,1,1:
command byte only mode
Result
0
1
Description
Fig. 18.16
Bit No
Data
S118
S119
S120
S121
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S23
S24
S25
Fig. 18.17
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EM6124
Applications
Two EM6124 work in parallel to drive up to 50 rows x 96 columns or 25 rows x 212 columns as below
By connecting the VLCD bias outputs as shown, the pixel load is averaged across all the drivers. The effective bias
level source impedance is the parallel combination of the total number of drivers.
* VDD1 and VDD2 have been connected together.
Fig. 19
Contacting Power Supply
In order to guarantee the best
functioning VDD1 and VDD2 have to
be connected separately on the
PCB, if possible
Fig. 20
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EM6124
Applications
Recommended flow to use EM6124 with external VLCD power supply.
Power Supplies:
-VHV pad should be connected to GND.
- Power should be applied first on VDD1,2 then on VLCD (external).
Voltage (V)
Ext
VLCD
--VDD1,2
___
time
VLCD
EXT Power Supply
EM6124
Initialization sequence method:
The software should be adapted to avoid high current consumption.
If external Vlcd is lower than the internally generated Vlcd then EM6124 will understand that the level set by the user is not
achieved and it will increase the current to achieve the requested level.
For this raison Vlcd step (bit18 to 23) should be set to “000000b” which means 3V then the minimum voltage.
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EM6124
Dimensions of Chip Form and Bumped Die
All dimensions in micron
Thickness:
15 mils
Bump size:
LCD output pads = 50 x 100 micron, input/output pads = 102 x 102 micron
Bump height:
17.5 micron
Bump hardness:
50 Vickers
Chip size:
[X x Y] 7930 x 1493 micron or 312 x 59 mils
Note:
The origin (0,0) is the lower left coordinate of center pads.
The lower left corner of the chip shows distances to origin.
Fig. 21
Ordering Information
When ordering, please specify the complete Part Number
Part Number
EM6124V1WP15E
EM6124V2WP15E
Recommended for cascaded
applications (see p.16)
Yes
No
Die Form
Bumping
Die in waffle pack, 15 mils thickness
Die in waffle pack, 15 mils thickness
With gold bumps
With gold bumps
For other delivery form in die (with or without bumps), please contact EM Microelectronic-Marin S.A.
Minimum order quantity might apply.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM
Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice
at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
© EM Microelectronic-Marin SA, 08/04, Rev. G
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