Infineon Technologies preliminary ICE1PD265G Power Factor Controller + Cool- MOS: BoostSET IC for High Power Factor and low THD =IC for sinusoidal line-current consumption =Controller and CoolMOS within one package =P-DSO-16-10 =Power factor achieves nearly 1 = Controls boost converter as active harmonic filter for low THD Start up with very low current consumption =Zero current detector for discontinuous operation mode Output overvoltage protection =Output undervoltage lockout =Internal start up timer =Totem pole output with active shut down =Internal leading edge blanking LEB =Very low comparator and multiplier offsets for universal input applications =High sophisticated amplifier minimizes distortion inteferences caused by MOSFET switching AC The ICE1PD265G IC controls a boost converter in a way that sinusoidal current is taken from the single phase line supply and stabilized DC voltage is available at the output. CoolMOS and controller are placed together in one package. This active harmonic filter limits the harmonic currents resulting from the capacitor pulsed charge currents during rectification. The power factor which descibes the ratio between active and apparent power is almost one. Line voltage fluctuations can be compensated very efficiently RF-Filter and Rectifier DC Output Voltage Controller ICE CoolMOS 1PD265G GND Type Ordering Code ICE1PD265G Infineon Tech Package P-DSO-16-10 PCI Group 10.09.01 1 Infineon Technologies preliminary ICE1PD265G Pin Connections Pin Symbol Function 1 GND Ground 2 VSENSE Voltage amplifier inverting input 3 VAOUT Voltage amplifier output 4 MULTIN Multiplier input 5 n.c. 6 DRAIN 650V Drain 7 DRAIN 650V Drain 8 DRAIN 650V Drain 9 DRAIN 10 P-DSO-16-10 1 GND 16 GND 2 VSENSE 15 DETIN 3 VAOUT 14 VCC 4 MULTIN 13 ISENSE 5 n.c. 12 n.c. 650V Drain 6 DRAIN 11 DRAIN DRAIN 650V Drain 7 DRAIN 10 DRAIN 11 DRAIN 650V Drain 8 DRAIN 9 DRAIN 12 n.c. 13 ISENSE Current sense input + Source 14 VCC Positive voltage supply 15 DETIN Zero current detector input 16 GND Ground Do not touch DRAIN pins on application board: 650V Pin Description Pin1,16 GND (Ground) The GND pins are internally connected via the lead frame Pin 2 VSENSE (voltage amplifier inverting input) VSENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to VAOUT the internal error amplifier acts as an integrator. Pin 3 VAOUT (voltage amplifier output) VAOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage is clamped internally at 5V. Input voltage less then 2.2V shuts the gate driver down. If the current flowing into this pin is exceeding an internal threshold the multiplier output voltage is reduced to prevent the MOSFET from overvoltage damage. Pin 4 MULTIN (multipier input) MULTIN is the second multiplier input and is connected via a resistive divider to the rectifier output voltage. Pin 5, 12 not connected Pin 6,7,8,9,10,11 DRAIN (drain connection of internal CoolMOS) The DRAIN pins are internally connected via the leadframe. Be aware of 650V input voltage! Infineon Tech PCI Group 10.09.01 2 Infineon Technologies preliminary ICE1PD265G Pin 13 ISENSE (current sense input and CoolMOS source) Controller current sense input and CoolMOS source are internaly connected via bonds. ISENSE should be connected to an external sense resistor controlling the CoolMOS source current. The input is internally clamped at -0.3V to prevent negative input voltage interaction. A leading edge blanking circuitry suppresses voltage spiks when turning the MOSFET on. Pin 14 Vcc (Positive voltage supply) If Vcc exceeds the turn-on threshold the IC is switched on. When Vcc falls below the turn-off threshold it is switched off and power consumption is very low. An auxilliary winding is charging a capacitor which provides the supply current. A second 100nF ceramic capacitor should be added to Vcc to absorbe supply current spikes required to charge the MOSFET gate capacitance. Pin 15 DETIN (Zero current detector input) DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current. Block Diagram VCC GND clamp detin 20V + Reference Voltage UVLO 10V 12.5V 1.0 V - 0.2V DRAIN DETIN + Detector 1.5 V - Restart Timer tres=150 us Cool MOS Enable + 2.2V RS Flip-Flop tdVA=2us - Inhibit time delay Inhibit 10 Gate Drive + 2.5V + Voltage Amp multout Multiplier 1V - tdsd=70n s Current Comp + + - OVR 10p clamp VA VSENSE Infineon Tech 20k uvlo active shut down tLEB=150ns LEB VAOUT MULTIN PCI Group ISENSE 10.09.01 3 Infineon Technologies preliminary ICE1PD265G Functional Description Introduction Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: The apparent power is higher than the real power that means low power factor condition, the current spikes are non sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary. With the ICE1PD265G preconverter a sinusoidal current is achieved which varies in direct instantaneous proportional to the input voltage half sine wave and so provides a power factor near 1. This is due to the appearence of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC555 standard requirements. IC Description The ICE1PD265G contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer, an undervoltage lockout circuitry and last not least a CoolMOS transistor. Voltage Amplifier With an external capacitor between VSENSE and VAOUT the voltage amplifier forms an integrator. The integrator monitors the average output voltage over several line cycles. Typically the integrators bandwidth is set below 20 Hz in order to suppress the 100 Hz ripple of the rectified line voltage. The voltage amplifier is internally compensated and has a gain bandwidth of 3 MHz and a phase margin of 80 degrees. The non-inverting input is biased internally at 2.5V. The output is directly connected to the multiplier input. The gate drive is disabled when VSENSE voltage is less than 0.2 V or VAOUT voltage is less than 2.2 V. If the MOSFET is placed nearby the controller switching inteferences have to be taken into account. The output of the voltage amplifier is designed in a way to minimize these inteferences. Overvoltage Regulator Because of the integrators low bandwidth fast changes of the output voltage can’t be regulated whithin an adequate time. Fast output changes occure during initial start-up, sudden load removal, or output arcing. While the integrators differential input voltage remains zero during this fast changes a peak current is flowing through the external capacitor into pin VAOUT. If this current exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output voltage. As a result the on time of the MOSFET is reduced. Infineon Tech PCI Group 10.09.01 4 Infineon Technologies preliminary ICE1PD265G Multiplier The one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. Special efforts are made to assure universal line applications with respect to a 90 to 270 V AC range. The multiplier output is internally clamped at 1.0V. So the MOSFET is protected against critical operating during start up. Current sense comparator, LEB and RS Flip-Flop An external sense resistor transferes the source current of the MOSFET into a sense voltage.The multiplier output voltage is compared with this sense voltage. To protect the current comparator input from negative pulses a current source is inserted which sends current out of the ISENSE pin every time when ISENSE is falling below ground potential. The switch-on current peak of the MOSFET is blanked out via a resistor-capacitor circuit with a blanking time of typically 220ns. Therefore better THD is achieved at low load conditions. The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle (double pulse suppression). Zero Current Detector The zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time of the MOSFET is initiated immediately when the inductor current has reached zero. This diminishes the revers recovery losses of the boost converter diode. The MOSFET is switched off when the voltage drop of the shunt resistor reaches the voltage level of the multipler output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current. To prevent false tripping the zero current detector is designed as a Schmitt-Trigger with a hysteresis of 0.5V. An internal 5V clamp protects the input from overvoltage breadkdown, a 0.6V clamp prevents substrate injection. An external resistor has to be used in series with the auxiliary winding to limit the current through the clamps. Restart Timer If the MOS is off for more than 150us a restart impulse is generated by the restart timer. Infineon Tech PCI Group 10.09.01 5 Infineon Technologies preliminary ICE1PD265G Undervoltage Lockout An undervoltage lockout circuitry switches the IC on when Vcc reaches the upper threshold VCCH and switches the IC off when Vcc is falling below the lower threshold VCCL. During start up the supply current is less then 100uA. An internal voltage clamp has been added to protect the IC from Vcc overvoltage condition. When using this clamp special care must be taken on power dissipation. Start up current is provided by an external start up resistor which is connected from the AC line to the input supply voltage Vcc and a storage capacitor which is connected from Vcc to ground. Be aware that this capacitor is discharged befor the IC is plugged into the application board. Otherwise the IC can be destroyed due to the high capacitor voltage. Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see application circuit). CoolMOS The CoolMOS is designed for very low RDSon=to reduce power dissipation. Infineon Tech PCI Group 10.09.01 6 Infineon Technologies preliminary ICE1PD265G Signal Diagrams IVAOUT IOVR DETIN DRAIN LEB VISENSE multout Icoil Infineon Tech PCI Group 10.09.01 7 Infineon Technologies preliminary ICE1PD265G Absolute maximum ratings Parameter Symbol Min Max Unit Supply + Zener Current Icc+Iz - 20 mA Supply Voltage VCC -0.3 Vz V -0.3 6.5 V 30 mA mA VAOUT=4V,VSENSE=2.8V VAOUT=0V,VSENSE=2.3V t<1ms 10 mA mA DETIN > 6V DETIN< 0.4V Voltage at Pin 2,4,13 Current into Pin 3 IVAOUT -10 Current into Pin 15 IDETIN -10 Remark Vz=Zener Voltage Icc+Iz=20mA Voltage at Pin 6- 11 VDRAIN 650 Continuous Drain Current ID 3.2 2 A A TC=25°C TC=100°C Avalanche Energy EAr 0.2 mJ repetitive 2000 V MIL STD 883C method 3015.6, 100pF,1500τ ESD Protection TJ=115°C Storage Temperature Tstg -50 150 °C Operating Junction Temperature TJ -25 150 °C Thermal Resistance Junction-Ambient RthJA 120 K/W Infineon Tech PCI Group P-DSO-16-10 10.09.01 8 Infineon Technologies preliminary ICE1PD265G Characteristics Unless otherwise stated, -40°C<Tj <150 °C, VCC = 14.5V Parameter Symbol min. typ. max. Unit Test Condition Start-Up circuit Zener Voltage Vz Start-up supply current 18 20 22 V Icc+Iz=18mA ICCL 20 100 uA Vcc=10V Operating supply current ICCH 4 6 mA Output low Vcc Turn-ON threshold VCC ON 12 12.5 13 V Vcc Turn-OFF threshold VCC OFF 9.5 10 10.5 V Vcc Hysteresis VCCHY 2.5 Voltage Amplifier Voltage feedback Input Threshold VFB 2.45 Line regulation VFBLR Open Loop Voltage Gain1) GV 100 Unity Gain Bandwidth1) BW 5 MHz Phase Margin1) M 80 Degr Bias current VSENSE IBVSENSE Enable Threshold -1.0 2.5 2.55 V Pin1 connected with Pin2 2 5 mV VCC=12V to 16V dB -0.3 uA VVSENSEE 0.2 V Inhibit Threshold Voltage VVAOUTI 2.2 V VISENSE= -0.1V Inhibit Time Delay tdVA 3 us VISENSE= -0.1V Output Current Source IVAOUTH -6 mA VAOUT=0V VSENSE=2.3V,t<1ms Output Current Sink IVAOUTL 30 mA VAOUT=4V VSENSE=2.8V, t<1ms Upper Clamp Voltage VVAOUTH 5.4 V VSENSE=2.3V, I= -0.2mA Lower Clamp Voltage VVAOUTL 1.1 V VSENSE=2.8V, I=0.5mA uA Tj=25°C Overvoltage Regulator Threshold Current IOVR 35 40 45 1) not tested, guaranteed by design Infineon Tech PCI Group 10.09.01 9 Infineon Technologies Parameter preliminary typ. ICE1PD265G Symbol min. max. Unit Input Bias Current IBISENSE -1 Input Offset Voltage VISENSEO VISENSEO Max Threshold Voltage VISENSEM Threshold at OVR VISENOVR 0.05 V Shut Down Delay tdISG 100 ns Leading Edge Blanking tLEB 220 ns Upper threshold voltage VDETINU 1.5 V Lower threshold voltage VDETINL 1 V Hysteresis VDETINHY 0.5 V Input current IBDETIN Input clamp voltage High state Low state VDETINHC VDETINLC Test Condition Current Comparator uA 150 20 0.95 1.0 mV mV 1.05 VMULTIN=0V, VAOUT=2.4V VMULTIN=0V, VAOUT>2.8V V IOVR=50uA Detector -1 uA 5 0.5 IDETIN=5mA IDETIN=-5mA Multiplier Input bias current IBMULTIN Dynamic voltage range MULTIN VMULTIN Dynamic voltage range VAOUT Multiplier Gain VVAOUT Klow Khigh -1 uA 0 to 4 V VFB to VFB+1. VVAOUT=2.75V VMULTIN=1V 5 0.18 0.56 V V VVAOUT<3V VVAOUT>3.5V Restart Timer restart time Infineon Tech tRES PCI Group 150 us 10.09.01 10 Infineon Technologies Parameter preliminary Symbol min. typ. Drain source breakdown voltage VBRDSS 600 650 Drain source on-resistance RDSon 1.1 Zero gate voltage drain current IDSS 0.5 Output capacitance 1) COSS Rise time Fall time trise tfall max. ICE1PD265G Unit Test Condition V V TJ=25°C TJ=115°C 1.4 3.8 Ohm Ohm Tj=25°C Tj=150°C 1 70 uA uA UGS=0V, Tj=25° UGS=0V, Tj=150° 150 pF VDS=25V, f=1MHz 30 50 ns ns CoolMOS 1) not tested, guaranteed by design Infineon Tech PCI Group 10.09.01 11 Infineon Technologies preliminary ICE1PD265G Electrical Diagrams Diagram 1: Icc versus Vcc Diagram 2: VCCON/OFF versus Temperature 14 5 4,5 13 4 Vcc / V 3 Icc / mA VCC ON 12 3,5 2,5 VCC OFF 2 VCC ON 11 10 VCC OFF 1,5 9 1 8 0,5 7 0 0 5 10 15 -40 20 0 Vcc/V 40 80 120 160 Tj / °C Diagram 3: Iccl versus Vcc Diagram 4: ICCL versus 50 45 45 40 40 35 35 30 30 ICCL / uA Iccl / uA Temperature, VCC=9V 50 25 20 25 20 15 15 10 10 5 5 0 0 2 4 6 8 10 12 Vcc / V Infineon Tech PCI Group 14 16 0 -40 0 40 80 120 160 Tj / °C 10.09.01 12 Infineon Technologies preliminary Diagram 6: Voltage Amplifier Open loop gain and Phase Diagram 5: VFB vers. Temperature (pin1 connected to pin2) ICE1PD265G GV/dB 120 2,55 Phi/deg 180 2,54 160 100 2,53 Gv 140 2,52 80 120 VFB / V 2,51 100 2,5 60 Phi 80 2,49 40 2,48 60 40 2,47 20 20 2,46 2,45 -40 0 40 80 120 160 0 0,01 0,1 1 Tj / °C 10 100 0 1000 10000 f/kHz Diagram 7: Overvoltage Regulator VISENSE vers. Threshold Voltage Diagram 8: IOVR versus Temperature 45 1,2 VVAOUT = 3.5V 44 VMULTIN = 3.0V 1 43 42 41 IOVR /uA VISENSE / V 0,8 0,6 40 39 0,4 38 37 0,2 36 0 35 35 37 39 41 Iovp / uA Infineon Tech PCI Group 43 45 -40 0 40 80 120 160 Tj/°C 10.09.01 13 Infineon Technologies preliminary ICE1PD265G Diagram 10: Leading edge blanking (min on-time) vs. Temp. Diagram 9: max Threshold Voltage VISENSEM vs. Temperature 300 1,05 1,04 250 1,03 200 1,01 LEB / ns VISENSEM/V 1,02 1 150 0,99 100 0,98 0,97 50 0,96 0 0,95 -40 0 40 80 120 -40 160 0 40 80 120 160 Tj / °C Tj/°C Diagram 11: Current Sense Threshold VISENSE versus VMULTIN Diagram 12: Current sense threshold VISENSE versus VVAOUT 1 1 4.5V 0,9 Vmultin=4.0 0,9 4.0V 0,8 3.0 0,8 3.5V 0,7 2.0 0,7 3.25V 0,5 0,4 3.0V 0,3 VISENSE / V VISENSE / V 1.5 0,6 0,6 1.0 0,5 0,4 0.5 0,3 0,2 0,2 VVAOUT=2.75V 0,1 0.25 0,1 0 0 0 1 2 3 VMULTIN / V Infineon Tech PCI Group 4 2,5 3 3,5 4 4,5 VVAOUT / V 10.09.01 14 Infineon Technologies preliminary ICE1PD265G Diagram 13: Restart time versus temperature Diagram 14: VBRDSS vs. Temperature 800 250 700 200 600 500 trst / us VBRDSS / V 150 100 400 300 200 50 100 0 0 -40 0 40 80 120 160 Tj / °C -40 0 40 80 120 160 Tj/°C Diagram 15: RDSon vs. Temperature 3 2,5 RDSon / Ohm 2 1,5 1 0,5 0 -40 0 40 80 120 160 Tj/°C Infineon Tech PCI Group 10.09.01 15 Infineon Technologies preliminary ICE1PD265G Application circuit: RDSON=1.1 Ohm Pout=80W, Vin= 180 - 270V AC Pout=34W, Vin= 90 - 270 V AC RF filter Vin and 90-270V rectifier AC Vout D5 1N4937 R12 270 R8 100k R9 33k C10 47uF 16 C9 100n D6 MUR115 15 14 13 2 3 4 C1 1u R11 Infineon Tech R7 5.1k PCI Group 10 9 C8 47uF 5 6 7 8 R4 C2 1u C4 10n R7 11 ICE1PD265 1 R6 12 R5 GND 10.09.01 16