NEC MC-4564EC726PFB-A10 64 m-word by 72-bit synchronous dynamic ram module registered type Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM: µPD45128441 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 67,108,864 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
MC-4564EC726EFB-A80
MC-4564EC726EFB-A10
★
★
MC-4564EC726PFB-A80
MC-4564EC726PFB-A10
Clock frequency
Access time from CLK
Module type
(MAX.)
(MAX.)
CL = 3
125 MHz
6 ns
PC100 Registered DIMM
CL = 2
100 MHz
6 ns
Rev. 1.2 Compliant
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
• Stacked monolithic technology
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999
MC-4564EC726
Ordering Information
Part number
Clock frequency
(MAX.)
MC-4564EC726EFB-A80
125 MHz
168-pin Dual In-line Memory Module 36 pieces of µPD45128441G5 (Rev. E)
MC-4564EC726EFB-A10
100 MHz
(Socket Type)
★
MC-4564EC726PFB-A80
125 MHz
Edge connector: Gold plated
★
MC-4564EC726PFB-A10
100 MHz
43.18 mm height
2
Package
Data Sheet M14460EJ2V0DS00
Mounted devices
(10.16 mm (400) TSOP (II))
36 pieces of µPD45128441G5 (Rev. P)
(10.16 mm (400) TSOP (II))
MC-4564EC726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85
86
87
88
89
90
91
92
93
94
★
★
★
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
VSS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
VSS
A1
A3
A5
A7
A9
BA0 (A13)
A11
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
VSS
CKE0
/CS3
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
VSS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1(A12)
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vcc
CLK0
VSS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SDA
SCL
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/xxx indicates active low signal.
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11]
BA0 (A13), BA1 (A12)
: SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0
: Clock Enable Input
WP
: Write Protect
/CS0 - /CS3
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VCC
: Power Supply
VSS
: Ground
REGE
: Register / Buffer Enable
NC
: No Connection
Data Sheet M14460EJ2V0DS00
3
MC-4564EC726
Block Diagram
(1/2)
/RCS1
/RCS0
RDQMB0
RDQMB4
DQ 3
I/O 0
DQ 2
I/O 1
DQ 1
I/O 2
DQ 0
I/O 3
DQ 7
I/O 0
DQ 6
I/O 1
DQ 5
I/O 2
DQ 4
I/O 3
DQM
/CS
I/O 0
I/O 1
D0
I/O 2
DQM
/CS
D18
I/O 3
DQM
/CS
I/O 0
I/O 1
D1
I/O 2
DQM
/CS
D19
I/O 3
RDQMB1
DQ32
I/O 0
DQ33
I/O 1
DQ34
I/O 2
DQ35
I/O 3
DQ36
I/O 0
DQ37
I/O 1
DQ38
I/O 2
DQ39
I/O 3
DQM
I/O 0
/CS
I/O 1
D9
I/O 2
DQM
/CS
D27
I/O 3
DQM
I/O 0
/CS
I/O 1
D10
I/O 2
DQM
/CS
D28
I/O 3
RDQMB5
DQ11
I/O 0
DQ10
I/O 1
DQ 9
I/O 2
DQ 8
I/O 3
DQ15
I/O 0
DQ14
I/O 1
DQ13
I/O 2
DQ12
I/O 3
CB 3
I/O 0
CB 2
I/O 1
CB 1
I/O 2
CB 0
I/O 3
DQM
/CS
I/O 0
I/O 1
D2
I/O 2
DQM
/CS
D20
I/O 3
DQM
/CS
I/O 0
I/O 1
D3
I/O 2
DQM
/CS
D21
I/O 3
DQM
/CS
I/O 0
I/O 1
D4
I/O 2
DQM
/CS
D22
I/O 3
DQ40
I/O 0
DQ41
I/O 1
DQ42
I/O 2
DQ43
I/O 3
DQ44
I/O 0
DQ45
I/O 1
DQ46
I/O 2
DQ47
I/O 3
CB 4
I/O 0
CB 5
I/O 1
CB 6
I/O 2
CB 7
I/O 3
DQM
I/O 0
/CS
I/O 1
D11
I/O 2
DQM
/CS
D29
I/O 3
DQM
I/O 0
/CS
I/O 1
D12
I/O 2
DQM
/CS
D30
I/O 3
DQM
I/O 0
/CS
I/O 1
D13
I/O 2
DQM
/CS
D31
I/O 3
/RCS3
/RCS2
RDQMB2
RDQMB6
DQ19
I/O 0
DQ18
I/O 1
DQ17
I/O 2
DQ16
I/O 3
DQ23
I/O 0
DQ22
I/O 1
DQ21
I/O 2
DQ20
I/O 3
DQM
/CS
I/O 0
I/O 1
D5
I/O 2
DQM
/CS
D23
I/O 3
DQM
/CS
I/O 0
I/O 1
D6
I/O 2
DQM
/CS
D24
I/O 3
RDQMB3
DQ48
I/O 0
DQ49
I/O 1
DQ50
I/O 2
DQ51
I/O 3
DQ52
I/O 0
DQ53
I/O 1
DQ54
I/O 2
DQ55
I/O 3
DQM
I/O 0
/CS
I/O 1
D14
I/O 2
DQM
/CS
D32
I/O 3
DQM
I/O 0
/CS
I/O 1
D15
I/O 2
DQM
/CS
D33
I/O 3
RDQMB7
DQ27
I/O 0
DQ26
I/O 1
DQ25
I/O 2
DQ24
I/O 3
DQ31
I/O 0
DQ30
I/O 1
DQ29
I/O 2
DQ28
I/O 3
DQM
DQM
D8
I/O 1
I/O 2
DQM
/CS
D25
/CS
I/O 0
I/O 1
I/O 2
DQM
/CS
D26
I/O 3
PLL
★
I/O 0
I/O 3
10 Ω
CLK0
/CS
D7
DQ56
I/O 0
DQ57
I/O 1
DQ58
I/O 2
DQ59
I/O 3
DQ60
I/O 0
DQ61
I/O 1
DQ62
I/O 2
DQ63
I/O 3
CLK: D0, D18, D9, D27
CLK: D1, D19, D10, D28
CLK: D2, D20, D11, D29
CLK: D3, D21, D12, D30
CLK: D4, D22, D13, D31
CLK: D5, D23, D14, D32
CLK: D6, D24, D15, D33
CLK: D7, D25, D16, D34
CLK: D8, D26, D17, D35
CLK: Register1- Register3
DQM
I/O 0
/CS
I/O 1
D16
I/O 2
DQM
/CS
D34
I/O 3
DQM
I/O 0
/CS
I/O 1
D17
I/O 2
DQM
/CS
D35
I/O 3
10 Ω
CLK1 - CLK3
12 pF
SERIAL PD
SDA
SCL
★
A0
VCC
A1
A2
D0 - D35, REGISTER1 - REGISTER3, PLL
C
VSS
4
D0 - D35, REGISTER1 - REGISTER3, PLL
Data Sheet M14460EJ2V0DS00
WP
47 kΩ
SA0 SA1 SA2
MC-4564EC726
Block Diagram
(2/2)
A1
A3
10 kΩ
A5
REGE
A7
A9
Register 1
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
/LE
A0
A2
A4
A6
A8
Register 2
A10
/WE
BA0
/CS0
DQMB0
DQMB1
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
/LE
A11
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
BA1
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
CKE0
Register 3
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
/LE
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 – D35: µPD45128441 (8M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
4. Register: HD74ALVC16835
PLL: HD74CDC2510B
Data Sheet M14460EJ2V0DS00
5
MC-4564EC726
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on power supply pin relative to GND
VCC
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
40
W
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.3
3.6
V
Supply voltage
VCC
3.0
High level input voltage
VIH
2.0
VCC + 0.3
V
Low level input voltage
VIL
–0.3
+0.8
V
Operating ambient temperature
TA
0
70
°C
MAX.
Unit
pF
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
★
Data input/output capacitance
6
Symbol
Test condition
MIN.
TYP.
CI1
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
TBD
TBD
CI2
CLK0
TBD
TBD
CI3
CKE0
TBD
TBD
CI4
/CS0 - /CS3
TBD
TBD
CI5
DQMB0 - DQMB7
TBD
TBD
CI/O
DQ0 - DQ63, CB0 - CB7
TBD
TBD
Data Sheet M14460EJ2V0DS00
pF
MC-4564EC726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
ICC1
Test condition
Burst length = 1
Grade
/CAS latency = 2
tRC ≥ tRC (MIN.), IO = 0 mA
/CAS latency = 3
Precharge standby current in
★
power down mode
Precharge standby current in
ICC2P
ICC2PS
ICC2N
non power down mode
MIN.
MAX.
Unit Notes
-A80
2,640
mA
-A10
2,640
-A80
2,640
-A10
2,640
CKE ≤ VIL (MAX.), tCK = 15 ns
286
CKE ≤ VIL (MAX.), tCK = ∞
116
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
970
1
mA
mA
Input signals are changed one time during 30 ns.
ICC2NS
CKE ≥ VIH (MIN.), tCK = ∞ ,
368
Input signals are stable.
Active standby current in
power down mode
Active standby current in
ICC3P
ICC3PS
ICC3N
non power down mode
CKE ≤ VIL (MAX.), tCK = 15 ns
430
CKE ≤ VIL (MAX.), tCK = ∞
224
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
1,330
mA
mA
Input signals are changed one time during 30 ns.
ICC3NS
CKE ≥ VIH (MIN.), tCK = ∞ ,
800
Input signals are stable.
Operating current
ICC4
tCK ≥ tCK (MIN.), IO = 0 mA
/CAS latency = 2
(Burst mode)
/CAS latency = 3
★
CBR (Auto) Refresh current
ICC5
tRC ≥ tRC (MIN.)
/CAS latency = 2
★
★
/CAS latency = 3
★
Self refresh current
ICC6
CKE ≤ 0.2 V
Input leakage current
II (L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
Input leakage current (CKE0)
Input leakage current
(/CS0-/CS3, DQMB0-DQMB7)
-A80
2,730
-A10
2,370
-A80
3,180
-A10
2,820
-A80
4,980
-A10
4,980
-A80
4,980
-A10
4,980
mA
2
mA
3
322
mA
–20
+20
µA
–40
+40
–10
+10
+3
Output leakage current
IO (L)
DOUT is disabled, VO = 0 to 3.6 V
–3
High level output voltage
VOH
IO = –4.0 mA
2.4
Low level output voltage
VOL
IO = +4.0 mA
µA
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet M14460EJ2V0DS00
7
MC-4564EC726
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
★
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
tCK
tCH
CLK
2.4 V
1.4 V
0.4 V
tSETUP tHOLD
Input
2.4 V
1.4 V
0.4 V
tAC
tOH
Output
8
Data Sheet M14460EJ2V0DS00
tCL
Value
Unit
2.4 / 0.4
V
1.4
V
1
ns
1.4
V
MC-4564EC726
Synchronous Characteristics
Parameter
Clock cycle time
Access time from CLK
Symbol
-A80
-A10
Unit
MIN.
MAX.
MIN.
MAX.
/CAS latency = 3
tCK3
8
(125 MHz)
10
(100 MHz)
ns
/CAS latency = 2
tCK2
10
(100 MHz)
13
(77 MHz)
ns
/CAS latency = 3
tAC3
6
6
ns
1
/CAS latency = 2
tAC2
6
7
ns
1
Input clock frequency
50
125
50
100
MHz
Input CLK duty cycle
40
60
40
60
%
Data-out hold time
Note
/CAS latency = 3
tOH3
3
3
ns
1
/CAS latency = 2
tOH2
3
3
ns
1
tLZ
0
0
ns
/CAS latency = 3
tHZ3
3
6
3
6
ns
/CAS latency = 2
tHZ2
3
6
3
7
ns
Data-in setup time
tDS
2
2
ns
Data-in hold time
tDH
1
1
ns
Address setup time
tAS
2
2
ns
Address hold time
tAH
1
1
ns
CKE setup time
tCKS
2
2
ns
CKE hold time
tCKH
1
1
ns
CKE setup time (Power down exit)
tCKSP
2
2
ns
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
tCMS
2
2
ns
tCMH
1
1
ns
Data-out low-impedance time
Data-out high- impedance time
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet M14460EJ2V0DS00
9
MC-4564EC726
Asynchronous Characteristics
Parameter
Symbol
-A80
MIN.
-A10
MAX.
MIN.
Unit
MAX.
ACT to REF/ACT command period (Operation)
tRC
70
70
ns
REF to REF/ACT command period (Refresh)
tRC1
70
78
ns
ACT to PRE command period
tRAS
48
PRE to ACT command period
tRP
20
20
ns
Delay time ACT to READ/WRITE command
tRCD
20
20
ns
ACT(one) to ACT(another) command period
tRRD
16
20
ns
Data-in to PRE command period
tDPL
−1CLK+8
−1CLK+10
ns
120,000
50
120,000
ns
Data-in to ACT(REF) command
/CAS latency = 3
tDAL3
20
20
ns
period (Auto precharge)
/CAS latency = 2
tDAL2
20
20
ns
tRSC
2
2
CLK
tT
0.5
Mode register set cycle time
Transition time
Refresh time (4,096 refresh cycles)
10
tREF
Data Sheet M14460EJ2V0DS00
30
64
1
30
ns
64
ms
Note
MC-4564EC726
Serial PD
Byte No.
(1/2)
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
0
Defines the number of bytes written into
serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
04H
0
0
0
0
0
1
0
0
SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
0BH
0
0
0
0
1
0
1
1
11 columns
5
Number of banks
02H
0
0
0
0
0
0
1
0
2 bank
6
Data width
48H
0
1
0
0
1
0
0
0
72 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
01H
0
0
0
0
0
0
0
1
LVTTL
9
CL = 3 Cycle time
-A80
80H
1
0
0
0
0
0
0
0
8 ns
-A10
A0H
1
0
1
0
0
0
0
0
10 ns
10
CL = 3 Access time
-A80
60H
0
1
1
0
0
0
0
0
6 ns
-A10
60H
0
1
1
0
0
0
0
0
6 ns
11
DIMM configuration type
02H
0
0
0
0
0
0
1
0
ECC
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
04H
0
0
0
0
0
1
0
0
x4
14
Error checking SDRAM width
04H
0
0
0
0
0
1
0
0
x4
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
8FH
1
0
0
0
1
1
1
1
1, 2, 4, 8, F
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
06H
0
0
0
0
0
1
1
0
2, 3
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
01H
0
0
0
0
0
0
0
1
0
21
SDRAM module attributes
1FH
0
0
0
1
1
1
1
1
Registered
22
SDRAM device attributes : General
0EH
0
0
0
0
1
1
1
0
23
CL = 2 Cycle time
-A80
A0H
1
0
1
0
0
0
0
0
-A10
D0H
1
1
0
1
0
0
0
0
13 ns
24
CL = 2 Access time
-A80
60H
0
1
1
0
0
0
0
0
6 ns
-A10
70H
0
1
1
1
0
0
0
0
7 ns
25-26
27
28
29
30
31
tRP(MIN.)
tRRD(MIN.)
tRCD(MIN.)
tRAS(MIN.)
Module bank density
10 ns
00H
0
0
0
0
0
0
0
0
-A80
14H
0
0
0
1
0
1
0
0
20 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
10H
0
0
0
1
0
0
0
0
16 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
14H
0
0
0
1
0
1
0
0
20 ns
-A10
14H
0
0
0
1
0
1
0
0
20 ns
-A80
30H
0
0
1
1
0
0
0
0
48 ns
-A10
32H
0
0
1
1
0
0
1
0
50 ns
40H
0
1
0
0
0
0
0
0
256M bytes
Data Sheet M14460EJ2V0DS00
11
MC-4564EC726
(2/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
Command and address signal input
setup time
20H
0
0
1
0
0
0
0
0
2 ns
33
Command and address signal input hold
time
10H
0
0
0
1
0
0
0
0
1 ns
34
Data signal input setup time
20H
0
0
1
0
0
0
0
0
2 ns
35
Data signal input hold time
10H
0
0
0
1
0
0
0
0
1 ns
00H
0
0
0
0
0
0
0
0
36-61
62
SPD revision
63
Checksum for bytes 0 - 62
64-71
72
73-90
91
12H
0
0
0
1
0
0
1
0
-A80
3BH
0
0
1
1
1
0
1
1
-A10
A1H
1
0
1
0
0
0
0
1
1.2 A
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
Revision Code
93-94
Manufacturing date
95-98
Assembly serial number
99-125
Mfg specific
126
Intel specification frequency
64H
0
1
1
0
0
1
0
0
127
Intel specification /CAS
-A80
87H
1
0
0
0
0
1
1
1
latency support
-A10
85H
1
0
0
0
0
1
0
1
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
12
Notes
Data Sheet M14460EJ2V0DS00
100 MHz
MC-4564EC726
★
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
M1 (AREA B)
Z
R
N
M
Q
L
A
M2 (AREA A)
B
S
T
(OPTIONAL HOLES)
K
C
J
I
B
H
U
E
D
G
A1 (AREA A)
ITEM
detail of A part
detail of B part
D2
W
133.35
A1
133.35±0.13
B
11.43
C
D
36.83
6.35
D1
2.0
D2
3.125
54.61
E
G
H
I
J
V
X
6.35
1.27 (T.P.)
8.89
K
24.495
42.18
L
17.78
P
M
M1
43.18±0.13
23.40
M2
19.78
D1
N
6.35 MAX.
1.0
P
Q
R
S
T
U
V
W
X
Y
Z
Data Sheet M14460EJ2V0DS00
MILLIMETERS
A
R2.0
4.0±0.10
φ 3.0
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
3.0 MIN.
M168S-50A112
13
MC-4564EC726
[MEMO]
14
Data Sheet M14460EJ2V0DS00
MC-4564EC726
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14460EJ2V0DS00
15
MC-4564EC726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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