NSC ADC0848BCV 8-bit up compatible a/d converters with multiplexer option Datasheet

ADC0844/ADC0848
8-Bit µP Compatible A/D Converters with Multiplexer
Options
General Description
Features
The ADC0844 and ADC0848 are CMOS 8-bit successive approximation A/D converters with versatile analog input multiplexers. The 4-channel or 8-channel multiplexers can be
software configured for single-ended, differential or
pseudo-differential modes of operation.
The differential mode provides low frequency input common
mode rejection and allows offsetting the analog range of the
converter. In addition, the A/D’s reference can be adjusted
enabling the conversion of reduced analog ranges with 8-bit
resolution.
The A/Ds are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE ® output latches
that directly drive the data bus permit the A/Ds to be configured as memory locations or I/O devices to the microprocessor with no interface logic necessary.
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 VDC
voltage reference
n No zero or full-scale adjust required
n 4-channel or 8-channel multiplexer with address logic
n Internal clock
n 0V to 5V input range with single 5V power supply
n 0.3" standard width 20-pin or 24-pin DIP
n 28 Pin Molded Chip Carrier Package
Key Specifications
n
n
n
n
n
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
± 1⁄2 LSB and ± 1 LSB
5 VDC
15 mW
40 µs
Block and Connection Diagrams
DS005016-1
*ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844
TRI-STATE ® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation
DS005016
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ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options
June 1999
Block and Connection Diagrams
Molded Chip Carrier Package
(Continued)
Dual-In-Line Package
Dual-In-Line Package
DS005016-2
Top View
DS005016-29
DS005016-30
Top View
See Ordering Information
Top View
Ordering Information
Temperature
Range
Total Unadjusted Error
± 1⁄2 LSB
MUX
Package
± 1 LSB
Channels
Outline
ADC0844CCN
4
0˚C to +70˚C
ADC0848BCN
8
ADC0848CCN
ADC0844BCJ
−40˚C to +85˚C
4
ADC0848BCV
J20A
Cerdip
8
2
N24C
Molded Dip
ADC0844CCJ
ADC0848CCV
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N20A
Molded Dip
V28A
Molded Chip Carrier
Absolute Maximum Ratings (Notes 1, 2)
Lead Temperature
(Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage
Logic Control Inputs
At Other Inputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Storage Temperature
Package Dissipation at TA = 25˚C
ESD Susceptibility (Note 4)
6.5V
−0.3V to +15V
−0.3V to VCC+0.3V
5 mA
20 mA
−65˚C to +150˚C
875 mW
800V
260˚C
300˚C
215˚C
220˚C
Operating Conditions
(Notes 1, 2)
Supply Voltage (VCC)
Temperature Range
ADC0844CCN, ADC0848BCN,
ADC0848CCN
ADC0844BCJ, ADC0844CCJ,
ADC0848BCV, ADC0848CCV
4.5 VDC to 6.0 VDC
TMIN≤TA≤TMAX
0˚C≤TA≤70˚C
−40˚C≤TA≤85˚C
Electrical Characteristics
The following specifications apply for VCC = 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25˚C.
ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
ADC0844BCJ
ADC0844CCJ
Parameter
Conditions
Typ
Tested
(Note 5)
Design
Typ
Limit
Limit
(Note 5)
(Note 6)
(Note 7)
Tested
Design
Limit
Units
Limit
Limit
(Note 6)
(Note 7)
ADC0844BCN, ADC0848BCN, BCV
± 1⁄2
± 1⁄2
LSB
ADC0844CCN, ADC0848CCN, CCV
±1
±1
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
VREF = 5.00 VDC
Unadjusted Error
(Note 8)
±1
ADC0844CCJ
Minimum Reference
LSB
2.4
1.1
2.4
1.2
1.1
kΩ
2.4
5.9
2.4
5.4
5.9
kΩ
Input Resistance
Maximum Reference
Input Resistance
Maximum Common-Mode
(Note 9)
VCC+0.05
VCC+0.05
VCC+0.05
V
(Note 9)
GND−0.05
GND−0.05
GND−0.05
V
Input Voltage
Minimum Common-Mode
Input Voltage
DC Common-Mode Error
Differential Mode
± 1/16
± 1⁄4
± 1/16
± 1⁄4
± 1⁄4
LSB
Power Supply Sensitivity
VCC = 5V ± 5%
± 1/16
± 1⁄8
± 1/16
± 1⁄8
± 1⁄8
LSB
Off Channel Leakage
(Note 10)
−1
−0.1
−1
µA
1
0.1
1
µA
VCC = 5.25V
2.0
2.0
2.0
V
VCC = 4.75V
0.8
0.8
0.8
V
Current
On Channel = 5V,
Off Channel = 0V
On Channel = 0V,
Off Channel = 5V
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input
Voltage (Min)
VIN(0), Logical “0” Input
Voltage (Max)
IIN(1), Logical “1” Input
VIN = 5.0V
0.005
1
0.005
1
µA
VIN = 0V
−0.005
−1
−0.005
−1
µA
Current (Max)
IIN(0), Logical “0” Input
Current (Max)
VOUT(1), Logical “1”
VCC = 4.75V
Output Voltage (Min)
IOUT = −360 µA
2.4
2.8
2.4
V
IOUT = −10 µA
4.5
4.6
4.5
V
3
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Electrical Characteristics
(Continued)
The following specifications apply for VCC = 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25˚C.
ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
ADC0844BCJ
ADC0844CCJ
Parameter
Conditions
Typ
Tested
(Note 5)
Design
Typ
Limit
Limit
(Note 5)
(Note 6)
(Note 7)
Tested
Design
Limit
Limit
(Note 6)
(Note 7)
0.34
0.4
Limit
Units
DIGITAL AND DC CHARACTERISTICS
VOUT(0), Logical “0”
VCC = 4.75V
Output Voltage (Max)
IOUT = 1.6 mA
IOUT, TRI-STATE Output
VOUT = 0V
−0.01
−3
−0.01
−0.3
−3
µA
Current (Max)
VOUT = 5V
0.01
3
0.01
0.3
3
µA
ISOURCE, Output Source
VOUT = 0V
−14
−6.5
−14
−7.5
−6.5
mA
VOUT = VCC
16
8.0
16
9.0
8.0
mA
CS = 1, VREF
Open
1
2.5
1
2.3
2.5
mA
0.4
V
Current (Min)
ISINK, Output Sink
Current (Min)
ICC, Supply Current (Max)
AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN
to TMAX; all other limits TA = Tj = 25˚C.
Tested
Parameter
Conditions
tC, Maximum Conversion Time (See Graph)
tW(WR), Minimum WR Pulse Width
Design
Typ
Limit
Limit
(Note 5)
(Note 6)
(Note 7)
30
40
60
50
150
Units
µs
(Note 11)
CL = 100 pF
145
225
ns
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising
(Note 11)
CL = 10 pF, RL = 10k
125
200
ns
Edge of RD to Hi-Z State)
(Note 11)
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to
(Note 11)
200
400
ns
tDS, Minimum Data Set-Up Time
(Note 11)
50
100
ns
tDH, Minimum Data Hold Time
(Note 11)
0
50
tACC, Maximum Access Time (Delay from Falling Edge of
RD to Output Data Valid)
ns
Reset of INTR
ns
CIN, Capacitance of Logic Inputs
5
pF
COUT, Capacitance of Logic Outputs
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of the current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typicals are at 25˚C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
Note 9: For VIN (−) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input
voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V)
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an
absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 10: Off channel leakage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.3%/˚C.
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Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
Output Current vs
Temperature
Power Supply Current vs
Temperature
DS005016-32
DS005016-31
Linearity Error vs VREF
DS005016-33
Conversion Time vs VSUPPLY
DS005016-34
Conversion Time vs
Temperature
DS005016-35
Unadjusted Offset Error vs
VREF Voltage
DS005016-36
DS005016-37
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TRI-STATE Test Circuits and Waveforms
t1H, CL = 10 pF
t1H
DS005016-5
DS005016-4
tr = 20 ns
t0H, CL = 10 pF
t0H
DS005016-7
DS005016-6
tr = 20 ns
Leakage Current Test Circuit
DS005016-8
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Timing Diagrams
Programming New Channel Configuration and Starting a Conversion
DS005016-9
Note 12: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR .
Note 13: MA stands for MUX address.
Using the Previously Selected Channel Configuration and Starting a Conversion
DS005016-10
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DS005016-11
ADC0848 Functional Block Diagram
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8
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the
most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros output code.
Functional Description
The ADC0844 and ADC0848 contain a 4-channel and
8-channel analog input multiplexer (MUX) respectively. Each
MUX can be configured into one of three modes of operation
differential, pseudo-differential, and single ended. These
modes are discussed in the Applications Information Section. The specific mode is selected by loading the MUX address latch with the proper address (see Table 1 and Table
2). Inputs to the MUX address latch (MA0-MA4) are common
with data bus lines (DB0-DB4) and are enabled when the RD
line is high. A conversion is initiated via the CS and WR lines.
If the data from a previous conversion is not read, the INTR
line will be low. The falling edge of WR will reset the INTR
line high and ready the A/D for a conversion cycle. The rising
edge of WR, with RD high, strobes the data on the MA0/
DB0-MA4/DB4 inputs into the MUX address latch to select a
new input configuration and start a conversion. If the RD line
is held low during the entire low period of WR the previous
MUX configuration is retained, and the data of the previous
conversion is the output on lines DB0-DB7. After the conversion cycle (tC ≤ 40 µs), which is set by the internal clock frequency, the digital data is transferred to the output latch and
the INTR is asserted low. Taking CS and RD low resets INTR
output high and outputs the conversion result on the data
lines (DB0-DB7).
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, single
ended, or pseudo-differential. Figure 1 shows the three
modes using the 4-channel MUX ADC0844. The eight inputs
of the ADC0848 can also be configured in any of the three
modes. In the differential mode, the ADC0844 channel inputs
are grouped in pairs, CH1 with CH2 and CH3 with CH4. The
polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1–CH4 assigned as the positive input with the negative input being the
analog ground (AGND) of the device. Finally, in the
pseudo-differential mode CH1–CH3 are positive inputs referenced to CH4 which is now a pseudo-ground. This
pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above VCC (typically 5V) without degrading conversion accuracy.
Applications Information
1.0 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data comparator structure which allows a differential analog input to
be converted by a successive approximation routine.
TABLE 1. ADC0844 MUX ADDRESSING
MUX Address
MA3
CS
WR
Channel#
RD
MA2
MA1
MA0
X
L
L
L
L
X
L
L
H
L
X
L
H
L
L
H
X
L
H
H
L
H
L
H
L
L
L
H
L
H
L
H
L
L
H
H
L
L
L
L
CH1
CH2
H
+
−
H
−
+
H
H
H
L
H
H
L
L
L
H
H
H
L
H
L
H
H
H
L
L
X
X
X
X
L
L
−
−
+
+
+
Single-Ended
−
+
L
Mode
−
−
+
H
AGND
Differential
+
H
L
+
+
H
L
CH4
+
H
H
MUX
CH3
−
−
Pseudo-
−
Differential
−
Previous Channel Configuration
X = don’t care
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Applications Information
(Continued)
4 Single-Ended
2 Differential
DS005016-12
DS005016-13
3 Pseudo-Differential
Combined
DS005016-14
DS005016-15
FIGURE 1. Analog Input Multiplexer Options
most typical). The time interval between sampling the “+” input and then the “−” inputs is 1⁄2 of a clock period. The
change in the common-mode voltage during this short time
interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
2.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN)) over which the 256
possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute
accuracy. The reference pin must be connected to a voltage
source capable of driving the minimum reference input resistance of 1.1 kΩ. This pin is the top of a resistor divider string
used for the successive approximation conversion.
In a ratiometric system (Figure 2a), the analog input voltage
is proportional to the voltage used for the A/D reference. This
voltage is typically the system power supply, so the VREF pin
can be tied to VCC. This technique relaxes the stability requirements of the system reference as the analog input and
A/D reference move together maintaining the same output
code for a given input condition.
For absolute accuracy (Figure 2b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with these converters.
The maximum value of the reference is limited to the VCC
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals VREF/256).
DS005016-38
where fCM is the frequency of the common-mode signal,
Vpeak is its peak voltage value and tC is the conversion time.
For a 60 Hz common-mode signal to generate a 1⁄4 LSB error
(≈5 mV) with the converter running at 40 µS, its peak value
would have to be 5.43V. This large a common-mode signal is
much greater than that generally found in a well designed
data acquisition system.
3.0 THE ANALOG INPUTS
3.1 Analog Differential Voltage Inputs and
Common-Mode Rejection
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
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Applications Information
(Continued)
TABLE 2. ADC0848 MUX Addressing
MUX Address
CS
WR
RD
MA4 MA3 MA2 MA1 MA0
Channel
CH1
CH2
CH3
CH4
MUX
CH5
CH6
H
+
−
−
+
CH7
CH8 AGND
X
L
L
L
L
L
H
+
−
X
L
L
L
H
L
H
−
+
X
L
L
H
L
L
H
+
−
X
L
L
H
H
L
H
−
+
X
L
H
L
L
L
X
L
H
L
H
L
H
X
L
H
H
L
L
H
+
−
X
L
H
H
H
L
H
−
+
L
H
L
L
L
L
H
L
H
L
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
H
L
L
H
H
L
L
L
L
H
H
L
H
L
H
L
H
H
H
L
L
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
L
H
L
H
H
H
L
H
L
L
H
H
H
L
H
H
L
H
H
H
L
L
L
H
H
H
H
L
H
L
H
H
H
H
H
L
L
H
X
X
X
X
X
L
L
L
L
Differential
+
−
+
−
+
H
−
+
H
L
Mode
−
+
Single-Ended
−
+
−
+
−
+
+
−
−
+
−
+
H
+
+
Pseudo-
−
Differential
−
+
−
+
L
−
−
Previous Channel Configuration
put 0000 0000 digital code for this minimum input voltage by
biasing any VIN (−) input at this VIN(MIN) value. This is useful
for either differential or pseudo-differential modes of input
channel configuration.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V− input and applying a small magnitude positive voltage to the V+ input. Zero error is the difference between actual DC input voltage which is necessary to just
cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 9.8 mV for
VREF = 5.000 VDC).
3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the “−” input
at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal
comparator is strobed at the end of a clock period. Bypass
capacitors at the inputs will average these currents and
cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors
should not be used if the source resistance is greater than
1 kΩ.
3.3 Input Source Resistance
The limitation of the input source resistance due to the DC
leakage currents of the input multiplexer is important. A
worst-case leakage current of ± 1 µA over temperature will
create a 1 mV input error with a 1 kΩ source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 1⁄2 LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing
from 1111 1110 to 1111 1111.
4.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus 1⁄2 LSB (where the
4.0 OPTIONAL ADJUSTMENTS
4.1 Zero Error
The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a
zero offset can be done. The converter can be made to out-
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Applications Information
reference voltage at the corresponding “−” input should then
be adjusted to just obtain the 00HEX to 01HEX code transition.
(Continued)
LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected “+” input and the zero
DS005016-16
a) Ratiometric
DS005016-17
b) Absolute with a Reduced Span
FIGURE 2. Referencing Examples
The VREF (or VCC) voltage is then adjusted to provide a code
change from FEHEX to FFHEX. This completes the adjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.
The full-scale adjustment should be made [with the proper
VIN (−) voltage applied] by forcing a voltage to the VIN (+) input which is given by:
where VMAX = the high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range. (Both
are ground referenced.)
Zero-Shift and Span Adjust (2V≤VIN≤5V)
DS005016-18
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Applications Information
(Continued)
Differential Voltage Input 9-Bit A/D
DS005016-19
Span Adjust (0V≤VIN≤3V)
DS005016-20
Protecting the Input
DS005016-21
Diodes are 1N914
13
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Applications Information
(Continued)
High Accuracy Comparators
DS005016-22
DO = all 1s if VIN(+) > VIN(−)
DO = all 0s if VIN(+) < VIN(−)
Operating with Automotive Ratiometric Transducers
DS005016-23
*VIN(−) = 0.15 VCC
15% of VCC≤VXDR≤85% of VCC
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Applications Information
(Continued)
A Stand Alone Circuit
DS005016-25
Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.
Start a Conversion without Updating the Channel Configuration
DS005016-26
CS • WR will update the channel configuration and start a conversion.
CS • RD will read the conversion data and start a new conversion without updating the channel configuration.
Waiting for the end of this conversion is not necessary. A CS • WR can immediately follow the CS • RD .
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Applications Information
(Continued)
ADC0844 — INS8039 Interface
DS005016-27
SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
0000
04 10
BEGIN:
ORG
0H
JMP
BEGIN
ORG
10H
;MAIN PROGRAM
MOV
R1,#0FFH
;LOAD R1 WITH A UNUSED ADDR
;START PROGRAM AT ADDR 10
0010
B9 FF
0012
B8 20
MOV
R0,#20H
0014
89 FF
ORL
P1,#0FFH
;SET PORT 1 OUTPUTS HIGH
0016
23 00
MOV
A,00H
;LOAD THE ACC WITH A/D MUX DATA
0018
14 50
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
001A
23 02
MOV
A,#02H
;LOCATION
;A/D DATA ADDRESS
;CH1 AND CH2 DIFFERENTIAL
;LOAD THE ACC WITH A/D MUX DATA
;CH3 AND CH4 DIFFERENTIAL
001C
18
INC
R0
;INCREMENT THE A/D DATA ADDRESS
001D
14 50
CALL
CONV
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC — A/D MUX DATA
;EXIT: ACC — CONVERTED DATA
0050
99 FE
0052
91
0053
09
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CONV:
LOOP:
ORG
50H
ANL
P1,#0FEH
MOVX
@ R1,A
;LOAD A/D MUX & START CONVERSION
IN
A,P1
;INPUT INTR STATE
16
;CHIP SELECT THE A/D
Applications Information
(Continued)
SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS (Continued)
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT A/D DATA
0054
32 53
JB1
LOOP
0056
81
MOVX
A,@R1
0057
89 01
ORL
P1,&01H
;CLEAR THE A/D CHIP SELECT
0059
A0
MOV
@ R0,A
;STORE THE A/D DATA
005A
83
RET
;RETURN TO MAIN PROGRAM
I/O Interface to NSC800
DS005016-28
SAMPLE PROGRAM FOR ADC0848 — NSC800 INTERFACE
0008
NCONV
EQU
16
000F
DEL
EQU
15
;DELAY 50 µsec CONVERSION
001F
CS
EQU
1FH
;THE BOARD ADDRESS
3C00
ADDTA
EQU
003CH
;START OF RAM FOR A/D
MUXDTA:
DB
08H,09H,0AH,0BH
;MUX DATA
DB
0CH,0DH,0EH,0FH
START:
LD
C,CS
;DATA
0000'
08 09 0A 0B
0004'
0C 0D 0E 0F
0008'
0E 1F
000A'
06 16
LD
B,NCONV
000C'
21 0000'
LD
HL,MUXDTA
000F'
11 003C
LD
DE,ADDTA
0012'
ED A3
0014'
EB
EX
DE,HL
0015'
3E 0F
LD
A,DEL
0017'
3D
DEC
A
;WAIT 50 µsec FOR THE
0018'
C2 0013'
JP
NZ,WAIT
;CONVERSION TO FINISH
001B'
ED A2
INI
001D'
EB
EX
DE,HL
001E'
C2 000E'
JP
NZ,STCONV
STCONV:
OUTI
;LOAD A/D’S MUX DATA
;AND START A CONVERSION
;HL = RAM ADDRESS FOR THE
;A/D DATA
WAIT:
;STORE THE A/D’S DATA
;CONVERTED ALL INPUTS?
;IF NOT GOTO STCONV
END
Note 14: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 µs wait for the A/D to
complete a conversion and the data is stored at address ADDTA for CH1, ADDTA + 1 for CH2, etc.
17
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Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
Molded Dual-In-Line Package (N)
NS Package Number N20A
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18
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N24C
19
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ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Chip Carrier Package (V)
NS Package Number V28A
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