Samsung K6F1008V2C-YF70 128kx8 bit super low power and low voltage cmos static ram Datasheet

K6F1008V2C Family
CMOS SRAM
Document Title
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
Revision History
History
Draft Data
Remark
0.0
Initial Draft
November 27, 2001
Preliminary
0.1
Revise
- Changed Package Type
: 48(36)-TBGA-6.00x7.00 to 32-TSOP1-0813.4F
December 13, 2001
Preliminary
1.0
Finalize
June 12, 2002
Final
Revision No.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
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The K6F1008V2C families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and have various package types
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with low
data retention current.
Process Technology: Full CMOS
Organization: 128K x8 bit
Power Supply Voltage: 3.0~3.6V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
PKG Type
K6F1008V2C-F
Industrial(-40~85°C)
3.0~3.6V
551)/70ns
0.5µA2)
3mA
32-TSOP1-0813.4F
1. The parameter is measured with 30pF test load.
2. Typical values are measured at VCC=3.3V, TA=25°C and not 100% tested.
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTIONAL BLOCK DIAGRAM
32-sTSOP
Type1-Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Clk gen.
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Row
select
I/O1
I/O8
Data
cont
Precharge circuit.
Memory array
1024 rows
128×8 columns
I/O Circuit
Column select
Data
cont
Name
Function
CS1, CS2 Chip Select Inputs
Name
Function
I/O1~I/O8 Data Inputs/Outputs
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
Vss
Ground
Address Inputs
NC
No Connection
CS 1
CS 2
WE
Control
logic
OE
A0~A16
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F1008V2C-YF55
K6F1008V2C-YF70
32-sTSOP1-F, 55ns, 3.3V
32-sTSOP1-F, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
1)
1)
H
X
X
X
High-Z
Deselected
Standby
X1)
L
X1)
X1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
L
Din
Write
Active
1)
1)
X
1. X means don′t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
VIN,VOUT
-0.2 to VCC+0.3V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted within recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.
3
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
3.0
3.3
3.6
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.2
-
Vcc+0.3
V
Input low voltage
VIL
-
0.6
V
-0.3
3)
V
2)
Note :
1. TA=-40 to 85°C, otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Symbol
Test Condition
Min
Max
Unit
Input capacitance
Item
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min Typ 1 Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100%duty, I IO=0mA, CS1 ≤0.2V, CS2 ≥Vcc-0.2V, V IN≤0.2V
or VIN≥VCC-0.2V
-
-
3
mA
Average operating current
ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1 =VIL, CS2=VIH, VIN=VIH or VIL
-
-
35
mA
Output low voltage
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
Standby Current(CMOS)
ISB1
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc
-
0.5
5
2)
V
µA
1. Typical values are measured at VCC=3.3V, TA=25°C and not 100% tested.
2. Super low power product=1µA with special handling.
4
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
AC OPERATING CONDITIONS
VTM3)
TEST CONDITIONS(Test Load and Test Input/Output Reference)
R12)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL = 30pF+1TTL
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070Ω, R2 =3150Ω
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=3.0~3.6V, Industrial product:TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Write
Units
70ns
Min
Max
Min
Max
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
Read Cycle Time
Read
55ns
1)
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
VDR
CS1≥Vcc-0.2V
Data retention current
IDR
Vcc=1.5V, CS1≥Vcc-0.2V1)
Data retention set-up time
tSDR
Recovery time
tRDR
Vcc for data retention
1)
See data retention waveform
Min
Typ
Max
Unit
1.5
-
3.6
V
µA
-
-
1.0
0
-
-
tRC
-
-
ns
1. CS1 ≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)
5
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS 1
tAW
CS 2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 going low,
CS2 going high and WE going low : A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or from CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 is applied in case a write ends with CS1 or WE going high and
tWR2 is applied in case a write ends with CS2 going low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
3.0V
2.2V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0V
CS 2
tSDR
tRDR
VDR
CS2≤0.2V
0.4V
GND
8
Revision 1.0
June 2002
K6F1008V2C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters(inches)
0.20
0.008
+0.10
-0.05
+0.004
-0.002
0.10
MAX
0.004
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40 ±0.20
0.528 ±0.008
#1
#32
0.50
0.0197
#16
0.25
)
0.010
8.00
0.315
8.40
0.331 MAX
(
#17
1.00 ±0.10
0.039 ±0.004
0.25
0.010 TYP
11.80 ±0.10
0.465 ±0.004
+0.10
-0.05
0.006 +0.004
-0.002
0.15
0.05
0.002 MIN
1.20
0.047 MAX
0~8 °
0.45~0.75
0.018~0.030
(
9
0.50
)
0.020
Revision 1.0
June 2002
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