NTB45N06L, NTBV45N06L Power MOSFET 45 Amps, 60 Volts Logic Level, N−Channel D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features • • • • • • • • • • Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge AEC−Q101 Qualified and PPAP Capable − NTBV45N06L These Devices are Pb−Free and are RoHS Compliant http://onsemi.com 45 AMPERES, 60 VOLTS RDS(on) = 28 mW N−Channel D G S 4 Typical Applications • • • • Power Supplies Converters Power Motor Controls Bridge Circuits 1 2 3 D2PAK CASE 418B STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT1 4 Drain NTx 45N06LG AYWW 1 Gate NTx45N06L x A Y WW G 2 Drain 3 Source = Device Code = B or P = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 1 1 Publication Order Number: NTB45N06L/D NTB45N06L, NTBV45N06L MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc VGS VGS "15 "20 ID ID 45 30 150 Adc PD 125 0.83 3.2 2.4 W W/°C W W TJ, Tstg −55 to +175 °C EAS 240 mJ RqJC RqJA RqJA 1.2 46.8 63.2 TL 260 Rating Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) Vdc Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) IDM Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds Apk °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). ORDERING INFORMATION Package Shipping† D2PAK 50 Units / Rail NTB45N06LT4G D2PAK (Pb−Free) 800 / Tape & Reel NTBV45N06LT4G D2PAK (Pb−Free) 800 / Tape & Reel Device NTB45N06LG (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTB45N06L, NTBV45N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Min Typ Max Unit 60 − 67 67.2 − − − − − − 1.0 10 − − ±100 1.0 − 1.8 4.7 2.0 − − 23 28 − − 1.03 0.93 1.51 − gFS − 22.8 − mhos Ciss − 1212 1700 pF Coss − 352 480 Crss − 90 180 td(on) − 13 30 tr − 341 680 td(off) − 36 75 tf − 158 320 QT − 23 32 Q1 − 4.6 − Q2 − 14.1 − VSD − − 1.01 0.92 1.15 − Vdc trr − 56 − ns ta − 30 − tb − 26 − QRR − 0.09 − OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Note 4) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 4) (VGS = 5.0 Vdc, ID = 22.5 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 4) (VGS = 5.0 Vdc, ID = 45 Adc) (VGS = 5.0 Vdc, ID = 22.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 4) (VDS = 8.0 Vdc, ID = 12 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 45 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 4) Fall Time Gate Charge (VDS = 48 Vdc, ID = 45 Adc, VGS = 5.0 Vdc) (Note 4) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 45 Adc, VGS = 0 Vdc) (Note 4) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 45 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 4) Reverse Recovery Stored Charge 3. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 in2). mC NTB45N06L, NTBV45N06L 80 60 VGS = 6 V 50 VGS = 7 V VGS = 4.5 V 40 VGS = 4 V 30 VGS = 8 V 20 VGS = 3.5 V VGS = 9 V 10 0 0.046 1 3 2 4 TJ = 25°C 0.03 0.026 0.022 TJ = −55°C 0.018 10 20 30 40 50 60 80 70 TJ = 25°C 20 TJ = 100°C 10 TJ = −55°C 2.6 3.4 4.2 5 5.8 0.046 0.042 0.038 0.034 VGS = 5 V 0.03 0.026 VGS = 10 V 0.022 0.018 0 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 ID = 22.5 A VGS = 5 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.8 30 Figure 2. Transfer Characteristics 0.034 2 40 Figure 1. On−Region Characteristics TJ = 100°C 0 50 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.038 0.014 60 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = 5 V 0.042 VDS > = 10 V 70 0 1.8 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS = 5 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 70 80 VGS = 5.5 V VGS = 10 V 1.6 1.4 1.2 1 TJ = 150°C 1000 TJ = 125°C 100 TJ = 100°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 10 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 60 4000 Ciss TJ = 25°C 3200 Crss 2800 2400 2000 Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 25 20 3 2 1 ID = 45 A TJ = 25°C 0 0 4 8 12 16 20 tr td(off) 1 10 100 40 32 24 16 8 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 10 10 ms 1 ms RDS(on) Limit Thermal Limit Package Limit 1 100 ms 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) dc 0.1 0.10 VGS = 0 V TJ = 25°C RG, GATE RESISTANCE (W) VGS = 15 V SINGLE PULSE TC = 25°C 1 24 48 VDS = 30 V ID = 45 A VGS = 5 V td(on) ID, DRAIN CURRENT (AMPS) 4 VGS Q2 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 100 100 Q1 Figure 7. Capacitance Variation tf 1000 QT 5 Qg, TOTAL GATE CHARGE (nC) 1000 10 6 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS) C, CAPACITANCE (pF) 3600 t, TIME (ns) VGS = 0 V VDS = 0 V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTB45N06L, NTBV45N06L 280 ID = 45 A 240 200 160 120 80 40 0 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTB45N06L, NTBV45N06L 1 EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RqJC at Steady State r(t), 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RqJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.001 0.00001 0.0001 0.001 0.1 0.01 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 6 10 100 1000 NTB45N06L, NTBV45N06L PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E V W −B− 4 1 2 A S 3 −T− SEATING PLANE K J G D W H 3 PL 0.13 (0.005) M T B M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN VARIABLE CONFIGURATION ZONE N R P U L M DIM A B C D E F G H J K L M N P R S V L M L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 NTB45N06L, NTBV45N06L ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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