FAN5365 1A / 0.8A, 6MHz Digitally Programmable Regulator Features Description The FAN5365 is a high-frequency, ultra-fast transient response, synchronous step-down, DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors. The FAN5365 supports up to 800mA or 1A load current. High Efficiency (>88%) at 6MHz 800mA or 1A Output Current Regulation Maintained with VIN from 2.3V to 5.5V 6-Bit VOUT Programmable from 0.75 to 1.975V 6MHz Fixed-Frequency Operation (PWM Mode) Excellent Load and Line Transient Response Small Size, 470nH Inductor Solution ±2% DC Voltage Accuracy in PWM Mode 25ns Minimum On-Time High-Efficiency, Low-Ripple, Light-Load PFM Smooth Transition between PWM and PFM 40μA Operating PFM Quiescent Current 2 I C™-Compatible Interface up to 3.4Mbps 2 Pin-Selectable or I C™ Programmable Output Voltage 9-Bump, 1.27 x 1.29mm, 0.4mm Pitch WLCSP Package Applications ® ® 3G, WiFi , WiMAX™, and WiBro Data Cards ® Netbooks , Ultra-Mobile PCs SmartReflex™-Compliant Power Supply Split Supply DSPs and μP Solutions OMAP™, XSCALE™ ® Handset Graphic Processors (NVIDIA , ATI) The FAN5365 is ideal for mobile phones and similar portable applications powered by a single-cell Lithium-Ion battery. 2 With an output voltage range adjustable via I C™ interface from 0.75V to 1.975V, it supports low-voltage DSPs and processors, core power supplies, and memory modules in smart phones, data cards, and hand-held computers. The FAN5365 operates at 6MHz (nominal) fixed switching frequency in PWM mode. During light-load conditions, the regulator includes a PFM mode to enhance light-load efficiency. The regulator transitions smoothly between PWM and PFM modes with no glitches on VOUT. In hardware shutdown, the current consumption is reduced to less than 200nA. The serial interface is compatible with fast / standard mode, 2 fast mode plus, and high-speed mode I C specifications, allowing transfers up to 3.4Mbps. This interface is used for dynamic voltage scaling with 12.5mV voltage steps, for reprogramming the mode of operation (PFM or forced PWM), or to disable/enable the output voltage. The chip's advanced protection features include short-circuit protection and current and temperature limits. During a sustained over-current event, the IC shuts down and restarts after a delay to reduce average power dissipation into a fault. During startup, the IC controls the output slew rate to minimize input current and output overshoot at the end of soft-start. The IC maintains a consistent soft-start ramp, regardless of output load during startup. The FAN5365 is available in a 1.27 x 1.29mm, 9-bump WLCSP package. All trademarks are the property of their respective owners © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator November 2010 (1) Part Number Option Slave Address LSB A2 FAN5365UC00X 00 FAN5365UC02X 0 A1 Output Current A0 1 mA 0 Power-up Defaults VOUT Programming 800 Min. Max. 0.7500 Package VSEL0 VSEL1 (3) 1.05 1.20 WLCSP-09 (3) 0.95 1.10 WLCSP-09 1.4375 02 1 1 0 800 0.7500 (2) 03 0 0 0 1000 0.7500 1.5375 1.00 1.20 WLCSP-09 (2) 06 0 0 0 1000 1.1875 1.9750 1.80 1.80 WLCSP-09 FAN5365UC03X FAN5355UC06X 1.4375 Notes: 1. The “X” designator on the part number indicates tape and reel packaging. 2. Preliminary; not full production release at this time. Contact a Fairchild representative for information. 3. VOUT is limited to the maximum voltage for all VSEL codes greater than the maximum VOUT listed. Typical Application VIN VIN Q1 CIN EN VSEL SDA VOUT SW MODULATOR Q2 L COUT SCL PGND AGND VOUT Figure 1. Typical Application Table 1. Recommended External Components Component L (LOUT) COUT (5) CIN Description 470nH Nominal Vendor Murata, TDK, FDK 0603 (1.6x0.8x0.8), 10μF X5R Various 0402 (1x0.5x0.25), 4.7μF X5R Taiyo-Yuden Parameter L (4) Min. Typ. Max. Units 390 470 600 nH DCR (Series R) (6) C 80 2.2 10.0 1.6 4.7 mΩ 15.0 μF μF Notes: 4. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases when increasing current). 5. A capacitor similar to CIN can be used for COUT. With 1.4V of bias, a 4.7μF 0402 capacitor minimum value is 2.5μF. The regulator is stable, but transient response degraded due to large signal effects. 6. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects. CIN is biased with a higher voltage which reduces its effective capacitance by a larger amount. © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 2 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Ordering Information A1 A2 A3 A3 A2 A1 B1 B2 B3 B3 B2 B1 C1 C2 C3 C3 C2 C1 Bumps Facing Down Bumps Facing Up Figure 2. WLCSP-09, 0.4mm Pitch Pin Definitions Pin # Name Description A1 VSEL Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior 2 can be overridden through I C register settings. This pin should not be left floating. A2 VIN Input Voltage. Connect to input power source. The connection from this pin to CIN should be as short as possible. A3 SDA SDA. I C interface serial data. This pin should not be left floating. B1 SW Switching Node. Connect to output inductor. B2 SCL SCL. I C interface serial clock. This pin should not be left floating. B3 EN Enable. When this pin is HIGH, the circuit is enabled. When LOW, part enters shutdown mode and input current is minimized. This pin should not be left floating. C1 VOUT Output Voltage Monitor. Tie this pin to the output voltage at COUT. This is a signal input pin to the control circuit and does not carry DC current. C2 PGND Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The connection from this pin to the bottom of CIN should be as short as possible. C3 AGND Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. AGND should be connected to PGND at a single point. 2 2 © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 3 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Min. VIN, SW Pins –0.3 6.5 VOUT –0.3 2.5 Other Pins ESD Max. V (7) –0.3 Electrostatic Discharge Protection Units VIN + 0.3 Human Body Model, JESD22-A114 3 Charged Device Model, JESD22-C101 1 KV TJ Junction Temperature –40 +150 °C TSTG Storage Temperature –65 +150 °C +260 °C TL Lead Soldering Temperature, 10 Seconds Note: 7. Lesser of 6.5V or VCC+0.3V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VIN VCCIO Parameter Supply Voltage SDA and SCL Voltage Swing (8) Min. Max. Units 2.3 5.5 V 1.2 2.0 V TA Ambient Temperature –40 +85 °C TJ Junction Temperature –40 +125 °C Note: 2 8. The I C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage 2 swings greater than 2.5V are required (for example, if the I C bus is pulled up to VIN), the minimum tHD;DAT must be 2 increased to 80ns. Most I C masters change SDA near the midpoint between the falling and rising edges of SCL, which provides ample tHD;DAT. Dissipation Ratings(9) Package Wafer-Level Chip-Scale Package (WLCSP) (10) RθJA 110ºC/W Power Rating at TA ≤ 25°C Derating Factor > TA = 25ºC 900mW 9mW/ºC Notes: 9. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max) - TA ] / θJA. 10. This thermal data is measured with a high-K board (four-layer board, according to the JESD51-7 JEDEC standard). © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 4 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Absolute Maximum Ratings Unless otherwise noted, over the recommended operating range for VIN and TA, EN = VSEL = SCL = SDA = 1.8V, and register VSEL0[6] bit = 1. Typical values are at VIN = 3.6V, TA = 25°C. Circuit and components according to Figure 1. Symbol Parameter Conditions Min. Typ. Max. Units IO = 0mA, PFM Mode, 2.3V<=VIN<=4.5V IO = 0mA, PFM Mode, 2.3V<=VIN<=5.5V IO = 0mA, 6MHz PWM Mode 40 40 6.3 55 65 μA EN = GND 0.1 1.0 N/A N/A 2.18 2.02 160 2.25 Power Supplies IQ ISD VUVLO Quiescent Current Shutdown Supply Current Under-Voltage Lockout Threshold VUVHYST Under-Voltage Lockout Hysteresis ENABLE, VSEL, SDA, SCL VIH HIGH-Level Input Voltage VIL LOW-Level Input Voltage IIN Input Bias Current Power Switch and Protection P-Channel MOSFET On RDS(ON)P Resistance ILKGP P-Channel Leakage Current N-Channel MOSFET On RDS(ON)N Resistance ILKGN N-Channel Leakage Current ILIMPK P-MOS Current Limit TLIMIT Thermal Shutdown THYST Thermal Shutdown Hysteresis Frequency Control (11) fSW Switching Frequency Output Regulation VOUT VOUT Accuracy EN = VIN, EN_DCDC bit = 0, SDA = SCL = 1.8V (Software Shutdown) VIN Rising VIN Falling 1.95 mA 1.05 Input Tied to GND or VIN 0.01 VIN = 3.6V 300 VDS = 5.5V 0.2 VIN = 3.6V 200 VDS = 5.5V Options 00, 02 Options 03, 06 IOUT(DC) = 0, Forced PWM, VOUT = VSEL1 Default Value 2.3V ≤ VIN ≤ 5.5V, VOUT from Minimum to Maximum, IOUT(DC) = 0 to 1A, Forced PWM 2.3V ≤ VIN ≤ 5.5V, VOUT from Minimum to Maximum, IOUT(DC) = 0 to 1A, Auto PWM/PFM ΔVOUT ΔILOAD Load Regulation IOUT(DC) = 0 to 1A, Forced PWM ΔVOUT ΔVIN Line Regulation VRIPPLE Output Ripple Voltage V V mV V V μA mΩ 1.0 μA mΩ μA 0.3 1350 1550 150 20 1.0 1600 1840 6.0 6.6 MHz –1.5 1.5 % –2.0 2.0 % –2.0 3.5 % 1150 1300 PWM Operation 0.4 1.00 μA 5.4 mA °C °C –0.2 %/A 2.3V ≤ VIN ≤ 5.5V, IOUT(DC) = 300mA, Forced PWM 0 %/V PWM Mode, VOUT = 1.2V PFM Mode, IOUT(DC) = 10mA 4 16 mVP-P mVP-P Continued on the following page… © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 5 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Electrical Specifications Unless otherwise noted, over the recommended operating range for VIN and TA, EN = VSEL = SCL = SDA = 1.8V, and register VSEL0[6] bit = 1. Typical values are at VIN = 3.6V, TA = 25°C. Circuit and components according to Figure 1. Symbol Parameter Conditions Min. Typ. Max. Units DAC Resolution 6 Differential Nonlinearity Bits Monotonicity Assured by Design 0.8 LSB Timing 2 2 I CEN EN HIGH to I C Start tV(L-H) VOUT LOW to HIGH Settling Transition from 0.75V to 1.438V VOUT Settled to within 2% of Setpoint Regulator Enable to Regulated VOUT RLOAD > 5Ω, to VOUT = Power-up Default μs 250 μs 7 Soft-Start tSS 140 180 μs Notes: 11. Limited by the effect of tOFF minimum (see Figure 14 in Typical Performance Characteristics). Block Diagram VIN VIN Q1 DAC EN VSEL SDA I2C INTERFACE AND LOGIC SCL CIN REF FPWM EN_REG VOUT SW SOFT START Q2 L COUT MODULATOR PGND CLK VOUT AGND 6 Mhz Osc Figure 3 Block Diagram © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 6 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Electrical Specifications (Continued) Guaranteed by design. Symbol Parameter fSCL SCL Clock Frequency tBUF Bus-free Time between STOP and START Conditions tHD;STA tLOW tHIGH START or Repeated START Hold Time SCL LOW Period SCL HIGH Period tSU;STA Repeated START Setup Time tSU;DAT Data Setup Time tHD;DAT Data Hold Time tRCL SCL Rise Time (8) Conditions Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus Standard Mode Fast Mode Fast Mode Plus High-Speed Mode Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode Standard Mode Fast Mode Fast Mode Plus High-Speed Mode Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Min. Typ. Max. Units 100 400 1000 3400 1700 kHz 4.7 1.3 0.5 4 600 260 160 4.7 1.3 0.5 160.0 320.0 4 600 260 60 120 4.7 600.0 260.0 160.0 250 100 50 10 0 0 0 0 0 20+0.1CB 20+0.1CB 20+0.1CB 10 20 μs μs ns ns ns μs ns ns ns ns μs ns ns ns ns μs ns ns ns ns 3.45 900.00 450.00 70.00 150.00 1000 300 120 80 160 μs ns ns ns ns ns Continued on the following page… © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 7 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator I2C Timing Specifications Guaranteed by design. Symbol Parameter tFCL SCL Fall Time tRCL1 Rise Time of SCL after a Repeated START Condition and after ACK Bit tRDA SDA Rise Time tFDA SDA Fall Time tSU;STO CB Stop Condition Setup Time Conditions Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Fast Mode Plus High-Speed Mode Capacitive Load for SDA and SCL © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 Min. Typ. 20+0.1CB 20+0.1CB 20+0.1CB 10 20 10 20 20+0.1CB 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 20+0.1CB 10 20 4 600 120 160 Max. 300 300 120 40 80 80 160 1000 300 120 80 160 300 300 120 80 160 400 Units ns ns ns ns μs ns ns ns pF www.fairchildsemi.com 8 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator I2C Timing Specifications (Continued) tF tSU;STA tBUF SDA tR SCL TSU;DAT tHD;STO tHIGH tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START STOP START 2 Figure 4. I C Interface Timing for Fast Plus, Fast, and Slow Modes tFDA tRDA REPEATED START tSU;DAT STOP SDAH tSU;STA tRCL1 SCLH tFCL tLOW tHD;STA REPEATED START tRCL tSU;STO tHIGH tHD;DAT note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. 2 Figure 5. I C Interface Timing for High-Speed Mode © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 9 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Timing Diagrams 100% 100% 90% 90% 80% 80% Efficiency Efficiency Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. 70% 2.3V Auto PFM/PWM 60% 70% 2.3V Auto PFM/PWM 2.7V Auto PFM/PWM 60% 2.7V Auto PFM/PWM 3.6V Auto PFM/PWM 3.6V Auto PFM/PWM 4.2V Auto PFM/PWM 4.2V Auto PFM/PWM 50% 50% 5.5V Auto PFM/PWM 5.5V Auto PFM/PWM 3.6V Forced PWM 3.6V Forced PWM 40% 1 10 100 40% 1 1000 Output Current (mA) 100% 100% 90% 90% 80% 80% Auto PFM/PWM Efficiency Efficiency 70% 50% Forced PWM 40% VIN=3.6V Vout=0.75V 30% 70% Auto PFM/PWM 60% Forced PWM 40% 10% 10% 100 0% 1 1000 10 100 1000 Output Current (mA) Output Current (mA) Figure 9. Efficiency, Auto PWM/PFM vs. Forced PWM at VOUT = 1.4375V Figure 8. Efficiency, Auto PWM/PFM vs. Forced PWM at VOUT = 0.75V © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 VIN=3.6V VOUT=1.4375V 30% 20% 10 1000 50% 20% 0% 1 100 Figure 7. Efficiency vs. Load and Input Supply at VOUT = 1.2V Figure 6. Efficiency vs. Load and Input Supply at VOUT = 1.1V 60% 10 Output Current (mA) www.fairchildsemi.com 10 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. 1.112 1.212 1.110 1.210 1.108 1.208 1.106 1.206 Auto PFM/PWM Auto PFM/PWM 1.204 V out( V ) V out( V ) 1.104 Forced PWM 1.102 Forced PWM 1.202 1.100 1.200 1.098 1.198 1.096 1.196 1.094 1.194 1.092 1.192 1 10 100 Output Current(mA) 1000 1 10 100 Output Current(mA) 1000 Figure 11. Load Regulation, Auto PFM / PWM and Forced PWM at VOUT = 1.2V Figure 10. Load Regulation, Auto PFM / PWM and Forced PWM at VOUT = 1.1V 1.450 0.760 1.448 0.758 Auto PFM/PWM 0.756 Auto PFM/PWM 1.446 Forced PWM Forced PWM 1.444 1.442 V out( V ) V out( V ) 0.754 1.440 0.752 1.438 1.436 0.750 1.434 0.748 1.432 1.430 0.746 1 10 100 Output Current(mA) 1 1000 10 Output Current(mA) 100 1000 Figure 13. Load Regulation, Auto PFM / PWM and Forced PWM at VOUT = 1.4375V Figure 12. Load Regulation, Auto PFM / PWM and Forced PWM at VOUT = 0.75V 7.0 Frequency (MHz) 6.0 5.0 4.0 3.0 Vo=1.4375V Vo=1.36V 2.0 1.0 Vo=1.3V Vo=1.2V 0 200 400 600 800 1000 1200 IOUT (mA) Figure 14. Effect of tOFF(MIN) on Reducing the PWM Switching Frequency, VIN=2.3V © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 11 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. Quiescent Current (µA) 55 15 -40°C 25°C 85°C Quiescent Current (mA) 60 50 45 40 35 30 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 12 -40°C 25°C 85°C 9 6 3 2.3 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VIN (V) VIN (V) Figure 15. Quiescent Current in PFM Mode vs. Input Voltage and Temperature Figure 16. Quiescent Current in PWM Mode vs. Input Voltage and Temperature 0.8 80 -40°C 25°C 85°C VOUT =1.2V 70 Rejection Ratio (dB) Shutdown Current (µA) 1.0 0.6 0.4 0.2 VOUT =1.05V 60 50 40 30 20 10 0.0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 0 5.5 0.1 1 10 10 0 100 0 VIN (V) Frequency (KHz) Figure 17. Shutdown Current (EN = 0) vs. Input Voltage and Temperature Figure 18. VIN Ripple Rejection (PSRR) in Forced PWM at 200mA © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 12 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. Figure 19. Combined Line/Load Transient 3.0 to 3.6VIN Combined with 500 to 50mA Load Transient Figure 20. Combined Line/Load Transient 3.6 to 3.0VIN Combined with 50 to 500mA Load Transient Figure 21. Combined Line/Load Transient 3.0 to 3.6VIN Combined with 800 to 200mA Load Transient Figure 22. Combined Line/Load Transient 3.6 to 3.0VIN Combined with 200 to 800mA Load Transient © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 13 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. Figure 23. VSEL Transition, Single Step (DefSlew = 7), RLOAD = 24Ω Figure 24. VSEL Transition, Single Step (DefSlew = 7), RLOAD = 4Ω Figure 25. VSEL Transition, DefSlew = 0, RLOAD = 24Ω Figure 26. VSEL Transition, DefSlew = 0, RLOAD = 4Ω © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 14 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. Figure 27. VSEL Transition, VSEL 1 to 0, RLOAD = 24Ω Figure 28. VSEL Transition, VSEL 1 to 0, RLOAD = 4Ω Figure 29. Shutdown, Output Discharge On Figure 30. Shutdown, Output Discharge Off © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 15 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Unless otherwise specified, Auto PWM/PFM, VIN = 3.6V, SCL = SCA = VSEL = EN = 1.8V, TA = 25°C; circuit and components according to Figure 1. Figure 31. Metallic Short Applied at VOUT Figure 32. Over-Current Fault Response, RLOAD = 500mΩ Figure 33. Soft Start, No Load Figure 34. Soft Start, RLOAD = 1.5Ω © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 16 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Typical Characteristics Table 2. VSEL vs. VOUT The FAN5365 is a synchronous buck regulator that typically operates at 6MHz with moderate to heavy load currents. At light load currents, the converter operates in power-saving PFM mode. The regulator automatically transitions between fixed-frequency PWM mode and variable-frequency PFM mode to maintain the highest possible efficiency over the full range of load current. VSEL Value Dec (NVSEL) Binary 0 000000 1 000001 2 000010 3 000011 4 000100 5 000101 6 000110 7 000111 8 001000 9 001001 10 001010 11 001011 12 001100 13 001101 14 001110 15 001111 16 010000 17 010001 18 010010 19 010011 20 010100 21 010101 22 010110 23 010111 24 011000 25 011001 26 011010 27 011011 28 011100 29 011101 30 011110 31 011111 32 100000 33 100001 34 100010 35 100011 36 100100 37 100101 38 100110 39 100111 40 101000 41 101001 42 101010 43 101011 44 101100 45 101101 46 101110 47 101111 48 110000 49 110001 50 110010 51 110011 52 110100 53 110101 54 110110 55 110111 56 111000 57 111001 58 111010 59 111011 60 111100 61 111101 62 111110 63 111111 The FAN5365 uses a very fast, non-linear control architecture to achieve excellent transient response with minimum-sized external components. 2 The FAN5365 integrates an I C-compatible interface, allowing transfers up to 3.4Mbps. This communication interface can be used to: Dynamically re-program the output voltage in 12.5mV increments Reprogram the mode of operation to enable or disable PFM mode Control voltage transition slew rate Enable / disable the regulator. 2 For more details, refer to the I C Interface and Register Description sections. Output Voltage Programming VOUT is programmed according to the following equations: Option (12) 00, 02, 03 06 VOUT Equation VOUT = 0.75 + NVSEL • 12.5mV (1) VOUT = 1.1875 + NVSEL • 12.5mV (2) Note: 12. For option 00 and 02, the maximum voltage is 1.4375V. © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 00, 02 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 VOUT 03 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 06 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 1.6125 1.6250 1.6375 1.6500 1.6625 1.6750 1.6875 1.7000 1.7125 1.7250 1.7375 1.7500 1.7625 1.7750 1.7875 1.8000 1.8125 1.8250 1.8375 1.8500 1.8625 1.8750 1.8875 1.9000 1.9125 1.9250 1.9375 1.9500 1.9625 1.9750 www.fairchildsemi.com 17 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Circuit Description All internal circuits remain de-biased and the IC is in a very low quiescent current state until the following are true: VIN is above its rising UVLO threshold, and EN is HIGH. Light-Load (PFM) Operation The FAN5365 provides a low ripple, single-pulse, PFM mode that ensures: 2 At that point, the IC begins a soft-start cycle, its I C interface is enabled, and its registers are loaded with their default values. During the initial soft-start, VOUT ramps linearly to the setpoint programmed in the VSEL register selected by the VSEL pin. The soft-start features a fixed output voltage slew rate of 20V/ms and achieves regulation approximately 90μs after EN rises. PFM mode is enabled during soft-start until the output is in regulation, regardless of the MODE bit settings. This allows the regulator to start into a partially charged output without discharging it; in other words, the regulator does not allow current to flow from the load back to the battery. Smooth transitions between PFM and PWM modes Single-pulse operation for low ripple Predictable PFM entry and exit currents. PFM begins after the inductor current has become discontinuous, crossing zero during the PWM cycle for 32 consecutive cycles. PFM exit occurs when discontinuous current mode (DCM) operation cannot supply sufficient current to maintain regulation. During PFM mode, the inductor current ripple is about 40% higher than in PWM mode. The load current required to exit PFM mode is thereby about 20% higher than the load current required to enter PFM mode, providing sufficient hysteresis to prevent “mode chatter.” As soon as the output has reached its setpoint, the control forces PWM mode for about 85μs to allow all internal control circuits to calibrate. While PWM ripple voltage is typically less than 4mVP-P, PFM ripple voltage can be up to 30mVP-P during very light load. To prevent significant undershoot when a load transient occurs, the initial DC setpoint for the regulator in PFM mode is set 10mV higher than in PWM mode. This offset decays to about 5mV after the regulator has been in PFM mode for ~100μs. The maximum instantaneous voltage in PFM is 30mV above the setpoint. Table 3. Soft-Start Timing Symbol Description Value (μs) tSSDLY Time from EN to start of softstart ramp 25 tREG VOUT ramp start to regulation (VSEL–0.1) X 53 tPOK PWROK (CONTROL2[5]) rising from tREG 11 PFM mode can be disabled by writing to the mode control bits: CONTROL1[3:0] (see Table 5) tCAL Regulator stays in PWM mode during this time 10 Output Voltage Transitions The IC regulates VOUT to one of two setpoint voltages, as determined by the VSEL pin and the HW_nSW bit. EN t REG VSEL Table 5. t SSD LY VOUT t CA L (FPWM) 0 VSEL Pin HW_nSW Bit VOUT Setpoint t P OK PWROK Figure 35. Soft-Start Timing Table 4. EN_DCDC Behavior 2 EN_DCDC Bit EN Pin IC REGULATOR 0 0 OFF OFF 1 1 ON ON 1 0 OFF OFF 0 1 ON OFF © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 VOUT Setpoint and Mode Control MODE_CTRL, CONTROL1[3:2] = 00 PFM 0 1 VSEL0 Allowed 1 1 VSEL1 Per MODE1 x 0 VSEL1 Per MODE1 If HW_nSW = 0, VOUT transitions are initiated through the following sequence: 1. 2. Write the new setpoint in VSEL1. Write desired transition rate in DEFSLEW, CONTROL2[2:0], and set the GO bit in CONTROL2[7]. If HW_nSW = 1, VOUT transitions are initiated either by changing the state of the VSEL pin or by writing to the VSEL register selected by the VSEL pin. www.fairchildsemi.com 18 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Software Enable The EN_DCDC bit, VSELx[7], can be used to enable the regulator in conjunction with the EN pin. Setting EN_DCDC with EN HIGH begins the soft-start sequence described above. Power-Up, EN, and Soft-Start All positive VOUT transitions inhibit PFM until the transition is complete, which occurs at the end of tPOK(L-H). When transitioning to a higher VOUT, the regulator can perform the transition using multi-step or single-step mode. Negative Transitions When moving from VSEL = 1 to VSEL = 0, the regulator enters PFM mode, regardless of the condition of the MODE bits, and remains in PFM until the transition is complete. Reverse current through the inductor is blocked, and the PFM minimum frequency control inhibited, until the new setpoint is reached; at which time, the regulator resumes control using the mode established by MODE_CTRL. The transition time from VHIGH to VLOW is controlled by load current and output capacitance as: Multi-Step Mode: The internal DAC is stepped at a rate defined by DEFSLEW, CONTROL2[2:0], ranging from 000 to 110. This mode minimizes the current required to charge COUT and thereby minimizes the current drain from the battery when transitioning. The PWROK bit, CONTROL2[5], remains LOW until about 1.5μs after the DAC completes its ramp. V HIGH t V (H−L ) = COUT • VHIGH − VLOW ILOAD VOUT (3) V HIGH V LOW VSEL tPOK(L-H) PWROK VOUT V LOW Figure 36. Multi-Step VOUT Transition VSEL Single-Step Mode: Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC is immediately set to the higher voltage and the regulator performs the transition as quickly as its current limit circuit allows, while avoiding excessive overshoot. Figure 38. Negative VOUT Transition Protection Features Current Limit / Auto-Restart The regulator includes cycle-by-cycle current limiting, which prevents the instantaneous inductor current from exceeding the “PMOS Current Limit” threshold. It is good practice to reduce the load current before making positive VSEL transitions. This reduces the time required to make positive load transitions and avoids current–limitinduced overshoot. The IC enters “fault” mode after sustained over-current. If current limit is asserted for more than 32 consecutive cycles (about 20μs), the IC returns to shutdown state and remains in that condition for ~80μs. After that time, the regulator attempts to restart with a normal soft-start cycle. If the fault has not cleared, it shuts down ~20μs later. tV(L-H) 98 % V HIGH If the fault is a short circuit, the initial current limit is ~30% of the normal current limit, which produces a very small drain on the system power source. VOUT Thermal Protection When the junction temperature of the IC exceeds 150°C, the device turns off all output MOSFETs and remains in a low quiescent current state until the die cools to 130°C before starting a normal soft-start cycle. VLOW VSEL PWROK tPOK(L-H) PWROK Figure 37 shows single-step transition timing. tV(L-H) is the time it takes the regulator to settle to within 2% of the new setpoint, typically 7μs for a full-range transition. The PWROK bit, CONTROL2[5], goes LOW until the transition is complete and VOUT settled. This typically occurs ~2μs after tV(L-H). V HIGH tV(L-H) tPOK(L-H) Figure 37. Single-Step VOUT Transition © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 19 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Positive Transitions Data change allowed SDA tH I2C Interface The FAN5365’s serial interface is compatible with standard, 2 fast, fast plus, and high-speed mode I C bus specifications. The FAN5365’s SCL line is an input and its SDA line is a bidirectional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. t SU SCL Figure 39. Data Transfer Timing Slave Address Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a “START” condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 40. In Table 6, A1 and A0 are according to the Ordering Information table on page 2. SDA t HD;STA Slave Address MS Bit 2 Table 6. I C Slave Address 7 6 5 4 3 2 1 0 1 0 0 1 A2 A1 A0 R/ W SCL Figure 40. Start Bit In Hex notation, the slave address assumes a 0 LSB. For example, the hex slave address of option 00 is 94H. A transaction ends with a “STOP” condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, shown in Figure 41. Register Addressing FAN5365 has four user-accessible registers: Slave Releases Master Drives 2 Table 7. I C Register Address SDA Address 7 6 5 4 3 2 1 0 VSEL0 0 0 0 0 0 0 0 0 VSEL1 0 0 0 0 0 0 0 1 CONTROL1 0 0 0 0 0 0 1 0 CONTROL2 0 0 0 0 0 0 1 1 tHD;STO ACK(0) or NACK(1) SCL Figure 41. Stop Bit During a read from the FAN5365 (Figure 44), the master issues a “Repeated Start” command after sending the register address and before resending the slave address. The “Repeated Start” is a 1-to-0 transition on SDA while SCL is HIGH, as shown in Figure 42. Bus Timing As shown in Figure 39, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. Slave Releases SDA tSU;STA tHD;STA ACK(0) or NACK(1) SLADDR MS Bit SCL Figure 42. Repeated Start Timing © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 20 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Under-Voltage Lockout (UVLO) The IC turns off all MOSFETs and remains in a low quiescent current state until VIN rises above the UVLO threshold. Read and Write Transactions The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) modes are identical, except the bus speed for HS mode is 3.4MHz. HS mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus mode (less than 1MHz clock) and slaves do not acknowledge (ACK) this transmission. The following figures outline the sequences for data read and write. Bus control is signified by the shading of the Master Drives Bus Symbol Definition S START, Figure 40. ACK. The slave drives SDA to 0 to acknowledge the preceding packet. NACK. The slave sends a 1 to NACK the preceding packet. Repeated START, see Figure 42. STOP, see Figure 41. A A The bus remains in HS mode until a stop bit (Figure 41) is sent by the master. While in HS mode, packets are separated by repeated start conditions. S Slave Address 0 . Table 8. I2C Bit Definitions for Figure 43 and Figure 44 The master then generates a repeated start condition (Figure 42) that causes all slaves on the bus to switch to HS 2 mode. The master then sends I C packets, as described above, using the HS mode clock rate and timing. 7 bits Slave Drives Bus and packet, defined as All addresses and data are MSB first. R P 0 8 bits 0 8 bits 0 A Reg Addr A Data A P Figure 43. Write Transaction 7 bits S Slave Address 0 0 8 bits 0 A Reg Addr A 7 bits R Slave Address 1 0 8 bits 1 A Data A P Figure 44. Read Transaction Register Descriptions both the default values and the bit’s type (as defined in Table 10) for each available option. Default Values Each option of the FAN5365 (see Table 9) has different default values for the some of the register bits. Table 9 defines Table 9. Default Values and Bit Types for VSEL and CONTROL Registers VSEL0 4 3 Option 7 6 5 00 02 03 06 1 1 1 1 1 1 1 1 0 0 0 1 Option 7 CONTROL1 6 5 4 00, 02 03, 06 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 2 1 0 VOUT Option 7 6 5 0 0 1 0 0 0 0 0 0 0 0 1 1.05 0.95 1.00 1.80 00 02 03 06 1 1 1 1 1 1 1 1 1 0 1 1 3 2 1 0 Option 7 0 0 0 0 0 0 0 0 00, 02 03, 06 0 0 VSEL1 4 3 0 1 0 1 0 1 0 0 CONTROL2 6 5 4 1 0 0 0 0 0 2 1 0 VOUT 1 1 1 0 0 0 0 0 0 0 0 1 1.20 1.10 1.20 1.80 3 2 1 0 0 0 1 1 1 1 1 1 Table 10. Bit Type Definitions for Table 9 # # # Active Bit Changing this bit changes the behavior of the converter, as described below. Disabled Converter logic ignores changes made to this bit. Bit can be written and read-back. 2 Read-Only Writing to this bit through I C does not change the read-back value, nor does it change converter behavior. © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 21 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator High-Speed (HS) Mode Table 11 defines the operation of each register bit. Superscript characters define the default state for each 0,2,3,6 option. Superscripts signify the default values for options 00, 02, 03, and 06, respectively. default for all options. A signifies the Table 11. Bit Definitions Bit Name Value VSEL0 7 EN_DCDC 6 Reserved 5:0 DAC[5:0] VSEL1 7 EN_DCDC 6 Reserved 5:0 DAC[5:0] CONTROL1 0 A 1 A 1 A Table 9 0 A 1 A 1 A Table 9 7:6 Reserved 10 5 Reserved 1 A Description Register Address: 00 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. 6-bit DAC value to set VOUT. Register Address: 01 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. 6-bit DAC value to set VOUT. Register Address: 02 Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be 2 used to distinguish between vendors via I C. A VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit. VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH and VOUT = VSEL0 when VSEL is LOW. Operation follows MODE0, MODE1. PFM with automatic transitions to PWM, regardless of VSEL. PFM disabled (forced PWM), regardless of VSEL. PFM with automatic transitions to PWM, regardless of VSEL. PFM disabled (forced PWM) when regulator output is controlled by VSEL1. PFM with automatic transitions to PWM when regulator output is controlled by VSEL1. 0 4 HW_nSW A 1 A 3:2 MODE_CTRL 1 MODE1 0 MODE0 00 01 10 11 A 0 1 A 0 1 CONTROL2 A 7 GO 6 OUTPUT_ DISCHARGE 5 PWROK (read only) 4:3 Reserved 2:0 DEFSLEW 0 1 3,6 0 0,2 1 0 1 A 00 000 001 010 011 100 101 110 A 111 PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation of the regulator. Register Address: 03 This bit has no effect when HW_nSW = 1. At the end of a VOUT transition, this bit is reset to 0. Starts a VOUT transition if HW_nSW = 0. When the regulator is disabled, VOUT is not discharged. When the regulator is disabled, VOUT discharges through an internal pull-down. VOUT is not in regulation or is in current limit. VOUT is in regulation. © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 VOUT slews at 0.15mV/μs during positive VOUT transitions. VOUT slews at 0.30mV/μs during positive VOUT transitions. VOUT slews at 0.60mV/μs during positive VOUT transitions. VOUT slews at 1.20mV/μs during positive VOUT transitions. VOUT slews at 2.40mV/μs during positive VOUT transitions. VOUT slews at 4.80mV/μs during positive VOUT transitions. VOUT slews at 9.60mV/μs during positive VOUT transitions. Positive VOUT transitions use single-step mode (see Figure 37). www.fairchildsemi.com 22 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Bit Definitions FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator Physical Dimensions 0.03 C 2X F A E 0.40 B Ø0.20 Cu Pad A1 PIN A1 INDEX AREA 0.40 D Ø0.30 Solder Mask 0.03 C 2X LAND PATTERN RECOMMENDATION (NSMD PAD TYPE) TOP VIEW 0.06 C 0.05 C 0.625 0.547 C SEATING PLANE D 0.378±0.018 E 0.208±0.021 SIDE VIEWS NOTES: A. NO JEDEC REGISTRATION APPLIES. Ø0.260±0.020 9X 0.40 C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 1994. C B A 0.40 B. DIMENSIONS ARE IN MILLIMETERS. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. (Y)±0.018 E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS ±39 MICRONS (547-625 MICRONS). F 1 2 3 (X)±0.018 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. BOTTOM VIEW G. DRAWING FILNAME: MKT-UC009ABrev2 Figure 45. 9-Ball WLCSP, 3X3 Array, 0.4mm Pitch, 250µm Ball Product-Specific Dimensions Product D E X Y FAN5365UC 1.290 +/-0.030 1.270 +/-0.030 0.250 0.250 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 23 FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator © 2008 Fairchild Semiconductor Corporation FAN5365 • Rev. 1.0.4 www.fairchildsemi.com 24