TI CSD17483F4R 30-v, n-channel nexfet power mosfet Datasheet

CSD17483F4
www.ti.com
SLPS447 – JULY 2013
30-V, N-Channel NexFET™ Power MOSFET
Check for Samples: CSD17483F4
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
2
•
•
•
•
Low On Resistance
Low Qg and Qgd
Low Threshold Voltage
Ultra Small Footprint (0402 Case Size)
– 1.0 mm x 0.6 mm
Ultra Low Profile
– 0.35 mm Height
Integrated ESD Protection Diode
– Rated > 4kV HBM
– Rated > 2kV CDM
Pb and Halogen Free
RoHS Compliant
VDS
Drain to Source Voltage
Qg
Gate Charge Total (4.5V)
Qgd
Gate Charge Gate to Drain
RDS(on)
VGS(th)
•
•
V
pC
130
Drain to Source On Resistance
pC
VGS = 1.8V
370
VGS = 2.5V
240
VGS = 4.5V
200
Threshold Voltage
mΩ
0.85
V
Text Added For Spacing
ORDERING INFORMATION
Device
Qty
Media
CSD17483F4
3,000
7-Inch
Reel
CSD17483F4R
18,000
13-Inch
Reel
APPLICATIONS
•
•
30
1010
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Single Cell Battery Applications
Handheld and Mobile Applications
DESCRIPTION
The FemtoFET™ MOSFET technology has been
designed and optimized to minimize the footprint in
many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
.
Package
Ship
Femto(0402) 1.0mm x
0.6mm SMD Lead Less
Tape and
Reel
Text Added For Spacing
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
12
V
ID
Continuous Drain Current, TA = 25°C(1)
1.5
A
IDM
Pulsed Drain Current, TA = 25°C(2)
PD
Power Dissipation(1)
5
A
500
mW
4
kV
2
kV
–55 to 150
°C
2.7
mJ
Human Body Model (HBM)
ESD
Rating Charged Device Model (CDM)
TJ,
TSTG
Operating Junction and Storage
Temperature Range
EAS
Avalanche Energy, single pulse ID = 7.4A,
L = 0.1mH, RG = 25Ω
(1) Typical RθJA = 90°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
Typical Part Dimensions
Top View
m
D
60
1.
0.
00
m
m
5m
0.3
m
m
G
S
.
.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FemtoFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD17483F4
SLPS447 – JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 10V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250μA
RDS(on)
gfs
Drain to Source On Resistance
Transconductance
30
0.65
V
1
μA
100
nA
0.85
1.10
V
VGS = 1.8V, IDS =0.5A
370
550
mΩ
VGS = 2.5V, IDS =0.5A
240
310
mΩ
VGS = 4.5V, IDS = 0.5A
200
260
mΩ
VGS = 8V, IDS =0.5A
185
240
mΩ
VDS = 15V, IDS = 0.5A
2.4
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
RG
Series Gate Resistance
Qg
Gate Charge Total (4.5V)
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
tr
td(off)
Turn Off Delay Time
tf
Fall Time
145
190
pF
42
55
pF
2
3
pF
1300
pC
VGS = 0V, VDS = 15V,
f = 1MHz
Ω
23
1010
130
pC
220
pC
145
pC
1095
pC
Turn On Delay Time
3.3
ns
Rise Time
1.3
ns
10.6
ns
3.4
ns
VDS = 15V, IDS = 0.5A
VDS = 15V, VGS = 0V
VDS = 0V, VGS = 4.5V,
IDS = 0.5A,RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 0.5A, VGS = 0V
VDS= 15V, IF = 0.5A, di/dt = 300A/μs
0.73
0.9
V
1475
pC
5.5
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
RθJA
(1)
(2)
2
Thermal Resistance Junction to Ambient
Typical Values
(1)
Thermal Resistance Junction to Ambient (2)
2
UNIT
90
°C/W
250
°C/W
2
Device mounted on FR4 material with 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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SLPS447 – JULY 2013
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.2
3.2
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
3.6
2.8
2.4
2
1.6
1.2
0.8
VGS =8V
VGS =4.5V
0.4
0
0
0.1
VGS =2.5V
VGS =1.8V
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
1
VDS = 5V
2
1.8
1.6
1.4
1.2
1
0.8
0.6
TC = 125°C
TC = 25°C
TC = −55°C
0.4
0.2
0
0
G001
Figure 2. Saturation Characteristics
0.4
0.8
1.2
1.6
VGS - Gate-to-Source Voltage (V)
2
Product Folder Links: CSD17483F4
G001
Figure 3. Transfer Characteristics
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2.4
3
CSD17483F4
SLPS447 – JULY 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 0.5A
VDS =15V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
100
10
2
1
0
0
0.2
0.4
0.6
0.8 1 1.2 1.4 1.6
Qg - Gate Charge (nC)
1.8
2
1
2.2
0
3
6
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
30
400
ID = 250uA
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
−75
−25
25
75
125
TC - Case Temperature (ºC)
TC = 25°C Id = 0.5A
TC = 125ºC Id = 0.5A
360
320
280
240
200
160
120
80
175
0
2
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
ID =0.5A
1.3
1.2
1.1
1
0.9
0.8
0.7
−75
12
10
VGS = 1.8V
VGS = 8V
ISD − Source-to-Drain Current (A)
1.4
4
6
8
10
VGS - Gate-to- Source Voltage (V)
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
1.5
Normalized On-State Resistance
27
Figure 5. Capacitance
1.2
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
4
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
1
G001
Figure 9. Typical Diode Forward Voltage
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CSD17483F4
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SLPS447 – JULY 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
1ms
10ms
100ms
1s
DC
10
1
0.1
Single Pulse
Typical RthetaJA =250ºC/W(min Cu)
0.01
0.01
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
100
0.1
1
10
VDS - Drain-to-Source Voltage (V)
10
1
0.1
0.001
50
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Typical RthetaJA =90ºC/W(max Cu)
0.0
−50
−25
0
25
50
75
100 125
TA - AmbientTemperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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5
CSD17483F4
SLPS447 – JULY 2013
www.ti.com
MECHANICAL DATA
0402 Mechanical Dimensions
(1)
All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994)
(2)
This drawing is subject to change without notice
(3)
This package is a PB-Free solder land design
Recommended Minimum PCB Layout
(1)
6
All dimensions are in millimeters.
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CSD17483F4
www.ti.com
SLPS447 – JULY 2013
Recommended Stencil Pattern
(1)
All dimensions are in millimeters.
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7
CSD17483F4
SLPS447 – JULY 2013
www.ti.com
CSD17483F4 Embossed Carrier Tape Dimensions
(1)
8
Pin 1 will be oriented in the top right quadrant of the tape enclosure (Quadrant 2), closest to the carrier tape sprocket
holes.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
CSD17483F4
ACTIVE
PICOSTAR
YJC
3
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-250C-UNLIM
-55 to 150
CSD17483F4R
PREVIEW
PICOSTAR
YJC
3
18000
TBD
Call TI
Call TI
-55 to 150
DP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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