AD ADuM6401ARWZ Quad-channel isolators with integrated dc-to-dc converter Datasheet

Quad-Channel Isolators with
Integrated DC-to-DC Converter
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
VDD1 1
VIA/VOA 3
VIB/VOB 4
VIC/VOC 5
VID/VOD 6
REG
16 VISO
15 GNDISO
14 VIA/VOA
4-CHANNEL iCOUPLER CORE
13 VIB/VOB
ADuM6400/ADuM6401/
ADuM6402/ADuM6403/
ADuM6404
12 VIC/VOC
11 VID/VOD
10 VSEL
GND1 8
9
GNDISO
Figure 1. ADuM640x Block Diagram
VIA
VOA
VIB
VIC
VID
14
4
13
ADuM6400
5
12
6
11
VOB
VOC
VOD
08141-002
3
Figure 2. ADuM6400
VIB
VIC
VOD
3
14
4
13
ADuM6401
5
12
6
11
VOA
VOB
VOC
VID
08141-003
VIA
RS-232/RS-422/RS-485 transceivers
Medical isolation
AC/dc power supply startup bias and gate drives
Isolated sensor interface
Figure 3. ADuM6401
VIB
The ADuM640x1 devices are quad-channel digital isolators with
isoPower®, an integrated, isolated dc-to-dc converter. Based on
the Analog Devices, Inc., iCoupler® technology, the dc-to-dc
converter provides up to 500 mW of regulated, isolated power at
either 5.0 V or 3.3 V from a 5.0 V input supply, or 3.3 V from a
3.3 V supply at the power levels shown in Table 1. This eliminates
the need for a separate, isolated dc-to-dc converter in low power,
isolated designs. The iCoupler chip scale transformer technology
is used to isolate the logic signals and for the magnetic components
of the dc-to-dc converter. The result is a small form factor, total
isolation solution.
VOC
VOD
3
14
4
13
ADuM6402
5
12
6
11
VOA
VOB
VIC
VID
08141-004
VIA
GENERAL DESCRIPTION
Figure 4. ADuM6402
VOB
VOC
VOD
3
14
4
13
ADuM6403
5
12
6
11
VOA
VIB
VIC
VID
08141-005
VIA
Figure 5. ADuM6403
VOA
The ADuM640x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide for more information).
1
RECT
VDDL 7
APPLICATIONS
isoPower uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. Refer to the AN-0971 application note for board
layout recommendations at www.analog.com.
OSC
GND1 2
VOB
VOC
VOD
VIA
3
14
4
13
ADuM6404
VIB
VIC
5
12
6
11
VID
08141-006
isoPower integrated, isolated dc-to-dc converter
Regulated 3.3 V or 5 V output
Up to 500 mW output power
Quad dc-to-25 Mbps (NRZ) signal isolation channels
Schmitt trigger inputs
16-lead SOIC package with 7.6 mm creepage
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
5000 V rms for 1 minute per UL1577
CSA Component Acceptance Notice #5A
IEC 60950-1: 600 V rms (reinforced)
IEC 60601-1: 250 V rms (reinforced)
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
FUNCTIONAL BLOCK DIAGRAMS
08141-001
FEATURES
Figure 6. ADuM6404
Table 1. Power Levels
Input Voltage (V)
5
5
3.3
Output Voltage (V)
5
3.3
3.3
Output Power (mW)
500
330
200
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions ......................... 11
Applications ....................................................................................... 1
Truth Table .................................................................................. 15
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 16
Functional Block Diagrams ............................................................. 1
Terminology .................................................................................... 18
Revision History ............................................................................... 2
Applications Information .............................................................. 19
Specifications..................................................................................... 3
Theory of Operation .................................................................. 19
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 3
Printed Circuit Board (PCB) Layout ....................................... 19
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 5
Propagation Delay-Related Parameters ................................... 20
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 6
DC Correctness and Magnetic Field Immunity........................... 20
Thermal Analysis ....................................................................... 19
EMI Considerations ................................................................... 20
Package Characteristics ............................................................... 8
Power Consumption .................................................................. 21
Regulatory Approvals................................................................... 8
Power Considerations ................................................................ 21
Insulation and Safety-Related Specifications ............................ 8
Insulation Lifetime ..................................................................... 22
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 9
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Recommended Operating Conditions ...................................... 9
Absolute Maximum Ratings.......................................................... 10
ESD Caution ................................................................................ 10
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
4.7
5.0
1
1
75
200
180
625
5.4
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
CBO = 0.1 μF||10 μF, IISO = 90 mA
5
100
34
19
290
IDD1 (Q)
IDD1 (MAX)
30
VISO > 4.5 V
IISO = 100 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
ADuM6400
ADuM6401
ADuM6402
ADuM6403
ADuM6404
Symbol
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
2 Mbps—A Grade, B Grade, C Grade
Min
Typ
Max
19
100
19
100
19
100
19
100
19
100
25 Mbps—C Grade
Min
Typ
Max
64
89
68
87
71
85
75
83
78
81
Rev. 0 | Page 3 of 24
Unit
Test Conditions
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
No VISO load
No VISO load
No VISO load
No VISO load
No VISO load
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Table 4. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
55
Min
1
100
40
C Grade
Typ
Max
15
50
50
6
15
ns
ns
1000
tPSKCD
tPSKOD
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
5
PW
tPSK
Test Conditions
Mbps
ns
ns
ps/°C
ns
ns
45
25
60
6
Unit
40
Within PWD limit
Between any two units
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the
isolation barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
7
Table 5. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
Min
VIH
VIL
VOH
0.7 VISO or 0.7 VDD1
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysterisis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
0.1
0.4
V
V
V
V
V
V
+20
V
V
V
μA
0.3 VISO or 0.3 VDD1
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
5.0
4.8
0.0
0.2
Unit
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supply
0 V ≤ VIx ≤ VDDX
10% to 90%
VIx= VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. 0 | Page 4 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA
CBO = 0.1 μF||10 μF, IISO = 54 mA
5
60
33
14
175
IDD1 (Q)
IDD1 (MAX)
20
VISO > 3 V
IISO = 60 mA
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
ADuM6400
ADuM6401
ADuM6402
ADuM6403
ADuM6404
Symbol
2 Mbps—A Grade, B Grade, C Grade
Min
Typ
Max
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
14
60
14
60
14
60
14
60
14
60
25 Mbps—C Grade
Min
Typ
Max
41
43
44
42
46
41
47
39
51
38
Unit
Test Conditions
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
No VISO load
No VISO load
No VISO load
No VISO load
No VISO load
Table 8. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
60
Min
1
100
40
C Grade
Typ
Max
tPSKCD
tPSKOD
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
45
50
50
6
15
ns
ns
5
PW
tPSK
Test Conditions
Mbps
ns
ns
ps/°C
ns
ns
45
25
60
6
Unit
1000
40
1
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the
isolation barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
7
Rev. 0 | Page 5 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Table 9. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
Min
VIH
VIL
VOH
0.7 VISO or 0.7 VDD1
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysterisis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
Unit
0.1
0.4
V
V
V
V
V
V
+10
V
V
V
μA
0.3 VISO or 0.3 VDD1
VDD1 − 0.2 or VISO − 0.2
VDD1 − 0.5 or VISO − 0.5
3.3
3.1
0.0
0.0
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supply
0 V ≤ VIx ≤ VDDX
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for
a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the
entire recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise
noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
CBO = 0.1 μF||10 μF, IISO = 90 mA
IDD1 (Q)
IDD1 (MAX)
5
100
30
14
230
20
Rev. 0 | Page 6 of 24
VISO > 3 V
IISO = 90 mA
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
ADuM6400
ADuM6401
ADuM6402
ADuM6403
ADuM6404
2 Mbps—A Grade, B Grade, C Grade
Min
Typ
Max
Symbol
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
IDD1
IISO (LOAD)
25 Mbps—C Grade
Min
Typ
Max
9
100
9
100
9
100
9
100
9
100
43
93
44
92
45
91
46
89
47
88
Unit
Test Conditions
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
No VISO load
No VISO load
No VISO load
No VISO load
No VISO load
Table 12. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
1
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
Min
1
100
40
60
C Grade
Typ
Max
15
50
50
6
15
ns
ns
1000
40
tPSKCD
tPSKOD
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
5
PW
tPSK
Test Conditions
Mbps
ns
ns
ps/°C
ns
ns
45
25
60
6
Unit
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7
2
Table 13. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
Min
VIH
VIL
VOH
0.7 VISO or 0.7 VDD1
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysterisis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
0.3 VISO or 0.3 VDD1
VDD1 − 0.2, VISO − 0.2
VDD1 − 0.5 or
VISO − 0.5
VDD1 or VISO
VDD1 − 0.2 or
VISO − 0.2
0.0
0.0
Unit
Test Conditions
V
V
V
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
+10
V
V
V
μA
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supply
0 V ≤ VIx ≤ VDDx
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. 0 | Page 7 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
PACKAGE CHARACTERISTICS
Table 14. Thermal and Isolation Characteristics
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.2
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3
1
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together; and Pin 9 to Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
2
REGULATORY APPROVALS
Table 15.
UL (Pending) 1
Recognized under 1577 component
recognition program1
5000 V rms isolation voltage double
protection
File E214100
CSA
Approved under CSA Component
Acceptance Notice #5A
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 600 V rms (848 V peak)
maximum working voltage
Reinforced insulation per IEC 60601-1
250 V rms (353 V peak) maximum working
voltage
File 205078
VDE (Pending) 2
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 3
Reinforced insulation, 846 V peak
File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM640x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
In accordance with DIN EN 60747-5-2, each ADuM640x is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection
limit = 5 pC).
3
In accordance with DIN V VDE V 0884-10, each ADuM640x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
2
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
5000
L(I01)
7.6
Unit Test Conditions/Comments
V rms 1-minute duration
mm
Measured from input terminals to output terminals,
shortest distance through air
>8.0
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.017 min mm
Distance through insulation
>400
V
IEC 60112
II
Material group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
Rev. 0 | Page 8 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 17. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
846
1590
V peak
V peak
1375
1018
V peak
V peak
VTR
6000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 7)
Case Temperature
Side 1 IDD1 Current
Insulation Resistance at TS
VIO = 500 V
500
400
300
200
100
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
08141-007
SAFE OPERATING VDD1 CURRENT (mA)
600
Figure 7. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter
Operating Temperature 1
Supply Voltages 2
VDD1 @ VSEL = 0 V
VDD1 @ VSEL = VISO
Minimum Load
1
2
Symbol
TA
Min
−40
Max
+105
Unit
°C
VDD
VDD
IISO(MIN)
3.0
4.5
10
5.5
5.5
V
V
mA
Operation at 105°C requires reduction of the maximum load current as specified in Table 19.
Each voltage is relative to its respective ground.
Rev. 0 | Page 9 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 19.
Parameter
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages (VDD1, VISO) 1
Input Voltage
(VIA, VIB, VIC, VID, VSEL)1, 2
Output Voltage
(VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin 3
Common-Mode Transients 4
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−10 mA to +10 mA
−100 kV/μs to +100 kV/μs
1
Each voltage is relative to its respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the Printed Circuit Board (PCB) Layout section.
3
See Figure 7 for maximum rated current values for various temperatures.
4
. Common-mode transients exceeding the absolute maximum slew rate may
cause latch-up or permanent damage.
2
Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime 1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
424
Unit
V peak
Applicable Certification
All certifications, 50-year operation
600
560
V peak
V peak
Working voltage per IEC 60950-1
Working voltage per DIN V VDE V 0884-10
600
560
V peak
V peak
Working voltage per IEC 60950-1
Working voltage per DIN V VDE V 0884-10
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Rev. 0 | Page 10 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIC 5
ADuM6400
13 VOB
TOP VIEW
(Not to Scale) 12 VOC
VID 6
11
VOD
VDDL 7
10
VSEL
GND1 8
9
GNDISO
08141-008
VIB 4
Figure 8. ADuM6400 Pin Configuration
Table 21. ADuM6400 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VID
Logic Input D.
7
VDDL
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VOD
Logic Output D.
12
VOC
Logic Output C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. 0 | Page 11 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIC 5
ADuM6401
13 VOB
TOP VIEW
(Not to Scale) 12 VOC
VOD 6
11
VID
VDDL 7
10
VSEL
GND1 8
9
GNDISO
08141-009
VIB 4
Figure 9. ADuM6401 Pin Configuration
Table 22. ADuM6401 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VOD
Logic Output D.
7
VDDL
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VOC
Logic Output C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. 0 | Page 12 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VOC 5
ADuM6402
13 VOB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
VDDL 7
10
VSEL
GND1 8
9
GNDISO
08141-010
VIB 4
Figure 10. ADuM6402 Pin Configuration
Table 23. ADuM6402 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
VDDL
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. 0 | Page 13 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VOC 5
ADuM6403
13 VIB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
VDDL 7
10
VSEL
GND1 8
9
GNDISO
08141-011
VOB 4
Figure 11. ADuM6403 Pin Configuration
Table 24. ADuM6403 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VOB
Logic Output B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
VDDL
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VIB
Logic Input B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. 0 | Page 14 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VOA 3
14
VIA
VOC 5
ADuM6404
13 VIB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
VDDL 7
10
VSEL
GND1 8
9
GNDISO
08141-012
VOB 4
Figure 12. ADuM6404 Pin Configuration
Table 25. ADuM6404 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VOA
Logic Output A.
4
VOB
Logic Output B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
VDDL
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VIB
Logic Input B.
14
VIA
Logic Input A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
TRUTH TABLE
Table 26. Truth Table (Positive Logic)
VIx Input 1
High
Low
High
Low
High
Low
High
Low
1
VSEL Input
High
High
Low
Low
Low
Low
High
High
VDD1 State
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
VDD1 Input (V)
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
VISO State
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
VISO Output (V)
5.0
5.0
3.3
3.3
3.3
3.3
5.0
5.0
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Rev. 0 | Page 15 of 24
VOx Output1
High
Low
High
Low
High
Low
High
Low
Notes
Normal operation, data is high
Normal operation, data is low
Normal operation, data is high
Normal operation, data is low
Normal operation, data is high
Normal operation, data is low
Configuration not recommended
Configuration not recommended
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
0.40
4.0
0.35
3.5
0.30
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
0.25
0.20
0.15
4.0
3.5
POWER
1.0
1.0
0.10
POWER (W)
INPUT CURRENT (A)
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
IDD1
0
0.02
0.04
0.06
0.08
OUTPUT CURRENT (A)
0.10
0.12
0
3.0
08141-033
0
0.5
0.5
Figure 13. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
3.5
4.0
4.5
5.0
5.5
6.0
0
6.5
08141-036
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0.05
INPUT SUPPLY VOLTAGE (V)
Figure 16. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage
OUTPUT VOLTAGE
(500mV/DIV)
1.0
0.9
0.7
0.6
0.5
10% LOAD
0.3
0.2
0
0
0.02
0.04
0.06
0.08
0.10
0.12
IISO (A)
(100µs/DIV)
08141-034
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3V
VDD1 = 3.3V, VISO = 3.3V
08141-037
0.4
0.1
90% LOAD
DYNAMIC LOAD
POWER DISSIPATION (W)
0.8
Figure 14. Typical Total Power Dissipation vs. IISO with Data Channels Idle
Figure 17. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
OUTPUT VOLTAGE
(500mV/DIV)
0.12
0.08
0.04
0.02
0
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0
0.05
0.10
0.15
0.20
INPUT CURRENT (A)
0.25
0.30
0.35
Figure 15. Typical Isolated Output Supply Current, IISO, as a Function of
External Load, No Dynamic Current Draw at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V
Rev. 0 | Page 16 of 24
10% LOAD
90% LOAD
08141-038
DYNAMIC LOAD
0.06
08141-035
OUTPUT CURRENT (A)
0.10
(100µs/DIV)
Figure 18. Typical Transient Load Response, 3 V Output,
10% to 90% Load Step
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
20
5V OUTPUT RIPPLE (10mV/DIV)
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
SUPPLY CURRENT (mA)
16
12
8
0
BW = 20MHz (400ns/DIV)
Figure 19. Typical VISO = 5 V Output Voltage Ripple at 90% Load
0
5
10
15
DATA RATE (Mbps)
20
25
08141-042
08141-039
4
Figure 22. Typical ICHn Supply Current per Reverse Data Channel
(15 pF Output Load)
5
SUPPLY CURRENT (mA)
3.3V OUTPUT RIPPLE (10mV/DIV)
4
3
5V
2
3.3V
0
0
5
BW = 20MHz (400ns/DIV)
Figure 20. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
25
3.0
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
2.5
SUPPLY CURRENT (mA)
16
12
8
4
2.0
1.5
5V
1.0
3.3V
0
5
10
15
DATA RATE (Mbps)
20
25
08141-041
0.5
0
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 24. Typical IISO (D) Dynamic Supply Current per Output
(15 pF Output Load)
Figure 21. Typical ICHn Supply Current per Forward Data Channel
(15 pF Output Load)
Rev. 0 | Page 17 of 24
08141-044
SUPPLY CURRENT (mA)
20
Figure 23. Typical IISO (D) Dynamic Supply Current per Input
20
0
10
15
DATA RATE (Mbps)
08141-043
08141-040
1
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
TERMINOLOGY
IDD1 (Q)
IDD1(Q) is the minimum operating current drawn at the VDD1 pin
when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current. IDD1(Q) reflects the minimum current operating condition.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
tPHL Propagation Delay
tPHL propagation delay is measured from the 50% level of the
falling edge of the VIx signal to the 50% level of the falling edge
of the VOx signal.
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the rising
edge of the VIx signal to the 50% level of the rising edge of the
VOx signal.
tPSK Propagation Delay Skew
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
tPSKCD/tPSKOD Channel-to-Channel Matching
Channel-to-channel matching is the absolute value of the
difference in propagation delays between the two channels
when operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. 0 | Page 18 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
APPLICATIONS INFORMATION
BYPASS < 2mm
VDD1
The dc-to-dc converter section of the ADuM640x works on
principles that are common to most modern power supplies.
It is a secondary side controller architecture with isolated pulsewidth modulation (PWM) feedback. VDD1 power is supplied to an
oscillating circuit that switches current into a chip-scale air core
transformer. Power transferred to the secondary side is rectified
and regulated to either 3.3 V or 5 V. The secondary (VISO) side
controller regulates the output by creating a PWM control signal
that is sent to the primary (VDD1) side by a dedicated iCoupler
data channel. The PWM modulates the oscillator circuit to control
the power being sent to the secondary side. Feedback allows for
significantly higher power and efficiency.
The ADuM640x implement undervoltage lockout (UVLO) with
hysteresis on the VDD1 power input. This feature ensures that the
converter does not go into oscillation due to noisy input power or
slow power-on ramp rates.
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise
on chip due to short or erratic PWM pulses. Excess noise generated this way can cause data corruption, in some circumstances.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM640x digital isolators with 0.5 W isoPower integrated
dc-to-dc converters require no external interface circuitry for
the logic interfaces. Power supply bypassing is required at the
input and output supply pins (see Figure 25). Note that a low
ESR bypass capacitor is required between Pin 1 and Pin 2, as
close to the chip pads as possible.
The power supply section of the ADuM640x uses a 180 MHz
oscillator frequency to efficiently pass power through its chip
scale transformers. In addition, normal operation of the data
section of the iCoupler introduces switching transients on the
power supply pins. Bypass capacitors are required for several
operating frequencies. Noise suppression requires a low
inductance, high frequency capacitor; ripple suppression
and proper regulation require a large value capacitor. These are
most conveniently connected between Pin 1 and Pin 2 for VDD1
and between Pin 15 and Pin 16 for VISO. To suppress noise and
reduce ripple, a parallel combination of at least two capacitors
is required. The recommended capacitor values are 0.1 μF and
10 μF for VDD1. The smaller capacitor must have a low ESR; for
example, use of a ceramic capacitor is advised.
VISO
GND1
GNDISO
VIA/VOA
VIA/VOA
VIB/VOB
VIB/VOB
VIC/VOC
VIC/VOC
VID/VOD
VID/VOD
VDDL
GND1
VSEL
GNDISO
08141-025
THEORY OF OPERATION
Figure 25. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between pins,
exceeding the absolute maximum ratings specified in Table 19,
thereby leading to latch-up and/or permanent damage.
The ADuM640x are power devices that dissipate about 1 W
of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the devices primarily depend on heat dissipation into
the PCB through the GND pins. If the devices are used at high
ambient temperatures, provide a thermal path from the GND
pins to the PCB ground plane. The board layout in Figure 25
shows enlarged pads for Pin 8 and Pin 9. Large diameter vias
should be implemented from the pad to the ground, and power
planes should be used to reduce inductance. Multiple vias in the
thermal pads can significantly reduce temperatures inside the
chip. The dimensions of the expanded pads are left to the
discretion of the designer and the available board space.
THERMAL ANALYSIS
The ADuM640x parts consist of four internal die attached to a
split lead frame with two die attach paddles. For the purposes of
thermal analysis, the die is treated as a thermal unit, with the
highest junction temperature reflected in the θJA from Table 14.
The value of θJA is based on measurements taken with the parts
mounted on a JEDEC standard, 4-layer board with fine width
traces and still air. Under normal operating conditions, the
ADuM640x devices operate at full load across the full temperature
range without derating the output current. However, following
the recommendations in the Printed Circuit Board (PCB) Layout
section decreases thermal resistance to the PCB, allowing
increased thermal margins in high ambient temperatures.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. A bypass between Pin 1 and
Pin 8 and between Pin 9 and Pin 16 should also be considered
unless both common ground pins are connected together
close to the package.
Rev. 0 | Page 19 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 26).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
50%
OUTPUT (VOx)
tPHL
08141-026
tPLH
50%
Figure 26. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM640x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM640x
components operating under the same conditions.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM640x, and
an imposed requirement that the induced voltage be, at most, 50%
of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 27.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM640x components
must, of necessity, operate at a very high frequency to allow
efficient power transfer through the small transformers.
This creates high frequency currents that can propagate in
circuit board ground and power planes, causing edge and
dipole radiation. Grounded enclosures are recommended for
applications that use these devices. If grounded enclosures are
not possible, follow good RF design practices in layout of the
PCB. See www.analog.com for the most current PCB layout
recommendations specifically for the ADuM640x.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
1
0.1
0.01
0.001
1k
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 μs, periodic sets of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than approximately 5 μs, the input side
is assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default high state by the watchdog
timer circuit. This situation should only occur in the ADuM640x
devices during power-up and power-down operations.
10
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
08141-027
INPUT (VIx)
The limitation on the ADuM640x magnetic field immunity is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3.3 V operating condition of the
ADuM640x is examined because it represents the most susceptible
mode of operation.
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing
threshold of the decoder.
Rev. 0 | Page 20 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
The preceding magnetic flux density values correspond
to specific current magnitudes at given distances from the
ADuM640x transformers. Figure 28 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 28, the ADuM640x are extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For
the 1 MHz example, a 0.5 kA current placed 5 mm away from
the ADuM640x is required to affect component operation.
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of fr. The dynamic current
of each channel is determined by its data rate. Figure 21 shows the
current for a channel in the forward direction, meaning that the
input is on the VDD1 side of the part. Figure 22 shows the current
for a channel in the reverse direction, meaning that the input is on
the VISO side of the part. Both figures assume a typical 15 pF load.
The following relationship allows the total IDD1 current to be
calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4
DISTANCE = 1m
(1)
where:
IDD1 is the total supply input current.
ICHn is the current drawn by a single channel determined from
Figure 21 or Figure 22, depending on channel direction.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at 100 mA load from Figure 13
at the VISO and VDD1 condition of interest.
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
0.1
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
08141-028
MAXIMUM ALLOWABLE CURRENT (kA)
1k
Figure 28. Maximum Allowable Current for
Various Current-to-ADuM640x Spacings
Note that, in combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler
data channels, as well as to the power converter. For this reason,
the quiescent currents drawn by the data converter and the
primary and secondary I/O channels cannot be determined
separately. All of these quiescent power demands have been
combined into the IDD1 (Q) current, as shown in Figure 29. The
total IDD1 supply current is equal to the sum of the quiescent
operating current; the dynamic current, IDD1 (D), demanded by
the I/O channels; and any external IISO load.
IDD1(Q)
IDD1(D)
IISO
E
CONVERTER
PRIMARY
IDDP(D)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 23 and Figure 24.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
The ADuM640x power input, data input channels on the
primary side, and data channels on the secondary side are all
protected from premature operation by UVLO circuitry. Below
the minimum operating voltage, the power converter holds its
oscillator inactive and all input channel drivers and refresh
circuits are idle. Outputs remain in a high impedance state to
prevent transmission of undefined states during power-up and
power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
CONVERTER
SECONDARY
IISO(D)
SECONDARY
DATA
INPUT/OUTPUT
4-CHANNEL
08141-029
PRIMARY
DATA
INPUT/OUTPUT
4-CHANNEL
(2)
Figure 29. Power Consumption Within the ADuM640x
Rev. 0 | Page 21 of 24
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
The insulation lifetime of the ADuM640x depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30,
Figure 31, and Figure 32 illustrate these different isolation
voltage waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines
the Analog Devices recommended maximum working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided the voltage conforms to
either the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 31 or Figure 32
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed
in Table 20.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care with the design to allow the
converter sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs
and the outputs are set to their default low value before the
secondary power reaches UVLO.
RATED PEAK VOLTAGE
08141-030
As the secondary side converter begins to accept power from
the primary, the VISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized to
their default low state until data is received from the corresponding
primary side input. It can take up to 1 μs after the secondary side is
initialized for the state of the output to correlate with the primary
side input.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest.
The values shown in Table 20 summarize the peak voltages for
50 years of service life in several operating conditions. In many
cases, the working voltage approved by agency testing is higher
than the 50-year service life voltage. Operation at working
voltages higher than the service life voltage listed leads to
premature insulation failure.
0V
Figure 30. Bipolar AC Waveform
RATED PEAK VOLTAGE
08141-031
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary power
is established. The primary side oscillator also begins to operate,
transferring power to the secondary power circuits. The secondary
VISO voltage is below its UVLO limit at this point; the regulation
control signal from the secondary is not being generated. The
primary side power oscillator is allowed to free run in this
circumstance, supplying the maximum amount of power to
the secondary, until the secondary voltage rises to its regulation
setpoint. This creates a large inrush current transient at VDD1.
When the regulation point is reached, the regulation control
circuit produces the regulation control signal that modulates
the oscillator on the primary side. The VDD1 current is reduced
and is then proportional to the load current. The inrush current
is less than the short-circuit current shown in Figure 16. The
duration of the inrush depends on the VISO loading conditions
and the current available at the VDD1 pin.
0V
Figure 31. DC Waveform
RATED PEAK VOLTAGE
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. Analog Devices
conducts an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM640x.
Rev. 0 | Page 22 of 24
NOTES
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE
VOLTAGE CANNOT CROSS 0V.
Figure 32. Unipolar AC Waveform
08141-032
0V
INSULATION LIFETIME
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADuM6400ARWZ1, 2
ADuM6400CRWZ1, 2
ADuM6401ARWZ1, 2
ADuM6401CRWZ1, 2
ADuM6402ARWZ1, 2
ADuM6402CRWZ1, 2
ADuM6403ARWZ1, 2
ADuM6403CRWZ1, 2
ADuM6404ARWZ1, 2
ADuM6404CRWZ1, 2
1
2
Number
of Inputs,
VDD1 Side
4
4
3
3
2
2
1
1
0
0
Number
of Inputs,
VISO Side
0
0
1
1
2
2
3
3
4
4
Maximum
Data Rate
(Mbps)
1
25
1
25
1
25
1
25
1
25
Maximum
Propagation
Delay, 5 V (ns)
100
60
100
60
100
60
100
60
100
60
Maximum
Pulse Width
Distortion (ns)
40
6
40
6
40
6
40
6
40
6
Tape and reel are available. The addition of an RL suffix designates a 13-inch (1,000 units) tape and reel option.
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
Temperature
Range (°C)
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Package
Option
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08141-0-5/09(0)
Rev. 0 | Page 24 of 24
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