Revised March 2005 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear (CLR) are common to all flip-flops. ■ Input and output interface capability to systems at 5V VCC The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop’s output. ■ Outputs source/sink 32 mA/64 mA The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Functionally compatible with the 74 series 273 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Package Description Number 74LVTH273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH273MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500100 www.fairchildsemi.com 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear July 1999 74LVTH273 Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input CLR Clear O0–O7 Outputs Truth Table Inputs On H H H L X H or L H Oo X X L L H L CP Outputs CLR Dn H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition Oo Previous Oo before HIGH-to-LOW of CP Functional Description The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions Units V V Output in HIGH or LOW State (Note 3) V VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V HIGH Level Output Current 32 mA LOW Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Units 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter TA 40qC to 85qC Min Typ Max Units Conditions 1.2 V II V VO d 0.1V or (Note 4) VIK Input Clamp Diode Voltage VIH Input HIGH Voltage VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 2.7–3.6 Output LOW Voltage Bushold Input Minimum Drive 2.0 0.8 V Data Pins 100 PA IOL 24 mA IOL 16 mA 32 mA 0.5 0.4 3.0 0.5 IOL 3.0 0.55 IOL 75 V PA 500 PA 500 Control Pins 32 mA IOL 3.0 3.0 Input Current 8 mA IOH 2.7 Current to Change State II 100 PA IOH 0.2 3.0 Bushold Input Over-Drive VO t VCC 0.1V IOH 2.7 75 II(OD) V 18 mA 64 mA VI 0.8V VI 2.0V (Note 5) (Note 6) 3.6 10 PA VI 5.5V 3.6 r1 PA VI 0V or VCC 5 PA VI 0V 1 PA VI VCC 0 r100 PA 0V d VI or VO d 5.5V 3.6 IOFF Power Off Leakage Current ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW Increase in Power Supply Current 3.6 0.2 mA One Input at VCC 0.6V 'ICC (Note 7) Note 4: All typical values are at VCC Other Inputs at VCC or GND 3.3V, TA 25qC. 3 www.fairchildsemi.com 74LVTH273 Absolute Maximum Ratings(Note 2) 74LVTH273 DC Electrical Characteristics (Continued) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol VCC (V) Parameter (Note 8) 25qC TA Min Typ Conditions Units Max CL 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 9) 500: Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA CL Symbol Parameter VCC Min 40qC to 85qC 50 pF, RL 3.3V r 0.3V Typ 500: VCC Max Min 2.7V Units Max (Note 10) fMAX Maximum Clock Frequency 150 tPLH Propagation Delay 1.7 4.9 1.7 5.5 tPHL CP to On 1.9 4.8 1.9 5.1 tPHL Propagation Delay CLR to On 1.6 4.8 1.6 5.4 tW Pulse Duration 3.3 3.3 tS Setup Time Data HIGH or LOW before CP 2.3 2.7 CLR HIGH before CP 2.3 2.7 0 0 tH Hold Time Data HIGH or LOW after CP Note 10: All typical values are at VCC Capacitance Symbol 3.3V, TA MHz ns ns ns ns ns 25qC. (Note 11) Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 11: Capacitance is measured at frequency f www.fairchildsemi.com 150 0V or VCC 0V or VCC 1 MHz, per MIL-STD-883B, Method 3012. 4 Typical Units 3 pF 6 pF 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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