Revised March 2005 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs General Description Features The LCX573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. ■ 5V tolerant inputs and outputs The LCX573 is functionally identical to the LCX373 but has inputs and outputs on opposite sides. The LCX573 is designed for low voltage (3.3V or 2.5V) applications with capability of interfacing to a 5V signal environment. The LCX573 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V–3.6V VCC specifications provided ■ 7.0 ns tPD max (VCC 3.3V), 10 PA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ r24 mA output drive (VCC 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance: Human body model ! 2000V Machine model ! 200V ■ Leadless Pb-Free DQFN package Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Package Description Number 74LCX573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX573BQX (Preliminary) (Note 2) MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 74LCX573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LCX573MTCX_NL (Note 3) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 2: DQFN package available in Tape and Reel only. Note 3: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS012405 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs March 1995 74LCX573 Logic Symbol Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs Connection Diagrams Truth Table Pin Assignments for SOIC, SOP, SSOP, TSSOP Inputs H L Z X O0 Pad Assignments for DQFN Outputs OE LE D On L H H H L H L L L L X O0 H X X Z HIGH Voltage LOW Voltage High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LCX573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. (Top View) Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150 Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI GND V mA VO GND mA VO ! VCC mA mA mA qC Recommended Operating Conditions (Note 6) Symbol VCC Parameter VI Input Voltage VO Output Voltage IOH/IOL Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 Supply Voltage Output Current TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V 2.0V, VCC 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC 3.0V 3.6V VCC 2.7V 3.0V VCC 2.3V 2.7V 3.0V r24 r12 r8 Units V V V mA 40 85 qC 0 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage 40qC to 85qC Min 2.3 2.7 1.7 2.7 3.6 2.0 Max 0.7 2.7 3.6 0.8 100 PA 2.3 3.6 VCC 0.2 8 mA 2.3 1.8 IOH 12 mA 2.7 2.2 IOH 18 mA 3.0 2.4 2.2 24 mA 3.0 IOL 100 PA 2.3 3.6 IOL 8 mA 2.3 0.6 IOL 12 mA 2.7 0.4 IOL 16 mA 3.0 0.4 IOL 24 mA IOZ 3-STATE Output Leakage 0 d VO d 5.5V VI V IH or VIL VI or VO 5.5V 3 V V IOH 0 d VI d 5.5V Units V 2.3 2.7 IOH Input Leakage Current Power-Off Leakage Current TA (V) IOH II IOFF VCC 0.2 V 3.0 0.55 2.3 3.6 r5.0 PA 2.3 3.6 r5.0 PA 0 10 PA www.fairchildsemi.com 74LCX573 Absolute Maximum Ratings(Note 4) 74LCX573 DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions (V) Quiescent Supply Current ICC VI VCC or GND 3.6V d VI, VO d 5.5V (Note 7) 'ICC Increase in ICC per Input VIH VCC 0.6V 40qC to 85qC TA Min Units Max 2.3 3.6 10 2.3 3.6 r10 2.3 3.6 500 PA PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA Symbol VCC Parameter 40qC to 85qC, RL 3.3V r 0.3V CL 50pF VCC 2.7V CL 50pF 500 : VCC 2.5 r 0.2V CL 30pF Min Max Min Max Min Max tPHL Propagation Delay 1.5 8.0 1.5 9.0 1.5 9.6 tPLH Dn to On 1.5 8.0 1.5 9.0 1.5 9.6 tPHL Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5 tPLH LE to On 1.5 8.5 1.5 9.5 1.5 10.5 tPZL Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 1.5 8.5 1.5 9.5 1.5 10.5 tPZH tPLZ Output Disable Time tPHZ 1.5 6.5 1.5 7.0 1.5 7.8 1.5 6.5 1.5 7.0 1.5 7.8 Units ns ns ns ns tS Setup Time, Dn to LE 2.5 2.5 4.0 ns tH Hold Time, Dn to LE 1.5 1.5 2.0 ns tW LE Pulse Width 3.3 3.3 4.0 ns tOSHL Output to Output Skew (Note 8) 1.0 tOSLH ns 1.0 Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL VCC Conditions 25qC TA (V) Typical CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 Units V V Capacitance Symbol Parameter Conditions Typical Units 0V or VCC 7 pF CIN Input Capacitance VCC Open, VI COUT Output Capacitance VCC 3.3V, VI 0V or VCC CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f www.fairchildsemi.com 4 10 MHz 8 pF 25 pF 74LCX573 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.15V Vy VOH 0.3V VOH 0.3V VOH 0.15V 5 www.fairchildsemi.com 74LCX573 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 Tape Format for DQFN Package Designator BQX Tape Number Cavity Section Cavities Status Cover Tape Status Leader (Start End) 125 (typ) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) REEL DIMENSIONS inches (millimeters) Tape Size 12 mm A B C D N W1 W2 13.0 0.059 0.512 0.795 2.165 0.488 0.724 (330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4) 7 www.fairchildsemi.com 74LCX573 Tape and Reel Specification 74LCX573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 8 74LCX573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 9 www.fairchildsemi.com 74LCX573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B www.fairchildsemi.com 10 74LCX573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 11 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 12