® ispLSI 2128VE 3.3V In-System Programmable SuperFAST™ High Density PLD Functional Block Diagram* • 3.3V LOW VOLTAGE 2128 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 250MHz Maximum Operating Frequency — tpd = 4.0ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power Output Routing Pool (ORP) Output Routing Pool (ORP) D7 D3 D5 D4 D1 D0 A0 C7 A1 C6 A2 A3 Logic Array A4 D Q D Q D Q D Q C5 C4 GLB A5 C3 C2 A6 C1 Global Routing Pool (GRP) A7 B0 B1 B2 B3 Output Routing Pool (ORP) *128 I/O Version Shown • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping D2 B4 B5 C0 B6 B7 Output Routing Pool (ORP) D6 Output Routing Pool (ORP) Output Routing Pool (ORP) Output Routing Pool (ORP) • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2128V Devices CLK 0 CLK 1 CLK 2 Features Output Routing Pool (ORP) 0139A/2128VE Description The ispLSI 2128VE is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2128VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity The basic unit of logic on the ispLSI 2128VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 2128ve_08 1 September 2000 Specifications ispLSI 2128VE Functional Block Diagram RESET Output Routing Pool (ORP) IN 5 IN 4 D0 D1 I/O 87 I/O 86 I/O 85 I/O 84 A2 C4 Global Routing Pool (GRP) Input Bus C3 A4 C2 A5 C1 B0 B1 B2 B3 B5 B4 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 8 I/O 9 I/O 10 I/O 11 I/O 67 I/O 66 I/O 65 I/O 64 Output Routing Pool (ORP) Output Routing Pool (ORP) IN 7* IN 6* IN 5* IN 4* D0 D1 I/O 47 I/O 46 I/O 45 I/O 44 C6 I/O 43 I/O 42 I/O 41 I/O 40 A2 C4 Global Routing Pool (GRP) A3 C3 A4 C2 C1 I/O 35 I/O 34 I/O 33 I/O 32 C0 I/O 12 I/O 13 I/O 14 I/O 15 I/O 39 I/O 38 I/O 37 I/O 36 A5 A6 A7 TDI/IN 0 TMS/IN 1 B7 B6 D2 D3 C5 A7 TDI/IN 0 TMS/IN 1 D4 A1 I/O 71 I/O 70 I/O 69 I/O 68 C0 D5 A0 I/O 4 I/O 5 I/O 6 I/O 7 I/O 75 I/O 74 I/O 73 I/O 72 A6 D6 B0 B1 B2 B3 B5 B4 B6 B7 Output Routing Pool (ORP) Input Bus Input Bus BSCAN The 128-I/O 2128VE contains 128 I/O cells, while the 64I/O version contains 64 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. Y0 Y1 Y2 I/O 28 I/O 29 I/O 30 I/O 31 I/O 20 I/O 21 I/O 22 I/O 23 0139B/2128VE I/O 16 I/O 17 I/O 18 I/O 19 TDO/IN 2 TCK/IN 3 Y0 Y1 Y2 I/O 60 I/O 61 I/O 62 I/O 63 I/O 56 I/O 57 I/O 58 I/O 59 I/O 52 I/O 53 I/O 54 I/O 55 I/O 48 I/O 49 I/O 50 I/O 51 I/O 44 I/O 45 I/O 46 I/O 47 I/O 40 I/O 41 I/O 42 I/O 43 I/O 36 I/O 37 I/O 38 I/O 39 I/O 32 I/O 33 I/O 34 I/O 35 TDO/IN 2 TCK/IN 3 BSCAN I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 C5 A3 Output Routing Pool (ORP) I/O 24 I/O 25 I/O 26 I/O 27 A1 Input Bus I/O 8 I/O 9 I/O 10 I/O 11 I/O 0 I/O 1 I/O 2 I/O 3 CLK 0 CLK 1 CLK 2 I/O 4 I/O 5 I/O 6 I/O 7 D7 C7 I/O 91 I/O 90 I/O 89 I/O 88 Output Routing Pool (ORP) Output Routing Pool (ORP) C6 Output Routing Pool (ORP) A0 Generic Logic Blocks (GLBs) I/O 95 I/O 94 I/O 93 I/O 92 Input Bus D2 D3 Output Routing Pool (ORP) D4 CLK 0 CLK 1 CLK 2 D5 Input Bus D6 Output Routing Pool (ORP) D7 C7 I/O 20 I/O 21 I/O 22 I/O 23 I/O 51 I/O 50 I/O 49 I/O 48 Output Routing Pool (ORP) Megablock Generic Logic Blocks (GLBs) I/O 0 I/O 1 I/O 2 I/O 3 Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Megablock I/O 16 I/O 17 I/O 18 I/O 19 I/O 55 I/O 54 I/O 53 I/O 52 RESET Input Bus GOE 0 GOE 1 I/O 12 I/O 13 I/O 14 I/O 15 I/O 59 I/O 58 I/O 57 I/O 56 I/O 63 I/O 62 I/O 61 I/O 60 IN 7 IN 6 I/O 99 I/O 98 I/O 97 I/O 96 I/O 103 I/O 102 I/O 101 I/O 100 I/O 107 I/O 106 I/O 105 I/O 104 I/O 111 I/O 110 I/O 109 I/O 108 I/O 115 I/O 114 I/O 113 I/O 112 I/O 119 I/O 118 I/O 117 I/O 116 I/O 123 I/O 122 I/O 121 I/O 120 I/O 127 I/O 126 I/O 125 I/O 124 Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions) 0139B/2128VE.64IO *Not available on 84-PLCC Device Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools. Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 or 16 universal I/O cells by the two or one ORPs. Each ispLSI 2128VE device contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, 2 Specifications ispLSI 2128VE Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER VCC Supply Voltage VIL VIH Input Low Voltage Commercial TA = 0°C to + 70°C Industrial TA = -40°C to + 85°C MIN. MAX. UNITS 3.0 3.6 V 3.0 3.6 V 0.8 V 5.25 V VSS – 0.5 Input High Voltage 2.0 Table 2-0005/2128VE Capacitance (TA=25°C, f=1.0 MHz) TYPICAL UNITS Dedicated Input Capacitance 8 pf VCC = 3.3V, VIN = 0.0V I/O Capacitance 6 pf VCC = 3.3V, VI/O = 0.0V Clock and Global Output Enable Capacitance 10 pf VCC = 3.3V, VY = 0.0V SYMBOL C1 C2 C3 PARAMETER TEST CONDITIONS Table 2-0006/2128VE Erase Reprogram Specifications PARAMETER MINIMUM MAXIMUM UNITS 10,000 – Cycles Erase/Reprogram Cycles Table 2-0008/2128VE 3 Specifications ispLSI 2128VE Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V ≤ 1.5ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 3.3V R1 See Figure 2 Device Output 3-state levels are measured 0.5V from steady-state active level. Test Point Table 2 - 0003/2128VE R2 CL* Output Load Conditions (see Figure 2) TEST CONDITION A B C R1 R2 CL 316Ω 348Ω 35pF Active High ∞ 348Ω 35pF Active Low 316Ω 348Ω 35pF Active High to Z at VOH -0.5V ∞ 348Ω 5pF Active Low to Z at VOL +0.5V 316Ω 348Ω 5pF *CL includes Test Fixture and Probe Capacitance. 0213A/2128VE Table 2-0004/2128VE DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION 3 MIN. TYP. MAX. UNITS VOL VOH IIL Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA IIH Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC – – 10 µA VCC ≤ VIN ≤ 5.25V – – 10 µA IIL-isp IIL-PU IOS1 BSCAN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 3.3V, VOUT = 0.5V – – -100 mA ICC2, 4 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V – 195 – mA fCLOCK = 1 MHz Table 2-0007/2128VE 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 4 Specifications ispLSI 2128VE External Timing Parameters Over Recommended Operating Conditions 3 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl TEST COND. # DESCRIPTION -250 1 -180 MIN. MAX. MIN. MAX. UNITS A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 4.0 — 5.0 ns A 2 Data Propagation Delay — 6.0 — 7.5 ns A 3 Clock Frequency with Internal Feedback 2 — 4 Clock Frequency with External Feedback ( tsu2 + tco1) — 5 250 — 180 — MHz 158.7 — 125 — MHz Clock Frequency, Max. Toggle 275 — 200 — MHz 1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 — 3.5 — ns A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 3.0 — 3.5 ns — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — ns — 9 GLB Reg. Setup Time before Clock 3.3 — 4.5 — ns A 10 GLB Reg. Clock to Output Delay — 3.7 — 4.5 ns 0.0 — 0.0 — ns — 6.0 — 7.0 ns — 11 GLB Reg. Hold Time after Clock A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 13 Ext. Reset Pulse Duration 3.5 — 4.0 — ns B 14 Input to Output Enable — 6.0 — 10.0 ns C 15 Input to Output Disable — 6.0 — 10.0 ns B 16 Global OE Output Enable — 4.0 — 5.0 ns C 17 Global OE Output Disable — 4.0 — 5.0 ns — 18 External Synchronous Clock Pulse Duration, High 1.8 — 2.5 — ns — 19 External Synchronous Clock Pulse Duration, Low 1.8 — 2.5 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 5 Table 2-0030A/2128VE v.1.0 Specifications ispLSI 2128VE External Timing Parameters Over Recommended Operating Conditions 3 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl -135 TEST COND. # A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback — 4 — — DESCRIPTION 1 -100 MIN. MAX. MIN. MAX. — 7.5 — 10.0 UNITS ns — 10.0 — 13.0 ns 135 — 100 — MHz Clock Frequency with External Feedback ( tsu2 + tco1) 100 — 77 — MHz 5 Clock Frequency, Max. Toggle 143 — 100 — MHz 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.0 — 6.5 — ns 2 1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 4.0 — 5.0 ns — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — ns — 9 GLB Reg. Setup Time before Clock 6.0 — 8.0 — ns A 10 GLB Reg. Clock to Output Delay — 5.0 — 6.0 ns — 11 GLB Reg. Hold Time after Clock 0.0 — 0.0 — ns A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 13 Ext. Reset Pulse Duration — 9.0 — 12.5 ns 5.0 — 6.5 — ns B 14 Input to Output Enable — 12.0 — 15.0 ns C 15 Input to Output Disable — 12.0 — 15.0 ns B 16 Global OE Output Enable — 7.0 — 9.0 ns C 17 Global OE Output Disable — 7.0 — 9.0 ns — 18 External Synchronous Clock Pulse Duration, High 3.5 — 5.0 — ns — 19 External Synchronous Clock Pulse Duration, Low 3.5 — 5.0 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 6 Table 2-0030B/2128VE v.1.0 Specifications ispLSI 2128VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 DESCRIPTION -180 -250 MIN. MAX. MIN. MAX. UNITS Inputs tio tdin 20 Input Buffer Delay — 0.5 — 0.5 ns 21 Dedicated Input Delay — 0.7 — 1.1 ns 22 GRP Delay — 0.2 — 0.6 ns 23 4 Product Term Bypass Path Delay (Combinatorial) — 1.5 — 1.9 ns 24 4 Product Term Bypass Path Delay (Registered) — 2.0 — 2.4 ns 25 1 Product Term/XOR Path Delay — 2.8 — 3.4 ns 26 20 Product Term/XOR Path Delay — 2.8 — 3.4 ns 27 XOR Adjacent Path Delay 3 — 2.8 — 3.4 ns 28 GLB Register Bypass Delay — 0.0 — 0.0 ns 29 GLB Register Setup Time before Clock 0.8 — 1.2 — ns 30 GLB Register Hold Time after Clock 1.7 — 2.3 — ns 31 GLB Register Clock to Output Delay — 0.2 — 0.3 ns 32 GLB Register Reset to Output Delay — 0.3 — 0.6 ns 33 GLB Product Term Reset to Register Delay — 3.7 — 4.3 ns 34 GLB Product Term Output Enable to I/O Cell Delay — 2.9 — 5.9 ns 0.8 3.6 1.0 4.0 ns 36 ORP Delay — 1.1 — 1.4 ns 37 ORP Bypass Delay — 0.4 — 0.4 ns 38 Output Buffer Delay — 1.4 — 1.6 ns 39 Output Slew Limited Delay Adder — 2.0 — 2.0 ns 40 I/O Cell OE to Output Enabled — 2.4 — 3.0 ns 41 I/O Cell OE to Output Disabled — 2.4 — 3.0 ns 42 Global Output Enable — 1.6 — 2.0 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.0 1.0 1.2 1.2 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.2 1.2 1.4 1.4 ns — 3.9 — 4.4 ns GRP tgrp GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 35 GLB Product Term Clock Delay ORP torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036A/2128VE v.1.0 Specifications ispLSI 2128VE Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER #2 DESCRIPTION -135 -100 MIN. MAX. MIN. MAX. UNITS Inputs tio tdin 20 Input Buffer Delay — 0.5 — 0.7 ns 21 Dedicated Input Delay — 1.7 — 2.5 ns 22 GRP Delay — 1.2 — 1.8 ns 23 4 Product Term Bypass Path Delay (Combinatorial) — 3.7 — 5.2 ns GRP tgrp GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 24 4 Product Term Bypass Path Delay (Registered) — 3.7 — 4.7 ns 25 1 Product Term/XOR Path Delay — 4.7 — 6.2 ns 26 20 Product Term/XOR Path Delay — 4.7 — 6.2 ns — 4.7 — 6.2 ns 27 XOR Adjacent Path Delay 3 — 0.5 — 1.0 ns 29 GLB Register Setup Time before Clock 1.2 — 1.7 — ns 30 GLB Register Hold Time after Clock 3.8 — 4.8 — ns 31 GLB Register Clock to Output Delay — 0.3 — 0.3 ns 32 GLB Register Reset to Output Delay — 1.1 — 3.1 ns 33 GLB Product Term Reset to Register Delay — 6.1 — 7.1 ns 34 GLB Product Term Output Enable to I/O Cell Delay — 6.9 — 9.1 ns 1.6 4.6 2.6 5.6 ns 36 ORP Delay — 1.5 — 1.7 ns 37 ORP Bypass Delay — 0.5 — 0.7 ns 38 Output Buffer Delay — 1.6 — 1.6 ns 39 Output Slew Limited Delay Adder — 2.0 — 2.0 ns 40 I/O Cell OE to Output Enabled — 3.4 — 3.4 ns 41 I/O Cell OE to Output Disabled — 3.4 — 3.4 ns 42 Global Output Enable — 3.6 — 5.6 ns 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.6 1.6 2.4 2.4 ns 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.8 1.8 2.6 2.6 ns — 5.8 — 7.1 ns 28 GLB Register Bypass Delay 35 GLB Product Term Clock Delay ORP torp torpbp Outputs tob tsl toen todis tgoe Clocks tgy0 tgy1/2 Global Reset tgr 45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 8 Table 2-0036B/2128VE v.1.0 Specifications ispLSI 2128VE ispLSI 2128VE Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Comb 4 PT Bypass #23 #21 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 20 PT XOR Delays GLB Reg Delay ORP Delay #25, 26, 27 D Q #38, 39 #36 RST Reset #45 #29, 30, 31, 32 Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #40, 41 #43, 44 #42 0491/2032 Derivations of tsu, th and tco from the Product Term Clock tsu = = = 2.8ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8) th = = = 2.5ns = Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8) tco = = = 7.0ns = Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4) Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L. Table 2-0042/2128VE v.1.0 9 I/O Pin (Output) Specifications ispLSI 2128VE Power Consumption used. Figure 3 shows the relationship between power and operating speed. Power consumption in the ispLSI 2128VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 350 ispLSI 2128VE 300 ICC (mA) 250 200 150 100 0 50 100 150 fmax (MHz) 200 250 Notes: Configuration of eight 16-bit counters Typical current at 3.3V, 25¡ C ICC can be estimated for the ispLSI 2128VE using the following equation: ICC = 8 + (# of PTs * 0.669) + (# of nets * max freq * 0.0026) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/2128VE 10 Specifications ispLSI 2128VE Signal Descriptions Signal Name Description RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in the device. BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. TCK/IN 3 Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TMS/IN 1 Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TDO/IN 2 Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. IN 4 - IN 7 Dedicated Input Pins to the device. GND Ground (GND) VCC Vcc NC1 No Connect I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array. 1. NC pins are not to be connected to any active signals, VCC or GND. 11 Specifications ispLSI 2128VE Signal Locations 208-Ball fpBGA Signal 176-Pin TQFP 160-Pin PQFP 100-Ball caBGA 100-Pin TQFP RESET H3 21 19 D2 11 GOE 0, GOE 1 J16, H1 110, 23 100, 21 F9, E1 62, 13 Y0, Y1, Y2 H2, H14, J14 20, 113, 108 18, 103, 98 E3, F6, F8 10, 65, 60 BSCAN J1 25 23 E5 15 TDI/IN 0 J3 26 24 F2 16 TCK/IN 3 J15 107 97 G10 59 TMS/IN 1 P8 66 60 J5 37 TDO/IN 2 IN 4 - IN 7 C9 H16, A9, T8, H4 D4, D13, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, N4, N13 D5, D6, D12, E4, E13, F4, F13, L4, L13, M4, M13, N5, N11, N12 A2, A3, A15, A16, B1, B2, B3, B14, B15, B16, C2, C3, C14, C15, D14, P1, P2, P3, P13, P14, P15, R1, R2, R3, R14, R15, R16, T1, T2, T15, T16 154 114, 155, 67, 19 24, 46, 68, 87, 109, 134, 153, 175 140 104, 141, 61, 17 22, 42, 62, 79, 99, 122, 139, 159 B6 E9, A6, K5, D1 87 66, 88, 38, 9 B7, F1, G9, K6 14, 39, 61, 86 2, 22, 43, 65, 90, 111, 131, 156 2, 20, 39, 59, 82, 101, 119, 142 A5, E2, F10, J4 12, 36, 63, 89 9, 18, 27, 36, 55, 64, 69, 78, 97, 106, 112, 115, 124, 143, 152, 157, 166 102 A8, C3, C4, D6, D8, E7, E10, F4, G3, G5, H7, H8, K3 GND VCC NC1 1. NC pins are not to be connected to any active signals, VCC or GND. 12 4, 21, 25, 31, 44, 50, 54, 64, 71, 75, 81, 94, 100 Specifications ispLSI 2128VE I/O Locations Signal 208 fpBGA 176 TQFP 160 PQFP 100 caBGA 100 TQFP Signal 208 fpBGA 176 TQFP 160 PQFP 100 caBGA 100 TQFP I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 J2 J4 K1 K3 K2 K4 L1 L2 L3 M1 M2 M3 N1 N2 N3 P4 T3 R4 T4 P5 R5 N6 T5 R6 P6 T6 N7 R7 P7 T7 N8 R8 T9 P9 R9 N9 T10 P10 R10 N10 T11 P11 R11 T12 P12 R12 T13 R13 T14 N14 P16 N15 N16 M14 M15 M16 L15 L14 L16 K13 K15 K14 K16 J13 28 29 30 31 32 33 34 35 37 38 39 40 41 42 44 45 47 48 49 50 51 52 53 54 56 57 58 59 60 61 62 63 70 71 72 73 74 75 76 77 79 80 81 82 83 84 85 86 88 89 91 92 93 94 95 96 98 99 100 101 102 103 104 105 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 83 84 85 86 87 88 89 90 91 92 93 94 95 96 G1 F3 E4 H1 G2 J1 H2 K1 J2 K2 H3 J3 G4 H4 K4 H5 F5 J6 K7 H6 K8 G6 J7 K9 J8 K10 J9 J10 H9 H10 G7 G8 D10 E8 F7 C10 D9 B10 C9 A10 B9 A9 C8 B8 D7 C7 A7 C6 E6 B5 A4 C5 A3 D5 B4 A2 B3 A1 B2 B1 C2 C1 D4 D3 17 18 19 20 22 23 24 26 27 28 29 30 32 33 34 35 40 41 42 43 45 46 47 48 49 51 52 53 55 56 57 58 67 68 69 70 72 73 74 76 77 78 79 80 82 83 84 85 90 91 92 93 95 96 97 98 99 1 2 3 5 6 7 8 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 H15 H13 G16 G14 G15 G13 F16 F14 F15 E16 E14 E15 D16 C16 D15 A14 C13 B13 A13 C12 B12 D11 A12 C11 B11 D10 A11 B10 C10 D9 A10 B9 A8 C8 B8 D8 A7 C7 B7 D7 A6 C6 B6 A5 C5 B5 A4 B4 C4 A1 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G2 G3 G1 116 117 118 119 120 121 122 123 125 126 127 128 129 130 132 133 135 136 137 138 139 140 141 142 144 145 146 147 148 149 150 151 158 159 160 161 162 163 164 165 167 168 169 170 171 172 173 174 176 1 3 4 5 6 7 8 10 11 12 13 14 15 16 17 105 106 107 108 109 110 111 112 113 114 115 116 117 118 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 160 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 13 Specifications ispLSI 2128VE Signal Configuration ispLSI 2128VE 208-Ball fpBGA Signal Diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A NC1 NC1 I/O 79 I/O 82 I/O 86 I/O 90 I/O 94 IN 5 I/O 96 I/O 100 I/O 104 I/O 107 I/O 110 NC1 NC1 I/O 113 A B NC1 NC1 NC1 I/O 81 I/O 84 I/O 88 I/O 91 I/O 95 I/O 98 I/O 102 I/O 106 I/O 109 I/O 111 NC1 NC1 NC1 B C I/O 77 NC1 NC1 I/O 80 I/O 83 I/O 87 I/O 92 TDO/ IN 2 I/O 97 I/O 101 I/O 105 I/O 108 I/O 112 NC1 NC1 I/O 114 C D I/O 76 I/O 78 NC1 GND VCC I/O 85 I/O 89 I/O 93 I/O 99 I/O 103 VCC VCC GND I/O 115 I/O 116 I/O 117 D E I/O 73 I/O 75 I/O 74 VCC VCC I/O 118 I/O 119 I/O 120 E F I/O 70 I/O 72 I/O 71 VCC VCC I/O 121 I/O 122 I/O 123 F G I/O 66 I/O 68 I/O 67 I/O 69 GND GND GND GND I/O 124 I/O 126 I/O 125 I/O 127 G H IN 4 I/O 64 Y1 I/O 65 GND GND GND GND IN 7 RESET Y0 GOE 1 H J GOE TCK/ 0 IN 3 Y2 I/O 63 GND GND GND GND I/O 1 TDI/ IN 0 I/O 0 BSCAN J GND GND GND GND I/O 5 I/O 3 I/O 4 I/O 2 K I/O 8 I/O 7 I/O 6 L K I/O 62 I/O 60 I/O 61 I/O 59 L I/O 58 I/O 56 I/O 57 VCC ispLSI 2128VE VCC M I/O 55 I/O 54 I/O 53 VCC Bottom View VCC I/O 11 I/O 10 I/O 9 M N I/O 52 I/O 51 I/O 49 GND VCC VCC I/O 39 I/O 35 I/O 30 I/O 26 I/O 21 VCC GND I/O 14 I/O 13 I/O 12 N P I/O 50 NC1 NC1 NC1 I/O 44 I/O 41 I/O 37 I/O 33 TMS/ IN 1 I/O 28 I/O 24 I/O 19 I/O 15 NC1 NC1 NC1 P R NC1 NC1 NC1 I/O 47 I/O 45 I/O 42 I/O 38 I/O 34 I/O 31 I/O 27 I/O 23 I/O 20 I/O 17 NC1 NC1 NC1 R T NC1 NC1 I/O 48 I/O 46 I/O 43 I/O 40 I/O 36 I/O 32 IN 6 I/O 29 I/O 25 I/O 22 I/O 18 I/O 16 NC1 NC1 T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 208 BGA/2128VE 1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package. 14 Specifications ispLSI 2128VE Pin Configuration 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 NC1 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 NC1 VCC IN 5 TDO/IN 2 GND NC1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 NC1 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79 ispLSI 2128VE 176-Pin TQFP Pinout Diagram ispLSI 2128VE Top View 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 NC1 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 NC1 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 NC1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 NC1 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 NC1 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 NC1 VCC TMS/IN 1 IN 6 GND NC1 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 NC1 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48 I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 1NC I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 1 NC IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 1NC I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1NC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14 176-TQFP/2128VE 1. NC pins are not to be connected to any active signals, VCC or GND. 15 Specifications ispLSI 2128VE Pin Configuration 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 VCC IN 5 TDO/IN 2 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79 ispLSI 2128VE 160-Pin PQFP Pinout Diagram 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 ispLSI 2128VE Top View 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 VCC TMS/IN 1 IN 6 GND I/O 32 I/O 34 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48 I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14 160-PQFP/2128VE 1. NC pins are not to be connected to any active signal, VCC or GND. 16 I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49 Specifications ispLSI 2128VE Signal Configuration ispLSI 2128VE 100-Ball caBGA Signal Diagram 10 9 8 7 6 5 4 3 2 1 A I/O 39 I/O 41 NC1 I/O 46 IN 5 VCC I/O 50 I/O 52 I/O 55 I/O 57 A B I/O 37 I/O 40 I/O 43 GND TDO/ IN 2 I/O 49 I/O 54 I/O 56 I/O 58 I/O 59 B C I/O 35 I/O 38 I/O 42 I/O 45 I/O 47 I/O 51 NC1 NC1 I/O 60 I/O 61 C D I/O 32 I/O 36 NC1 I/O 44 NC1 I/O 53 I/O 62 I/O 63 RESET IN 7 D E NC1 IN 4 I/O 33 NC1 I/O 48 BSCAN I/O 2 Y0 VCC GOE 1 E F VCC GOE 0 Y2 I/O 34 Y1 I/O 16 NC1 I/O 1 TDI/ IN 0 GND F G TCK/ IN 3 GND I/O 31 I/O 30 I/O 21 NC1 I/O 12 NC1 I/O 4 I/O 0 G H I/O 29 I/O 28 NC1 NC1 I/O 19 I/O 15 I/O 13 I/O 10 I/O 6 I/O 3 H J I/O 27 I/O 26 I/O 24 I/O 22 I/O 17 TMS/ IN 1 VCC I/O 11 I/O 8 I/O 5 J K I/O 25 I/O 23 I/O 20 I/O 18 GND IN 6 I/O 14 NC1 I/O 9 I/O 7 K 3 2 1 ispLSI 2128VE Bottom View 10 9 8 7 6 5 4 100-BGA/2128VE 1NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 17 Specifications ispLSI 2128VE Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ispLSI 2128VE Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC1 I/O 38 I/O 37 I/O 36 NC1 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 NC1 I/O 27 I/O 26 I/O 25 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 1 NC I/O 12 I/O 13 I/O 14 I/O 15 VCC TMS/IN 1 IN 6 GND I/O 16 I/O 17 I/O 18 I/O 19 1 NC I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O 57 I/O 58 I/O 59 1 NC I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 1 NC I/O 4 I/O 5 I/O 6 1 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 NC1 I/O 51 I/O 50 I/O 49 I/O 48 VCC IN 5 TDO/IN 2 GND I/O 47 I/O 46 I/O 45 I/O 44 NC1 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 ispLSI 2128VE 100-Pin TQFP Pinout Diagram 100-TQFP/2128VE 1. NC pins are not to be connected to any active signals, VCC or GND. 18 Specifications ispLSI 2128VE Part Number Description ispLSI 2128VE – XXX X XXXX X Device Family Grade Blank = Commercial I = Industrial Package Q160 = 160-Pin PQFP T176 = 176-Pin TQFP B208 = 208-Ball fpBGA T100 = 100-Pin TQFP B100 = 100-Ball caBGA Power L = Low Device Number Speed 250 = 250 MHz fmax 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax 0212/2128VE ispLSI 2128VE Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) I/Os ORDERING NUMBER PACKAGE 250 4.0 128 ispLSI 2128VE-250LT176 176-Pin TQFP 250 4.0 128 ispLSI 2128VE-250LQ160 160-Pin PQFP 250 4.0 128 ispLSI 2128VE-250LB208 208-Ball fpBGA 180 5.0 128 ispLSI 2128VE-180LT176 176-Pin TQFP 180 5.0 128 ispLSI 2128VE-180LQ160 160-Pin PQFP 180 5.0 128 ispLSI 2128VE-180LB208 208-Ball fpBGA 180 5.0 64 ispLSI 2128VE-180LT100 100-Pin TQFP 180 5.0 64 ispLSI 2128VE-180LB100 100-Ball caBGA 135 7.5 128 ispLSI 2128VE-135LT176 176-Pin TQFP 135 7.5 128 ispLSI 2128VE-135LQ160 160-Pin PQFP 135 7.5 128 ispLSI 2128VE-135LB208 208-Ball fpBGA 135 7.5 64 ispLSI 2128VE-135LT100 100-Pin TQFP 135 7.5 64 ispLSI 2128VE-135LB100 100-Ball caBGA 100 10 128 ispLSI 2128VE-100LT176 176-Pin TQFP 100 10 128 ispLSI 2128VE-100LQ160 160-Pin PQFP 100 10 128 ispLSI 2128VE-100LB208 208-Ball fpBGA 100 10 64 ispLSI 2128VE-100LT100 100-Pin TQFP 100 10 64 ispLSI 2128VE-100LB100 100-Ball caBGA Table 2-0041A/2128VE INDUSTRIAL FAMILY ispLSI fmax (MHz) tpd (ns) I/Os ORDERING NUMBER PACKAGE 135 7.5 64 ispLSI 2128VE-135LT100I 100-Pin TQFP 135 7.5 128 ispLSI 2128VE-135LT176I 176-Pin TQFP Table 2-0041B/2128VE 19