ON NCV7608DWR2G Octal configurable low/high side driver Datasheet

NCV7608
Octal Configurable
Low/High Side Driver
The NCV7608 integrates 8 output drivers configurable in any
combination of high−side, low−side, or H−Bridge configurations. The
integrated standard Serial Peripheral Interface (SPI) allows digital
control of all output stages and provides diagnostic fault information.
In addition, four channels (#5−8) can be PWM controlled via external
control input pins.
Integrated clamping circuits (both in high and low−side operational
modes), waveshaping, positive and negative transient protection, and
dedicated channel pair overtemperature shutdown circuits provide for
a wide range of automotive and industrial applications.
Features
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MARKING
DIAGRAMs
NCV7608
AWLYYWWG
SOIC−28
DW SUFFIX
CASE 751F
• Eight Independent Configurable Drivers
• RDS(on) = 1.2 W (typ @25°C)
• SPI Interface for Data Communication
16 Bit Frame Length, Daisy Chain Compatible
3.3 V/5 V Compatible
♦ Frame Detection
PWM Inputs for 4 Outputs
Ultra−low Standby Current
Over Current Protection
♦ Characterized to AEC Q10X−12−REV A
High−Side and Low−Side Flyback Protection
Fault Repoting
Undervoltage Lockout (VS and VCC)
Overvoltage Shutdown (VS)
Supports LED Loads
Supports Cold Cranking Operation Down to 3 V
Overtemperature Protection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
♦
NCV7608
AWLYYWWG
G
♦
•
•
•
•
•
•
•
•
•
•
•
•
SSOP36 EP
DQ SUFFIX
CASE 940AB
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
Typical Applications
•
•
•
•
•
Automotive
Industrial
Relay Drive
DC Motor Drive
LED Drive
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 3
1
Publication Order Number:
NCV7608/D
NCV7608
VCC VS
EN
Bias +
Supply monitoring
D5
IN5
IN6
S5
IN7
D8
IN8
S8
D1
CSB
SCLK
SI
S1
SPI
SO
D4
S4
GND
Figure 1. Block Diagram (See Figure 2 for detailed diagram)
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2
NCV7608
VCC
VS
Core Functions +
Supply Monitoring
EN
Charge Pump
D5..8
IN5
IN6
IN7
IN8
Gate Drive
Control
S5..8
Waveshaping
Slew Rate Control
Fault
Channels
5-8
Overtemp
Overcurrent
Open Load
VS
Charge Pump
CSB
D1..4
SCLK
Gate Drive
Control
SI
SO
S1..4
Channels
1-4
GND
Fault
Waveshaping
Slew Rate Control
Overtemp
Overcurrent
Open Load
To Channels 5-8
Overtemp
Channels
1&2
Overtemp
Channels
3&4
Overtemp
Channels
5&6
Figure 2. Detailed Block Diagram
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3
Overtemp
Channels
7&8
NCV7608
1
D2
S2
S1
D1
CSB
SCLK
SI
VCC
SO
GND
D5
S5
S6
D6
D2
S2
S1
D1
NC
CSB
SCLK
SI
NC
NC
VCC
SO
GND
NC
D5
S5
S6
D6
D3
S3
S4
D4
VS
IN8
IN7
IN6
IN5
EN
D8
S8
S7
D7
1
SOIC−28
D3
S3
S4
D4
VS
NC
IN8
IN7
NC
NC
IN6
IN5
EN
NC
D8
S8
S7
D7
SSOP36
Figure 3. Pin Connections
SOIC−28 PACKAGE PIN DESCRIPTION
Pin #
Symbol
Description
1
D2
Drain of configurable driver #2
2
S2
Source of configurable driver #2
3
S1
Source of configurable driver #1
4
D1
Drain of configurable driver #1
5
CSB
SPI Chip Select “Bar” (100 kW pullup resistor to VCC)
6
SCLK
SPI clock (100 kW pulldown resistor)
7
SI
8
VCC
9
SO
10
GND
11
D5
Drain of configurable driver #5
12
S5
Source of configurable driver #5
13
S6
Source of configurable driver #6
14
D6
Drain of configurable driver #6
15
D7
Drain of configurable driver #7
16
S7
Source of configurable driver #7
17
S8
Source of configurable driver #8
18
D8
Drain of configurable driver #8
19
EN
Global Enable (active high) (100 kW pulldown resistor)
20
IN5
PWM control input for driver #5, (active high) (100 kW pulldown resistor)
Ground if not used.
21
IN6
PWM control input for driver #6, (active high) (100 kW pulldown resistor)
Ground if not used.
22
IN7
PWM control input for driver #7, (active high) (100 kW pulldown resistor)
Ground if not used.
23
IN8
PWM control input for driver #8, (active high) (100 kW pulldown resistor)
Ground if not used.
24
VS
Battery Supply Input Voltage.
25
D4
Drain of configurable driver #4
26
S4
Source of configurable driver #4
27
S3
Source of configurable driver #3
28
D3
Drain of configurable driver #3
SPI serial data input (100 kW pulldown resistor)
Logic Supply Input Voltage
SPI serial data output
Ground – Device substrate
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4
NCV7608
SSOP36EP PACKAGE PIN DESCRIPTION
Pin #
Symbol
1
D2
Drain of configurable driver #2
Description
2
S2
Source of configurable driver #2
3
S1
Source of configurable driver #1
4
D1
Drain of configurable driver #1
5
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
6
CSB
SPI Chip Select “Bar” (100KW pullup resistor to VCC)
7
SCLK
SPI clock (100kW pulldown resistor)
8
SI
SPI serial data input (100kW pulldown resistor)
9
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
10
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
11
VCC
Logic Supply Input Voltage
12
SO
13
GND
SPI serial data output
14
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
15
D5
Drain of configurable driver #5
16
S5
Source of configurable driver #5
17
S6
Source of configurable driver #6
18
D6
Drain of configurable driver #6
19
D7
Drain of configurable driver #7
20
S7
Source of configurable driver #7
21
S8
Source of configurable driver #8
22
D8
Drain of configurable driver #8
23
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
24
EN
Global Enable (active high) (100kW pulldown resistor)
25
IN5
PWM control input for driver #5, (active high) (100kW pulldown resistor)
Ground if not used.
26
IN6
PWM control input for driver #6, (active high) (100kW pulldown resistor)
Ground if not used.
27
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
28
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
29
IN7
PWM control input for driver #7, (active high) (100kW pulldown resistor)
Ground if not used.
30
IN8
PWM control input for driver #8, (active high) (100kW pulldown resistor)
Ground if not used.
31
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
32
VS
Battery Supply Input Voltage.
33
D4
Drain of configurable driver #4
34
S4
Source of configurable driver #4
35
S3
Source of configurable driver #3
36
D3
Drain of configurable driver #3
Ground – Device substrate
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5
NCV7608
MAXIMUM RATINGS (Voltages are with respect to device substrate)
Rating
Symbol
Value
Unit
VCCmax
−0.3 to 7
V
VSDCmax
VSACmax
−0.3 to 34
−0.3 to 40
V
V
VIOmax
−0.3 to 7
V
Configured for High−Side Operation
Drain = VS
Source Output DC Voltage (S1−S8)
Transient Source Output voltage (S1−S8)
VSHSXDCmax
VSHSXACmax
−1 to 34
−29 to 34
V
V
Configured for Low−Side Operation
Source = GND
Drain Output DC Voltage (D1−D8)
Transient Drain Output Voltage (D1−D8)
VDLSXDCmax
VDLSXACmax
−1 to 34 (Note 1)
−1 to 48 (Note 2)
V
V
Wmax
Wrep
100
20
mJ
mJ
Digital supply input voltage (VCC)
Battery supply input voltage (VS)
DC input supply voltage
Transient input supply voltage
Digital I/O pin voltage (IN5, IN6, IN7, IN8, SI, SO, CSB, SCLK, EN)
Clamping energy
Maximum (single pulse)
Repetitive (multiple pulse) (Note )3
Electrostatic Discharge (VS, D1−D8, S1−S8)
Human Body Model (100 pF, 1.5 kW)
Machine Model (200 pF)
Charged Device
ESD4
Electrostatic Discharge (All Other Pins)
Human Body Model (100 pF, 1.5 kW)
Machine Model (200pF)
Charged Device
ESD2
AECQ10x−12−REVA
SHORT−CIRCUIT
RELIABILITY CHARACTERIZATION
Storage Temperature Range
Moisture Sensitivity Level
SO28
SSOP36−EPAD
−4000 to 4000
−200 to 200
−1000 to 1000
−2000 to 2000
−200 to 200
−1000 to 1000
V
V
AECsc
Grade B
Tstr
−55 to 150
°C
MSLso
MSLssop
MSL3
MSL2
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. In this configuration lower voltage limit is due to drain−gate clamp.
2. Internally limited.
3. 1638000 pulses (triangular), 350 mA peak, VS = 18 V, 47 W, 410 mH, TA = 85°C.
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Min
Max
Unit
Digital supply input voltage (VCC)
VCCop
3.15
5.25
V
Battery supply input voltage (VS)
Vsop
5.5
28
V
DC Output current (Sx,Dx)
Ixop
−
350
mA
TJ
−40
150
°C
Rating
Junction temperature
THERMAL CONDITIONS
Thermal Parameter (Note 4)
Value
Unit
Junction−to−Lead (YJL)
SO28
SSOP36−EP
34
37
°C/W
Junction−to−Ambient (RqJA)
SO28
SSOP36−EP
64.6
55.8
°C/W
Junction−to−Exposed−Pad (YJPAD)
SSOP36−EP
7.3
°C/W
4. PCB 50x50x1.2 mm FR4, 2s0p, 2 oz copper, 650 sq mm heater spreader area with no vias. All 8 channels are dissipating 0.147 watts of
power each.
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6
NCV7608
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5.5 V < VS < 28 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise
specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VS Supply Current
Standby (Note 5)
Run (Note 6)
IQVS85
IVSop
En = 0 V, 0 V v VCC v 5.25 V, Dx = VS
= 13.2 V, Sx = 0 V, −40°C < TJ < 85°C
All channels Active
0
−
1
−
5
12
mA
mA
VCC Supply Current
Standby (Note 7)
Run
IQVCC
IVCCop
EN = 0 V, CSB = VCC, −40°C < TJ < 85°C
all channels active, I(SO) = 0
0
−
1
−
5
3
mA
mA
GENERAL PARAMETERS
VCC Power−on reset Threshold
VCCPOR
VCC Power−on reset Hysteresis
VCChys
VS Undervoltage Threshold
VSUV
VS Undervoltage Hysteresis
VSUhys
VS Overvoltage Threshold
VSOV
VS Overvoltage Hysteresis
VSOhys
VCC increasing
VS increasing
VS increasing
2.6
2.8
3.0
V
100
200
−
mV
2.5
2.8
3.0
V
100
200
−
mV
32
36
40
V
1.0
2.5
4.0
V
THERMAL RESPONSE
TW
Not ATE tested
120
145
170
°C
Thermal Warning Hysteresis
TWH
Not ATE tested
−
30
−
°C
Overtemperature Shutdown
TLIM
Not ATE tested
155
175
195
°C
Overtemperature Shutdown
hysteresis
TLIMHY
Not ATE tested
−
30
−
°C
Ratio of Overtemperature
Shutdown to Thermal Warning
TSTOTW
Not ATE tested
1.05
1.20
−
°C/°C
VS = 8 V, I(Dx) = 200 mA
VS = 5.5 V, I(Dx) = 200 mA
VS = 3 V, I(Dx) = 200 mA
−
−
−
1.2
1.4
1.6
2.8
5.6
9.9
W
VS = Dx = 16 V, Sx = 0 V
−
−
5
mA
350
mA
Thermal Warning
POWER OUTPUTS, DC CHARACTERISTICS
Output Transistor RDS(on)
(Note 8)
Output Leakage Current (Note 9)
RonOPx
RonVSminx
RonVS3
Ilkgx
Open Load Diagnostic Sink
Current Low Side
IdiagLSx
Open Load Diagnostic Source
Current High Side (Note 10)
IdiagHSx
Open load detection threshold
voltage, VD (LS)
Open load detection threshold
voltage, VS (HS)
Dx = 2.6 V, Sx = 0 V, Output disabled
100
215
Dx = VS, Sx = VS − 2.6 V, Output
disabled
−40°C < TJ < 125°C
mA
−500
−330
−150
VOLDx
1.0
2.0
3.0
V
VOLSx
VS−3
VS−
2
VS−1
V
−1.90
0.80
−1.35
1.35
−0.80
1.90
50
50
100
100
200
200
Over Current (Note 11)
High−Side
Low−Side
IlimHS
IlimLS
Output fault filter time
Over Current
Open Load
TFOC
TFOL
VS = 16 V
VS = 16 V
5. Refer to Figures 13 and 18 for the VS standby current behavior.
6. Refer to Figure 11. I(VS) versus Temperature.
7. Refer to Figure 17 for the VCC standby current behavior.
8. Refer to Figures 12 and 15 for RDS(on) behavior.
9. Refer to Figure 16 for output leakage current behavior.
10. Refer to Figures 19 and 20 for open load diagnostic current behavior.
11. Refer to Figure 14 for current limit behavior.
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7
A
ms
NCV7608
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 5.5 V < VS < 28 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise
specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
34
−
48
−29
−22
−16
Unit
OUTPUT CLAMPS
Output clamp Voltage
Drain with respect to Source
VOCLS
I(Dx) = 50 mA
Source = GND
Output clamp Voltage
Source with respect to GND
VOCHS
I(Sx) = −50 mA, VS = 14 V
V
V
POWER OUTPUTS, AC CHARACTERISTICS
Low Side Rise Time
T_LSr
8 V < VS < 16 V
Rload = 70 W
10/90% criteria, Figure 5
Low Side Fall Time
T_LSf
8 V < VS < 16 V
Rload = 70 W
10/90% criteria, Figure 4
High side Rise Time
T_HSr
8 V < VS < 16 V
Rload = 70 W
10/90% criteria, Figure 4
High side Fall Time
T_HSf
Serial Control
Output turn−on time (High side
and Low−side configuration)
TDONs
Serial Control
Output turn−off time (High side
and Low−side configuration)
TDOFFs
8 V < VS < 16 V
Rload = 70 W
10/90% criteria, Figure 5
8 V < VS < 16 V
CSB going high (at 90%)
to Vfinal going high (at 10%)
or Vfinal going low (at 90%)
Rload = 70 W, Figure 4
8 V < VS < 16 V
CSB going high (at 90%)
to Vfinal going low (at 90%)
or Vfinal going high (at 10%)
Rload = 70 W, Figure 5
Parallel Control
Output turn−on time (High side
and Low−side configuration)
TDONp
8 V < VS < 16 V
Inx going high (at 90%)
to Vfinal going high (at 10%)
or Vfinal going low (at 90%)
Rload = 70 W, Figure 6
Parallel Control
Output turn−off time (High side
and Low−side configuration)
TDOFFp
8 V < VS < 16 V
Inx going low (at 10%)
to Vfinal going low (at 90%)
or Vfinal going high (at 10%)
Rload = 70 W, Figure 7
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8
ms
−
12
50
ms
−
12
50
ms
−
12
50
ms
−
12
50
ms
1
−
50
ms
1
−
100
ms
1
−
50
ms
1
−
100
NCV7608
CSB
CSB
T_HSf
T_HSr
High−Side
High−Side
T_HSf
TDOFFs
Low−Side
Low−Side
T_LSf
T_LSr
TDONs
Figure 4. Serial Turn On
Figure 5. Serial Turn Off
INx
INx
High−Side
High−Side
TDOFFp
Low−Side
Low−Side
TDONp
Figure 6. Parallel Turn On
Figure 7. Parallel Turn Off
CSB
INx
SCLK
10 MHz
EN
END
SO
HS
LS
EN
SPIWak
Figure 8. EN Delay Time
Figure 9. SPI Wake Up
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9
NCV7608
Table 1. DIGITAL INTERFACE CHARACTERISTICS
Min
Typ
Max
Unit
Digital Input High Threshold
Characteristic
VINH
2.0
−
−
V
Digital Input Low Threshold
VINL
−
−
0.6
V
Input Pulldown Resistance
(EN, SI, SCLK, IN5, IN6, IN7, IN8)
RPDx
EN = SI = SCLK = VCC,
IN5 = IN6 = IN7 = IN8 = VCC
50
100
200
kW
IPUCSB
CSB = 0 V
50
100
200
kW
CSB Leakage to VCC
ILCSx
CSB = 5 V, VCC = 0 V
−
−
10
mA
Input Capacitance (Note 12)
CINx
Not ATE Tested
−
−
15
pF
SO – Output High
VOUTH
I(out) = −1 mA
VCC − 1.0
−
−
V
SO – Output Low
VOUTL
I(out) = 1.6 mA
−
−
0.4
V
SO Tristate Leakage
ILSOx
CSB = VCC
−10
−
10
mA
SO Tristate Input Capacitance
(Note 12)
CSOx
Not ATE Tested
−
−
15
pF
SCLK Frequency
CLKf
VCC = 5 V
VCC = 3.3 V
−
−
−
−
5
2
MHz
SCLK Clock Period
CLKper
VCC = 5 V
VCC = 3.3 V
200
500
−
−
−
−
ns
ns
SCLK High Time
CLKH
VCC = 5 V, Figure 10
85
−
−
ns
SCLK Low Time
CLKL
VCC = 5 V, Figure 10
85
−
−
ns
SCLK Setup Time
CLKsup
VCC = 5 V, Figure 10
85
−
−
ns
SI Setup Time
Sisup
VCC = 5 V, Figure 10
50
−
−
ns
SI Hold Time
SIH
VCC = 5 V, Figure 10
50
−
−
ns
CSB Setup Time
Cssup
VCC = 5 V, Figure 10
100
−
−
ns
CSB High Time
CSH
VCC = 5 V, Figure 10
200
−
−
ns
SO enable after CSB falling edge
(Note 12)
CStSOf
VCC = 5 V, Figure 10
−
−
50
ns
SO disable after CSB rising edge
(Note 12)
CStSOr
VCC = 5 V, Figure 10
−
−
50
ns
SO Rise Time
SOR
VCC = 5 V, Cload = 40 pF
−
−
25
ns
SO Fall Time
SOF
VCC = 5 V, Cload = 40 pF
−
−
25
ns
SO Valid Time (Note 12)
SOV
VCC = 5 V, Cload = 40 pF,
Figure 10
−
−
50
ns
EN Low Valid Time
ENL
10
−
−
ms
EN Delay Time
END
VCC = INx = 5 V
EN going high 50% to OUT5 −
OUT8 turning on 50%.
−
−
100
ms
SPIWak
SI = 5 V, CSB = 0 V, SCLK =
10 MHz, EN going high 50%
to SO going high 50%,
Figure 9
−
−
200
ms
Input Pullup Resistance (CSB)
SPI wake up after EN rising edge
Symbol
Conditions
12. Not subject to production testing.
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10
NCV7608
CLKSUP
CSH
CSB
CSSUP
CSSUP
SCLK
CLKSUP
CLKH
CLKL
CSB
SO
CStSOv
CStSOf
SI
SIH
SCLK
SOV
SISUP
SO
Figure 10. Detailed SPI Timing
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NCV7608
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
6.0
VS = 28 V, VCC = 5.5 V
VS = 28 V, VCC = 3.15 V
1.5
1.0
0.5
VS = 5.5 V, VCC = 5.25 V
VS = 5.5 V, VCC = 3.15 V
0
−50
0
50
4.0
3.0
2.0
VS = 8 V, HS
100
150
VS = 8 V, LS
0.0
−50
200
0
50
200
Figure 11. I(VS) vs. Temperature
Figure 12. RDS(on) vs. Temperature
8.00
1.520
VS = 16 V, HS
1.500
ILIM (A)
6.00
5.00
4.00
3.00
1.480
1.460
VS = 16 V, LS
1.440
2.00
1.420
1.00
1.400
0
−1.00
0
5
10
15
20
25
1.380
−50
30
0
50
VS (V)
150
200
Figure 14. Output Over Current vs.
Temperature
12
3
10
OUTPUT LEAKAGE (mA)
3.5
2.5
2
HS Driver
1.5
100
TEMPERATURE (°C)
Figure 13. I(VS) Standby Current vs. VS at 255C
RDS(on) (W)
150
TEMPERATURE (°C)
1.540
LS Driver
0.5
0
100
TEMPERATURE (°C)
9.00
1
VS = 5.5 V, HS
VS = 3 V, LS
VS = 5.5 V, LS
1.0
7.00
I(VS) (mA)
VS = 3 V, HS
5.0
RDS(on) (W)
I(VS) (mA)
2.0
8
6
150°C
4
2
25°C
−40°C
125°C
0
0
5
10
15
20
25
30
35
−2
−5
0
5
10
15
20
25
VS (V)
DRAIN AND SUPPLY VOLTAGE (V)
Figure 15. RDS(on) vs. VS
Figure 16. Standby Output Leakage vs. VS
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12
30
NCV7608
TYPICAL PERFORMANCE CHARACTERISTICS
5.0
16
4.5
14
4.0
12
2.5
2.0
1.5
VS = 28 V,
VCC = 3.15 V
1.0
0
VS = 28 V, VCC = 5.25 V
VS = 13.2 V, VCC = 5.25 V
6
VS = 5.5 V, VCC = 5.25 V
VS = 5.5 V, VCC = 3.15 V
2
0
0.0
−0.5
−50
8
4
VS = 5.5 V,
VCC = 5.25 V
0.5
VS = 28 V, VCC = 3.15 V
VS = 13.2 V, VCC = 3.15 V
10
VS = 5.5 V, VCC = 3.15 V
VS = 28 V, VCC = 5.25 V
3.0
I(VS) (mA)
I(VCC) (mA)
3.5
50
100
TEMPERATURE (°C)
150
−2
−50
200
300
LS, VS = 28 V
200
LS, VS = 5.5 V
100
0
−100
−200
HS, VS = 5.5 V
−300
−400
−500
−50
HS, VS = 28 V
0
50
100
TEMPERATURE (°C)
150
200
Low Side
200
100
0
−100
−200
High Side
−300
−400
−500
0
5
10
15
20
25
30
VS (V)
Figure 20. Open Load Detect Current vs. VS @
255C
1.20
50
40
CLAMP VOLTAGE (V)
−40°C
1.00
V(Diode) (V)
150
300
Figure 19. Open Load Detect Current vs.
Temperature
25°C
0.80
125°C
0.60
150°C
0.40
0.20
0.00
0
50
100
TEMPERATURE (°C)
Figure 18. VS Standby Current vs.
Temperature
OPEN LOAD DIAGNOSTIC CURRENT (mA)
OPEN LOAD DIAGNOSTIC CURRENT (mA)
Figure 17. I(VCC) vs. Temperature
0
30
20
10
0
−10
−20
0.10
0.20
0.30
0.40
Drain−to−Source Clamp
−30
−50
Source−to−Ground Clamp
0
50
100
150
I(Diode) (A)
TEMPERATURE (°C)
Figure 21. Source−to−Drain Voltage Body
Diode
Figure 22. Output Clamp vs. Temperature
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200
NCV7608
DETAILED OPERATING DESCRIPTION
Normal Operation
SPI−Interface
The device provides a 16 bit SPI−interface. Data is
imported into the NCV7608 through the SI (serial input) pin.
Data is exported out of the NCV7608 through the SO (serial
output) pin. The input−frame (SI) is used to command the
output stages and program individual channel open load
diagnostics. The response frame (SO) provides
channel−specific (1bit / channel) status information and
fault information. See Table 1 for channel status decoding.
Words should be composed of 16 bits LSB (least significant
bit) transmitted first.
Power Outputs
The NCV7608 provides eight independent power
transistors with pins D1−D8, and S1−S8 as drain and source
outputs respectively. For High−side Drive configurations
(sourcing), the drain pins are connected to the battery supply.
In Low−Side configurations (sinking), the drain pins are
connected to the load. All outputs may be configured as
high−side, low−side, half−bridge, or H−bridge. Internal
clamping structures are provided to limit transient voltages
when switching inductive loads.
CSB
SI
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
OL1
OL2
OL3
OL4
OL5
OL6
OL7
OL8
IN6
State
IN7
State
IN8
State
N/A
N/A
VS
PSM
SCLK
SO
IN5
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 State
TW
Figure 23. SPI Frame
CSB
OUT1
OL7
OL8
SI
SCLK
SO
TW
N/A
Figure 24. SPI Frame Detail
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14
VS
PSM
NCV7608
Table 2. SPI INPUT / OUTPUT
Input Data
Bit
Number
Output Data
Bit Description
Bit Status
Bit
Number
15
Driver 8
Open Diagnostic Enable
0 = Disable
14
Driver 7
Open Diagnostic Enable
0 = Disable
Driver 6
Open Diagnostic Enable
Driver 6
Open Diagnostic Enable
0 = Disable
Driver 5
Open Diagnostic Enable
0 = Disable
Driver 4
Open Diagnostic Enable
0 = Disable
Driver 3
Open Diagnostic Enable
0 = Disable
9
Driver 2
Open Diagnostic Enable
0 = Disable
8
Driver 1
Open Diagnostic Enable
0 = Disable
Driver 8 Enable
0 = Disable
13
12
11
10
7
Bit Description
Bit Status
15
VS Power Supply
Monitoring
0 = No Fault
14
N/A
0
13
N/A
0
12
IN8 State (Note 13)
0 = (IN8 = 0)
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = (IN8 = 1)
11
IN7 State (Note 13)
1 = Enable
10
IN6 State (Note 13)
1 = Enable
9
IN5 State (Note 13)
8
Driver 8 Status
0 = Disable
5
Driver 6 Enable
0 = Disable
7
Driver 7 Status
6
Driver 6 Status
0 = No Fault
5
Driver 5 Status
0 = No Fault
1 = Fault
1 = Fault
4
0 = Disable
Driver 4 Status
1 = Enable
Driver 4 Enable
0 = Disable
2
Driver 3 Enable
0 = Disable
3
Driver 3 Status
0 = No Fault
2
Driver 2 Status
0 = No Fault
1 = Fault
1 = Enable
Driver 2 Enable
1 = Fault
1
0 = Disable
Driver 1 Status
1 = Enable
0
Driver 1 Enable
0 = No Fault
1 = Fault
1 = Enable
1
0 = No Fault
1 = Fault
1 = Enable
3
0 = No Fault
1 = Fault
1 = Enable
Driver 5 Enable
0 = (IN5 = 0)
1 = (IN5 = 1)
1 = Enable
Driver 7 Enable
0 = (IN6 = 0)
1 = (IN6 = 1)
1 = Enable
6
0 = (IN7 = 0)
1 = (IN7 = 1)
1 = Enable
4
1 = Fault
0 = No Fault
1 = Fault
0
0 = Disable
1 = Enable
Thermal Warning
(TW)
0 = No Fault
1 = Fault
An output driver (Driver Status) fault is either open load,
over current, or over temperature.
13. When over current or thermal shutdown fault occurs, bits 9 through 12 records the state of INx.
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NCV7608
SPI Input
Parallel Input (INx) State (bits 9−12)
The state of the parallel (PWM) input pins (Inx) are
mirrored to SPI output bits #9−12. When overcurrent or
thermal shutdown fault occurs, bits 9 through 12 record the
state of INx. This enables the user to distinguish an open load
fault from an over current fault when the NCV7608 is
operated from two isolated controllers for the SPI input and
the Parallel input.
Driver Enable (bits 0−7)
A zero turns the driver off.
A one turns the driver on.
Open Load Diagnostic (bits 8−15)
A zero programming bit disables the detection of an open
load condition.
A one programming bit enables the detection of an open load
condition.
SPI Output
Table 3. SO DRIVER STATUS INFORMATION SUMMARY (Bits 0−8, 15)
Driver
Enable
Open Load
Diagnostic
enable
Disabled
Disabled
0
N/A
Disabled
Enabled
0 (No Open Load)
N/A
1 (Open Load Detected)
N/A
0 (No Fault)
N/A
1 (Over Current)
A valid SPI command with the offending Driver DISABLED is received.
1 (VS Power supply fail)
Any valid SPI command AND VS within limits
1 (Thermal Warning)
N/A
1 (Thermal Shutdown)
The over temperature goes away AND a valid SPI frame with the
offending driver pair DISABLED is received.
Enabled
SO Feedback
X
Status Information Reset Requirement
X=Don’t Care
Frame Detection
The frame length detector is enabled with the CSB falling
edge and the SCLK rising edge.
SCLK must be low during the CSB rising edge.
Reference the valid SPI frame shown below.
Input word integrity (SI) is evaluated by the use of a frame
consistency check. The word frame length is compared to an
n * 16 bit (where n is an integer) acceptable word length
before the data is latched into the input register. This
guarantees the proper word length has been imported and
allows for daisy chain operation applications.
Frame detection mode ends with
CSB rising edge.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
CSB
SCLK
SI
OUT1
Internal Counter 1
OUT2
OUT3
2
3
OUT4
4
OUT5
5
OUT6
OUT7
OUT8
OL1
6
7
8
9
OL2
OL3
10
11
OL4
12
OL5
13
OL6
14
OL7
15
OL8
Valid 16 bits shown
16
Figure 25. Frame Detection
PWM Operation
The SPI information is OR’d with the respective Parallel
input control pins (INx).
INx = 1 activates the output stage.
Channels 5, 6, 7, and 8 can be controlled via the serial port
(SPI) or via the respective parallel port input pins
(IN5−IN8).
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NCV7608
INx = 0 deactivates the output stage.
Special attention should be paid to detection of over
current and open load conditions when operated in a pwm
mode. These faults are detected in a 100 ms (typ) time
window. Faults will not be detected at higher frequencies if
the time period of the input signal does not allow for 100 ms
detection time.
Handling of Fault Conditions
Table 4. FAULT SUMMARY TABLE
Fault
Fault Memory
Driver Condition
Output Register Clear Requirement
None
Allowed to turn on
N/A
Latched
Latched Off
A valid SPI command is received with the
offending driver disabled
None
Allowed to turn/ remain on as
long as the device is not in
thermal shutdown
N/A
Thermal Shutdown
Latched
(Note 14)
Latched Off
The over temperature goes away AND a valid
SPI frame with the offending driver pair
DISABLED is received.
VS Power Supply Fail
Latched
(Note 14)
Allowed to turn on while the
Voltage is within operating
range
After ANY valid SPI frame & voltage within
operating range
Open Load
Over Current
Thermal Warning
14. Latched conditions are cleared in the same manner (via the SPI port) during normal operation regardless of the driver turn on command path
(via a SPI command or via a parallel input command). Latches are also cleared by cycling the EN pin or with a power−on reset of VCC.
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NCV7608
Start
No
Driver ON Yes
Current
Limit
Yes
Over
Current
TFOC
Yes
Report
Fault
Latch Fault
Fault Reported on SO
No
No
No
No
Open Load
Yes
Thermal
Warning
Yes
Thermal
Warning
Delay
Yes
No
CSB Low
Yes
Report
Fault
Fault Reported on SO
No
TFOL
No
Thermal Yes
Shutdown
No
Delay
Thermal Yes
Shutdown
Report
Fault
Latch Fault
Fault Reported on SO
Report
Fault
Latch Fault
Fault Reported on SO
No
CSB Low
Yes
No
Report
Fault
VS Power
Supply Fail
Yes
Delay
VS Powerr
Supply FailYes
No
Fault Reported on SO
Figure 26. Fault Reporting Flow Chart
Fault Filters
architecture whereby the microprocessor sends a command
(such as turning a device on when a short circuit exists) and
then proceeds to other focused microprocessor activity.
Eliminating an auto retry upon over current fault detection
scheme reduces IC stress by reducing the frequency of
attempts to turn back on.
The NCV7608 detects overtemperature, over current, VS
Power Supply and open load faults. Faults are reported in the
Output Data fault register. The fault filter timer for over
current or open load is 100 ms (typ). An over current or open
load event must exist for this period of time to be recognized.
There are eight fault timers, one dedicated to each driver for
use for both over current and open load. Thermal Warning,
Thermal Shutdown and VS Power Supply Fail each have
there own dedicated timers.
Thermal Warning & Overtemperature Shutdown
Four independent Overtemperature shutdown circuits are
featured (one common sensor for each drive pair). Channels
are sequentially paired together with its own thermal
detection circuit as Channels 1 and 2, Channels 3 and 4,
Channels 5 and 6, and Channels 7 and 8. Each thermal
detection circuit senses two temperature levels, one to give
a Thermal Warning (145°C typ) (TW, bit = 0), and one to
shut the driver pair off (Overtemperature) at a higher
temperature 30°C above TW (175°C typ). When the thermal
detection circuit reaches the temperature point of Thermal
Warning, the output data bit 0 (TW) will be set to a 1, and the
outputs will remain on. Overtemperature events will be
recorded as faults to the offending Output Driver pair
Open Load
Open Load conditions are detected in the off mode. See
“OFF−Mode Open Load Diagnostics” for details.
Over Current
The output current is limited in both high−side and
low−side configuration. Over Current is detected in the turn
on mode. High power dissipation during over current can
cause overtemperature shutdown. Over Current is a latched
off event. Latching off a driver in over current is especially
useful in systems utilizing a hierarchical software
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NCV7608
independently of the input state (serial or parallel).
Overtemperature shutdown is a latched event.
Since thermal warning precedes an overtemperature
shutdown, software polling of this bit will allow for load
control and possible prevention of overtemperature
shutdown conditions.
cycle. Figure 27 below displays how this is accomplished.
Bringing the CSB pin from a 1 to a 0 condition immediately
displays the information on the output data bit 0, thermal
warning, even in the absence of a SCLK signal. As the
temperature of the NCV7608 changes from a condition from
below the thermal warning threshold to above the thermal
warning threshold, the state of the SO pin changes and this
level is available immediately when the CSB goes to 0. A 0
on SO indicates there is no thermal warning, while a 1
indicates the IC is above the thermal warning threshold.
Thermal Warning Retrieval
Thermal warning information can be retrieved
immediately without performing a complete SPI access
Figure 27. Accessing Thermal Warning Bit
Power Supply Monitoring
status after reaching operational VS levels provided VCC
UVLO is not breached. The SPI port remains active during
VS overvoltage within a valid VCC voltage. Bit #15 is
cleared with any valid SPI frame and VS within the
operating limits.
Undervoltage shutdown
Both supply voltages (VCC and VS) are monitored for
undervoltage. When VCC goes below the threshold, all
outputs are turned OFF and the input and output registers are
cleared. An undervoltage condition on VS will cause all
channels to shut down. The fault bit (Bit #15) is latched in
the Output Data Register. The channels will return to the
commanded status after reaching operational VS levels
provided VCC UVLO is not breached. The SPI port remains
active during VS undervoltage within a valid VCC voltage.
Drivers are guaranteed to operate with automotive cranking
voltages down to 3 V on VS per the undervoltage shutdown
thresholds. Bit# 15 is cleared with a valid SPI frame and VS
within the operating limits.
OFF−Mode Open Load Diagnostics
Open load diagnostics are performed when the drivers are
off (provided the channel is programmed to perform the
operation via Bits #8 through #15). Open load diagnostics
are performed by connecting two tracking current sources
(IDIAGHSx and IDIAGLSx) to the corresponding outputs.
To support both operation modes (high−side and low−side)
and provide minimum delay due to external capacitances,
both Drain and Source pin voltages of the device are
monitored to generate the diagnostic information. Channel
diagnostic information is directed to the output data register.
Open load diagnostics are disabled during VS undervoltage
or overvoltage events or when EN is low.
Figure 28 shows the NCV7608 open load diagnostics
principles.
Figure 29 shows the internal circuitry used with the device
set up as a low−side driver.
Figure 30 shows the internal circuitry used with the device
set up as a high−side driver.
Overvoltage shutdown
VS is continuously monitored for overvoltage conditions.
The threshold is set above automotive jump start conditions
allowing operation of the IC during jump start. The
minimum overvoltage threshold is 32 V. When VS goes
above the overvoltage threshold voltage, all outputs are
turned OFF. The fault bit (Bit #15) is latched in the Output
Data Register. Input and output registers maintain all
information. The channels will return to the commanded
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NCV7608
Figure 28. Open Load Diagnostic Principle
Figure 29. Open Load Circuitry as Low Side Driver
Figure 30. Open Load Circuitry as High Side
Driver
Open Load Diagnostic Performance
operation through the parallel inputs (IN5...IN8). An
internal pulldown resistor is provided to ensure device
turn−off in the event the enable signal is lost.
A low on EN will result in a power−on−reset to the logic.
All outputs will be shut off and all registers reset.
System design sometimes requires open load diagnostics
to be turned off to prevent unintended operation. Input Bits
8−15 control this function.
One application example would be driving LED’s.
Leaving the diagnostic circuitry turned on would result in
visible illumination of the LED’s because of the currents
used in open load detection. Open load detection may still be
utilized by testing at low time intervals.
Loss of Ground
The NCV7608 output drivers will not be active during a
loss of ground condition. No damage to the device will occur
during this condition for VS less than or equal to 16 V.
Miscellaneous
Diagnostic Implementation
To provide maximum flexibility in using the device as an
H−Bridge driver, a current ratio between the HS and LS
diagnostic currents is implemented (the diagnostic source
current is always higher in magnitude than the diagnostic
Enable
A logic low on EN puts the device in a current saving
mode. Quiescent current (VCC) with EN low is less than
5 mA. A logic high on EN powers up the device allowing
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NCV7608
Open Load is not a latched condition and is not reported
when drivers are on.
To be captured, Open Load must be present when CSB goes
low.
* SPI Driver Enable bit = 0 and associated INx = 0
sink current). Equal diagnostic currents would result in
unpredictable results due to process variation.
Timing Information
Open Load
Open Load is reported if open load is enabled and an open
load fault exists.
CSB
SO
OL enabled
Driver Off*
OL enabled
Driver Off
OL enabled
Driver Off
OL enabled
Driver Off
No Fault Fault No Fault
Open Load
Exists
No Open
Load Exists
Open Load
Absent
OL enabled
Driver Off
OL enabled
Driver On
Fault No Fault Fault
Open Load
Exists
Open Load
Absent
Open Load
Exists
OL disabled
Driver Off
OL disabled
Driver On
No Fault
No Fault
Driver
Turns On
Driver
Turns
On
Figure 31. Open Load Timing Diagram
Over Current
To reset the driver status bit for over current, a valid SPI
frame with ENx = 0 is required. This will reset the driver
status bit and the driver can be turned back on in the next
valid SPI frame.
Over current is reported if the drivers’ over current
detection threshold is breached.
The driver is latched off after 100 ms from the over current
detection.
CSB
SO
Driver OnDriver OnDriver Off
No Fault Fault
No Over Current
Detected.
Fault
Over current
condition is
removed
Over Current detected
Driver latched off
Driver On
No Fault
Fault is Reset
Driver Turns On
INx=0
Figure 32. Over Current Timing Diagram
Thermal Warning and Thermal Shutdown
The driver status is reset if the die temperature falls below
175°C (typ) – 30°C (typ) and a valid SPI frame with the
Driver(s) x Enable bit = 0. The driver(s) can then be turned
on in the next valid SPI frame with the Driver x Enable(s) =
1.
Thermal Warning is reported in bit #0 when the die
temperature goes above 145°C (typ)
and does not fall below 145°C (typ) – 30°C hysteresis
(typ). Thermal Warning is only sampled and reported when
CSB is low.
Thermal Shutdown will turn off the two drivers associated
with the thermal sensor when the die temperature is above
175°C (typ). The driver status bit will be latched.
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NCV7608
CSB
Driver OnDriver OnDriver Off
SO
No Fault Fault No Fault
No TW
detected
TW is detected
Driver continues to run
Thermal Warning
condition is removed
Driver On
Fault
TW is detected
Driver continues to be off
Figure 33. Thermal Warning Timing Diagram
CSB
SO
Driver OnDriver OffDriver On
Fault
Fault No Fault
Fault Reset
TSD (T > 175°C)
Driver Off
Driver
Turns On
T<(175°C-30°C)
Figure 34. Thermal Shutdown Timing Diagram
Power Supply Fail
When coming out of VS OV or UV, the drivers will take
on the state determined by the last valid SPI frame.
The VS Power Supply Monitoring bit (bit #15) will be
reset by any valid SPI frame.
VS Overvoltage (OV) or undervoltage (UV) is reported
using bit #15 (PSM) in the SO output data register. This is
a latched event.
Drivers will shut off during VS OV or UV.
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NCV7608
Assumes a valid SPI frame.
Figure 35. Power Supply Fail Timing Diagram
3.0
170
28 Lead SOIC
36 Lead SSOP−EP
130
1.0 oz
110 2.0 oz
1.0 oz
90
2.0 oz
70
50
0
100
1.0 oz
2.0 oz
1.0 oz
2.5
MAXIMUM POWER (W)
qJA (°C/W)
150
2.0
2.0 oz
1.5
1.0
28 Lead SOIC
36 Lead SSOP−EP
0.5
200
300
400
500
600
700
0
800
0
100
200
300
400
500
600
700
800
COPPER HEAT SPREADER AREA (mm2)
COPPER HEAT SPREADER AREA (mm2)
Figure 36. qJA vs. Copper Heat Spreader
Figure 37. Maximum Power vs. Copper Heat
Spreader
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900
NCV7608
100
R(t) (°C/W)
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 38. NCV7608−28 Lead SOIC (body 18x7.55x2.55 mm) PCB Cu Area 650 sq mm PCB thk 2 oz All Outputs On
100
R(t) (°C/W)
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
TIME (sec)
Figure 39. 4.2x5.8x0.25 mm−36 Lead SSOP−EP PCB Cu Area 650 sq mm PCB thk 2 oz All Outputs On
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1000
NCV7608
Typical Application
The drawing below demonstrates the versatility of the NCV7608 in a typical application.
VS
NCV8664 NCV7608 supports both
13.2V 3.3 V and 5 V digital Rail
5V
10 uF for 5 V
3.3V
100 nF
22 uF for 3.3 V
MRA4003T3
13.2 V
100 nF
100 nF
CSB
SCLK
SI
SO
EN
IN5
IN6
IN7
IN8
MCU
VS
LS Relay
320 mH,
70 Ohm
VCC
VS
NCV7608
VS
D2
D3
S2
D1
S3
D4
S1
S4
D5
D8
S5
D6
S8
D7
320 mH,
70 Ohm
HS Relay
VS
VS
S6
GND
S7
ORDERING INFORMATION
Package
Shipping†
NCV7608DWR2G
SOIC−28 WB
(Pb−Free)
1000 / Tape & Reel
NCV7608DQR2G
SSOP36−EP
(Pb−Free)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV7608
PACKAGE DIMENSIONS
SOIC−28 WB
CASE 751F−05
ISSUE H
−X−
D
28
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
H
E
0.25
M
Y
M
−Y−
1
14
PIN 1 IDENT
A
L
0.10
G
B
0.025
M
T X
S
−T−
A1
Y
SEATING
PLANE
C
M
S
SOLDERING FOOTPRINT*
8X
11.00
28X
1.30
1
28
28X
0.52
1.27
PITCH
14
15
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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26
DIM
A
A1
B
C
D
E
G
H
L
M
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0_
8_
NCV7608
PACKAGE DIMENSIONS
0.20 C A-B
SSOP36 EP
CASE 940AB
ISSUE O
D
4X
E1
1
X = A or B
e/2
E
DETAIL B
36X
0.25 C
18
e
36X
B
b
0.25
TOP VIEW
A
H
X
19
ÉÉÉ
ÉÉÉ
PIN 1
REFERENCE
D
DETAIL B
A
36
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED
BETWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICATED AREA.
M
T A
B
S
S
NOTE 6
h
A2
DETAIL A
c
h
0.10 C
36X
SIDE VIEW
A1
C
END VIEW
SEATING
PLANE
D2
M1
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L2
M
M1
MILLIMETERS
MIN
MAX
--2.65
--0.10
2.35
2.60
0.18
0.36
0.23
0.32
10.30 BSC
5.70
5.90
10.30 BSC
7.50 BSC
3.90
4.10
0.50 BSC
0.25
0.75
0.50
0.90
0.25 BSC
0_
8_
5_
15 _
SOLDERING FOOTPRINT*
L2
C
5.90
M
GAUGE
PLANE
E2
SEATING
PLANE
36X
36X
1.06
L
DETAIL A
4.10
BOTTOM VIEW
10.76
1
0.50
PITCH
36X
0.36
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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