OKI MSM514102DL-80SJ 4,194,304-word x 1-bit dynamic ram : static column mode type Datasheet

E2G0149-29-41
¡ Semiconductor
MSM514102D/DL
¡ Semiconductor
This version:
Apr. 1999
MSM514102D/DL
4,194,304-Word ¥ 1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE
DESCRIPTION
The MSM514102D/DL is a 4,194,304-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514102D/DL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM514102D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514102DL (the low-power version) is specially
designed for lower-power applications.
FEATURES
• 4,194,304-word ¥ 1-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Static Column mode, read modify write capability
• CS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ
(SOJ26/20-P-300-1.27)
(Product : MSM514102D/DL-xxSJ)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM514102D/DL-xxZS)
26/20-pin 300 mil plastic TSOP
(TSOPII26/20-P-300-1.27-K) (Product : MSM514102D/DL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
tRAC
tAA
tCAC
MSM514102D/DL-60
60 ns
30 ns
15 ns
110 ns
495 mW
MSM514102D/DL-70
70 ns
35 ns
20 ns
130 ns
440 mW
MSM514102D/DL-80
80 ns
40 ns
20 ns
150 ns
385 mW
5.5 mW/
1.1 mW (L-version)
1/17
¡ Semiconductor
MSM514102D/DL
PIN CONFIGURATION (TOP VIEW)
DIN 1
A9 1
26 VSS
WE 2
DOUT 3
25 DOUT
RAS 3
24 CS
DIN 5
NC 4
23 NC
RAS 7
A10 5
22 A9
NC 9
A0 11
A0 9
18 A8
A2 13
A1 10
17 A7
VCC 15
A2 11
16 A6
A5 17
A3 12
15 A5
A7 19
VCC 13
14 A4
2 CS
4 VSS
6 WE
8 A10
10 NC
12 A1
14 A3
16 A4
18 A6
20 A8
DIN 1
26 VSS
WE 2
25 DOUT
RAS 3
24 CS
NC 4
23 NC
A10 5
22 A9
A0 9
18 A8
A1 10
17 A7
A2 11
16 A6
A3 12
15 A5
VCC 13
14 A4
20-Pin Plastic ZIP
26/20-Pin Plastic SOJ
Pin Name
A0 - A10
26/20-Pin Plastic TSOP
(K Type)
Function
Address Input
RAS
Row Address Strobe
CS
Chip Select Input
DIN
Data Input
DOUT
Data Output
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
2/17
¡ Semiconductor
MSM514102D/DL
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CS
11
Column
Address
Buffers
11
Internal
Address
Counter
A0 - A10
11
Row
Address
Buffers
Refresh
Control Clock
11
Row
Decoders
Word
Drivers
Column
Decoders
Write
Clock
Generator
Sense
Amplifiers
I/O
Selector
Memory
Cells
Input
Buffer
WE
Output
Buffer
DOUT
DIN
VCC
On Chip
VBB Generator
VSS
3/17
¡ Semiconductor
MSM514102D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A10, DIN)
CIN1
—
6
pF
Input Capacitance (RAS, CS, WE)
CIN2
—
7
pF
Output Capacitance (DOUT)
COUT
—
7
pF
4/17
¡ Semiconductor
MSM514102D/DL
DC Characteristics
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Condition
MSM514102 MSM514102 MSM514102
D/DL-60
D/DL-70
D/DL-80
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
90
—
80
—
70
mA 1, 2
—
2
—
2
—
2
—
1
—
1
—
1
—
200
—
200
—
—
90
—
80
—
5
—
—
90
—
—
0 V £ VI £ 6.5 V;
Input Leakage Current
ILI
All other pins not
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
DOUT disable
0 V £ VO £ 5.5 V
RAS, CS cycling,
tRC = Min.
RAS, CS = VIH
Power Supply
Current (Standby)
ICC2 RAS, CS
≥ VCC –0.2 V
1
200
mA
1, 5
—
70
mA 1, 2
5
—
5
mA
—
80
—
70
mA 1, 2
80
—
70
—
60
mA 1, 3
300
—
300
—
300
mA
RAS cycling,
Average Power
ICC3 CS = VIH,
Supply Current
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5 CS = VIL,
ICC6
Supply Current
(CS before RAS Refresh)
RAS cycling,
CS before RAS
Average Power
RAS = VIL,
Supply Current
ICC9 Address cycling,
(Static Column Mode)
tSC = Min.
tRC = 125 ms,
Average Power
ICC10 CS before RAS,
Supply Current
(Battery Backup)
1
DOUT = enable
Average Power
Notes : 1.
2.
3.
4.
5.
mA
tRAS £ 1 ms
1, 4,
5
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CS = VIH.
VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
L-version.
5/17
¡ Semiconductor
MSM514102D/DL
AC Characteristics (1/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Parameter
MSM514102 MSM514102 MSM514102
D/DL-70
D/DL-60
D/DL-80
Symbol
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
110
—
130
—
150
—
ns
tRWC
130
—
155
—
175
—
ns
tSC
35
—
40
—
45
—
ns
tSRWC
60
—
70
—
80
—
ns
Access Time from RAS
tRAC
—
60
—
70
—
80
ns
Access Time from CS
tCAC
—
15
—
20
—
20
ns
4, 5
Access Time from Column Address
tAA
—
30
—
35
—
40
ns
4, 6, 7
tALW
—
55
—
65
—
75
ns
4, 7
Output Enable Time referenced to WE
tOW
—
15
—
20
—
20
ns
4
Output Low Impedance Time from CS
tCLZ
0
—
0
—
0
—
ns
4
Data Output Hold Time referenced to
Column Address
tAOH
5
—
5
—
5
—
ns
Data Output Hold Time from WE
tWOH
0
—
0
—
0
—
ns
CS to Data Output Buffer Turn-off Delay Time
tOFF
0
15
0
20
0
20
ns
8
3
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Static Column Mode Cycle Time
Static Column Mode Read Modify Write
Cycle Time
Access Time from Last Write
4, 5, 6
Transition Time
tT
3
50
3
50
3
50
ns
Refresh Period
tREF
—
16
—
16
—
16
ms
Refresh Period (L-version)
tREF
—
128
—
128
—
128
ms
RAS Precharge Time
tRP
40
—
50
—
60
—
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Static Column Mode)
tRASC
60
100,000
70
100,000
80
100,000
ns
RAS Hold Time
tRSH
15
—
20
—
20
—
ns
CS Precharge Time (Static Column Mode)
tCP
10
—
10
—
10
—
ns
CS Pulse Width
tCS
15
10,000
20
10,000
20
10,000
ns
CS Hold Time
tCSH
60
—
70
—
80
—
ns
CS to RAS Precharge Time
tCRP
5
—
5
—
5
—
ns
RAS to CS Delay Time
tRCD
20
45
20
50
20
60
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
15
40
ns
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
15
—
15
—
15
—
ns
Column Address Hold Time from RAS
(Write Cycle)
tAWR
50
—
55
—
60
—
ns
Column Address Hold Time from RAS
tAR
75
—
85
—
95
—
ns
Column Address to RAS Lead Time
tRAL
30
—
35
—
40
—
ns
Column Address Hold Time from RAS
Precharge
tAH
10
—
10
—
10
—
ns
6/17
¡ Semiconductor
MSM514102D/DL
AC Characteristics (2/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Parameter
Symbol
MSM514102 MSM514102 MSM514102
D/DL-60
D/DL-80
D/DL-70
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
tAHLW
55
—
65
—
75
—
Last Write to Column Address Delay Time tLWAD
Column Address Hold Time
ns
20
25
20
30
20
35
ns
tRCS
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
9
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
9
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
10
Write Command Hold Time
tWCH
10
—
10
—
15
—
ns
Write Command Hold Time from RAS
tWCR
45
—
50
—
60
—
ns
Write Command Pulse Width
tWP
10
—
10
—
15
—
ns
Write Invalid Time
tWI
10
—
10
—
10
—
ns
Read Command Set-up Time
7
Write Command Hold Time (DOUT Disable)
tWH
0
—
0
—
0
—
ns
Write Command to RAS Lead Time
tRWL
15
—
20
—
20
—
ns
Write Command to CS Lead Time
tCWL
15
—
20
—
20
—
ns
Data-in Set-up Time
tDS
0
—
0
—
0
—
ns
11
Data-in Hold Time
tDH
15
—
15
—
15
—
ns
11
Data-in Hold Time from RAS
tDHR
50
—
55
—
60
—
ns
CS to WE Delay Time
tCWD
15
—
20
—
20
—
ns
10
Column Address to WE Delay Time
tAWD
30
—
35
—
40
—
ns
10
RAS to WE Delay Time
tRWD
60
—
70
—
80
—
ns
10
CS Active Delay Time from RAS Precharge tRPC
10
—
10
—
10
—
ns
RAS to CS Set-up Time (CS before RAS)
tCSR
5
—
5
—
5
—
ns
RAS to CS Hold Time (CS before RAS)
tCHR
10
—
10
—
10
—
ns
WE to RAS Precharge Time (CS before RAS) tWRP
10
—
10
—
10
—
ns
WE Hold Time from RAS (CS before RAS)
tWRH
10
—
10
—
10
—
ns
RAS to WE Set-up Time (Test Mode)
tWTS
10
—
10
—
10
—
ns
RAS to WE Hold Time (Test Mode)
tWTH
10
—
10
—
10
—
ns
10
7/17
¡ Semiconductor
Notes:
MSM514102D/DL
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of
eight initialization cycles (RAS-only refresh or CS before RAS refresh) before proper
device operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. Operating within the tLWAD (Max.) limit ensures that tALW (Max.) can be met.
tLWAD (Max.) is specified as a reference point only. If tLWAD is greater than the
specified tLWAD (Max.) limit, then the access time is controlled by tAA.
8. tOFF (Max.) defines the time at which the output achieves the open circuit condition and
is not referenced to output voltage levels.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD and tAWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.)
and tAWD ≥ tAWD (Min.), then the cycle is a read modify write cycle and data out will
contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CS leading edge in an early write cycle, and
to the WE leading edge in a read modify write cycle.
12. The test mode is initiated by performing a WE and CS before RAS refresh cycle. This
mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, the data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
8/17
E2G0150-18-41U
,
,,
¡ Semiconductor
MSM514102D/DL
TIMING WAVEFORM
Read Cycle
tRC
tRP
RAS
tRAS
VIH –
VIL –
tCSH
tCRP
CS
tRCD
VIH –
VIL –
Address
tCS
tRAD
VIH –
VIL –
tAH
tRAL
tRAH
tASR
tCRP
tRSH
Row
Column
tAR
tRRH
tRCS
WE
VIH –
VIL –
tCAC
tAA
tOFF
tRAC
DOUT
VOH –
VOL –
tRCH
Valid Data
Open
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
RAS
VIH –
VIL –
tAWR
tCSH
tCRP
CS
VIH –
VIL –
tRCD
tRAH
Row
Column
tRAD
WE
VIH –
VIL –
tASC
tCAH
tWCR
tWCS
tWP
tDS
DIN
VIH –
VIL –
DOUT
VOH –
VOL –
tCRP
tRSH
tCS
VIH –
VIL –
tASR
Address
tRP
tRAS
tWH
tDH
Valid Data
tDHR
Open
"H" or "L"
9/17
,,
, ,
¡ Semiconductor
MSM514102D/DL
Read Modify Write Cycle
tRWC
tRP
RAS
tRAS
VIH –
VIL –
tCRP
CS
VIH –
VIL –
WE
tRAL
tRCS
tCS
VIH –
VIL –
tCWL
tRWL
tRAH
tCAH
Row
Column
tRWD
tWP
VIH –
VIL –
tCSH
tDH
tDS
DIN
VIH –
VIL –
Valid Data
tAA
tRAC
DOUT
tCRP
tCWD
tAWD
tASR
Address
tRCD
tRAD
VOH –
VOL –
tCAC
tWOH
tOFF
Valid Data
Open
tCLZ
"H" or "L"
Static Column Mode Read Cycle
tRP
RAS
CS
tRASC
VIH –
VIL –
tCP
tCS
VIH –
VIL –
tRCD
tASR
Address
VIH –
VIL –
tRAH
tSC
Row
VIH –
VIL –
VOH –
VOL –
tAR
tRCH
tCSH
tAOH
tCLZ
Column
tRRH
tRCH
tRCS
tAA
tAA
tAA
Valid
Data
tAH
tRAL
Column
tCAC
tRAC
DOUT
tSC
Column
tRAD
tRCS
WE
tCRP
tRSH
tCS
Valid
Data
tOFF
tCAC
tOFF
tCLZ
Valid
Data
"H" or "L"
10/17
¡ Semiconductor
MSM514102D/DL
,,,
Static Column Mode Write Cycle (Early Write)
tRP
RAS
tRASC
VIH –
VIL –
tRAD
CS
VIH –
VIL –
tRCD
tASR
Address
WE
VIH –
VIL –
tCAH
Row
Column
tAWR
tASC
tWCH
tWCS
VIH –
VIL –
Column
Column
tCAH
tASC
tCAH
tCWL
tWH
tWP
tWCS
tWI
tDS
DOUT
tCRP
tRAL
tRAH
tSC
tDS
DIN
tRSH
tCP
tASC
VIH –
VIL –
tDH
tDH
Valid Data
tDH
tDS
Valid
Data
Valid Data
tDHR
VOH –
VOL –
Open
"H" or "L"
Static Column Mode Read Modify Write Cycle
tRASC
RAS
CS
VIH –
VIL –
tRCS
VIH –
VIL –
WE
VIH –
VIL –
tAWD
tRAH
Row
tRWL
Column
tSRWC
tAWD
tWP
VIH –
VIL –
tDS
VIH –
VIL –
VOH –
VOL –
tRAL
Column
tRAD
tRWD
tDH
Valid
Data
tRAC
DOUT
tCWL
tLWAD
tCAH
tRCD
DIN
tCRP
tCWD
tASR
Address
tRP
tAA
tCAC
Valid
Data
tWOH
tALW
tCLZ
Valid Data
tAA
tOW
tOFF
Valid Data
"H" or "L"
11/17
,,
,
,
,
,
¡ Semiconductor
MSM514102D/DL
Static Column Mode Read/Write Mixed Cycle
RAS
VIH –
VIL – tRCD
tASC
CS
VIH –
VIL –
tRAD
tASR
Address
WE
VIH –
VIL –
VIH –
VIL –
tCP
tCS
tRAH
Row
Column
DOUT
VIH –
VIL –
Column
tCAH
tSC
tWCR
tWCS
tAWD
tWP
tLWAD
tDH
tDS
DIN
Column
tAWR
tDH
tDS
Valid Data
tDHR
Invalid Data
tCAC
tAA
VOH –
VOL –
Valid
Data
tAOH
tAA
Valid
Data
tALW
tWOH
Valid
Data
(Read/Write)
(Read)
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tRPC
tCRP
CS
VIH –
VIL –
tASR
Address
VIH –
VIL –
tRAH
Row
tOFF
DOUT
VOH –
VOL –
Open
Note: WE = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM514102D/DL
,,,
,,,
CS before RAS Refresh Cycle
tRC
tRP
RAS
tRAS
VIH –
VIL –
tRPC
tRPC
tCP
CS
WE
tCSR
tCHR
tWRP
tWRH
tCSR
VIH –
VIL –
tWRP
VIH –
VIL –
tOFF
DOUT
VOH –
VOL –
Open
Note : Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
RAS
VIH –
VIL –
tRCD
tCRP
CS
tRP
tRAS
tRSH
tCHR
tCRP
tAR
VIH –
VIL –
tRAH
tASR
tRAL
tRAD
Address
VIH –
VIL –
Row
Column
tRRH tWRP
tRCS
WE
VIH –
VIL –
VOH –
VOL –
tWRH
tCAC
tRAC
DOUT
tAH
tAA
tOFF
Valid Data
tCLZ
"H" or "L"
13/17
,,,
,
,
¡ Semiconductor
MSM514102D/DL
Hidden Refresh Write Cycle
tRC
tRC
tRAS
RAS
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
tRSH
tRCD
tCHR
Row
tASC
tCAH
Column
tWCS
tWH
tWRP
WE
VIH –
VIL –
DIN
VIH –
VIL –
tWRH
tDH
tDS
DOUT
tCRP
tRAH
tASR
tRAD
Address
tRAS
tAR
tCRP
CS
tRP
tRP
Valid Data
tDHR
VOH –
VOL –
Open
"H" or "L"
Test Mode Initiate Cycle
tRC
tRP
RAS
VIH –
VIL –
tRPC
tCP
CS
tRAS
tCSR
VIH –
VIL –
tWTS
WE
tCHR
tWTH
VIH –
VIL –
tOFF
DOUT
VOH –
VOL –
Open
Note: Address, DIN = "H" or "L"
"H" or "L"
14/17
¡ Semiconductor
MSM514102D/DL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/17
¡ Semiconductor
MSM514102D/DL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.50 TYP.
16/17
¡ Semiconductor
MSM514102D/DL
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
Similar pages