HUF75639S3R4851
Data Sheet
December 2001
56A, 115V, 0.025 Ohm, N-Channel
UltraFET Power MOSFET
This N-Channel power MOSFETs is manufactured using the
innovative UltraFET® process. This advanced process
technology achieves the lowest possible on-resistance per
silicon area, resulting in outstanding performance. This
device is capable of withstanding high energy in the
avalanche mode and the diode exhibits very low reverse
recovery time and stored charge. It was designed for use in
applications where power efficiency is important, such as
switching regulators, switching converters, motor drivers,
relay drivers, low-voltage bus switches, and power
management in portable and battery-operated products.
Features
• 56A, 115V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and Saber Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
Formerly developmental type TA75639.‘
• UIS Rating Curve
Ordering Information
PART NUMBER
HUF75639S3R4851
PACKAGE
TO-262AA
BRAND
R4851
NOTE: When ordering, use the entire part number.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Packaging
JEDEC TO-262AA
Symbol
D
SOURCE
DRAIN
GATE
G
S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
HUF75639S3R4851
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
115
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
115
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
56
Figure 4
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200
1.35
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
115
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 56A, VGS = 10V (Figure 9)
-
0.021
0.025
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
0.74
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-262
-
-
62
oC/W
VDD = 50V, ID ≅ 56A,
RL = 0.89Ω, VGS = 10V,
RGS = 5.1Ω
-
-
110
ns
-
15
-
ns
tr
-
60
-
ns
td(OFF)
-
20
-
ns
tf
-
25
-
ns
tOFF
-
-
70
ns
-
110
130
nC
-
57
75
nC
-
3.7
4.5
nC
SWITCHING SPECIFICATIONS
(VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
VDD = 50V,
ID ≅ 56A,
RL = 0.89Ω
Ig(REF) = 1.0mA
(Figure 13)
Gate to Source Gate Charge
Qgs
-
9.8
-
nC
Reverse Transfer Capacitance
Qgd
-
24
-
nC
-
2000
-
pF
-
500
-
pF
-
65
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
MIN
TYP
MAX
UNITS
ISD = 56A
-
-
1.25
V
trr
ISD = 56A, dISD/dt = 100A/µs
-
-
110
ns
QRR
ISD = 56A, dISD/dt = 100A/µs
-
-
320
nC
VSD
TEST CONDITIONS
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Typical Performance Curves
60
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
50
40
30
20
10
0
0
0
25
50
75
100
125
150
25
175
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
IDM , PEAK CURRENT (A)
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
100
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Typical Performance Curves
(Continued)
300
1000
IAS, AVALANCHE CURRENT (A)
ID , DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
VDSS(MAX) = 115V
10
100
100
STARTING TJ = 25οC
STARTING TJ = 150οC
10
0.001
1
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
200
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
100
100
80
VGS = 20V
VGS = 10V
VGS = 7V
60
40
VGS = 5V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
1
2
3
4
5
6
40
20
25oC
-55oC
0
0
7
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.5
3.0
4.5
6.0
7.5
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
3.0
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5 V
GS = 10V, ID = 56A
NORMALIZED GATE
VGS = VDS, ID = 250µA
2.0
1.5
1.0
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
175oC
60
0
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
80
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 6V
1.0
0.8
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
200
0.6
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Typical Performance Curves
(Continued)
3000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
ID = 250µA
2500
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
2000
CISS
1500
1000
COSS
500
CRSS
0.9
-80
0
-40
0
40
80
120
160
200
0
10
TJ , JUNCTION TEMPERATURE (oC)
20
30
40
50
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 56A
ID = 37A
ID = 18A
2
VDD = 50V
0
0
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
-
VGS
VDS
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VGS = 20V
VDS
VDD
RL
Qg(TOT)
VDS
VGS
Qg(10)
+
-
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
HUF75639S3R4851 Rev. B
HUF75639S3R4851
PSPICE Electrical Model
SUBCKT R4851 2 1 3 ;
rev 19 Oct. 99
CA 12 8 2.8e-9
CB 15 14 2.65e-9
CIN 6 8 1.9e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
DBREAK
+
RSLC2
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
RLGATE 1 9 10
RLDRAIN 2 5 20
RLSOURCE 3 7 4.69
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.3e-2
RGATE 9 20 0.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
+
50
-
IT 8 17 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 126
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 2e-9
LGATE 1 9 1e-9
LSOURCE 3 7 0.47e-9
DRAIN
2
5
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
-
+
8
22
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*115),4))}
.MODEL DBODYMOD D (IS = 1.4e-12 RS = 3.3e-3 XTI = 4.7 TRS1 = 2e-3 TRS2 = 0.1e-5 CJO = 3.3e-9 TT = 6.1e-8 M = 0.7)
.MODEL DBREAKMOD D (RS = 3.5e- 1TRS1 = 1e- 3TRS2 = 1e-6)
.MODEL DPLCAPMOD D (CJO = 2.2e- 9IS = 1e-3 0N = 10 M = 0.95 vj = 1.0)
.MODEL MMEDMOD NMOS (VTO = 3.5 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u Rg = 0.7)
.MODEL MSTROMOD NMOS (VTO = 3.97 KP = 56.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO =3.11 KP = 0.085 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 0.8e- 3TC2 = 1e-6)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1.75e-5)
.MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 14e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -2.0e-3 TC2 = -1.75e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.75e- 3TC2 = 0.05e-9)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.0 VOFF = -3.5)
VON = -3.5 VOFF = -6.0)
VON = -2.5 VOFF = 4.95)
VON = 4.95 VOFF = -2.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev. B
HUF75639S3R4851
SABER Electrical Model
nom temp=25 deg c 115v Ultrafet
REV 19 Oct. 99
template r4851 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.4e-12, xti=4.7, cjo=33e-10,tt=6.1e-8, m=0.7)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=22e-10,is=1e-30,n=10,m=0.95, vj=1.0)
m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.11,kp=0.085,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-6.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.5,voff=4.95)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=4.95,voff=-2.5)
LDRAIN
DPLCAP
10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
LGATE
72
ISCL
RDRAIN
6
8
EVTHRES
+ 19 8
EVTEMP
RGATE +
18 22
9
20
21
71
11
16
MWEAK
DBODY
6
EBREAK
+
17
18
MMED
MSTRO
CIN
i.it n8 n17 = 1
RDBODY
DBREAK
50
-
RLGATE
-
8
LSOURCE
SOURCE
3
7
RSOURCE
l.ldrain n2 n5 = 2.0e-9
l.lgate n1 n9 = 1e-9
l.lsource n3 n7 = 4.69e-10
RLSOURCE
S1A
12
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S2A
13
8
14
13
S1B
CA
res.rbreak n17 n18 = 1, tc1=0.8e-3,tc2=-1e-6
res.rdbody n71 n5 = 3.3e-3, tc1=2.0e-3, tc2=0.1e-5
res.rdbreak n72 n5 = 3.5e-1, tc1=1e-3, tc2=1e-6
res.rdrain n50 n16 = 13e-3, tc1=1e-2,tc2=1.75e-5
res.rgate n9 n20 = 0.7
res.rldrain n2 n5 = 20
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 4.69
res.rslc1 n5 n51 = 1e-6, tc1=2.8e-3,tc2=14e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4.5e-3, tc1=0,tc2=0
res.rvtemp n18 n19 = 1, tc1=-2.75e-3,tc2=0.05e-9
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1.75e-5
RDBREAK
RSLC2
+
GATE
1
RLDRAIN
RSLC1
51
ESG
c.ca n12 n8 = 28.5e-10
c.cb n15 n14 = 26.5e-10
c.cin n6 n8 = 19e-10
DRAIN
2
5
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 126
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/115))** 4))
}
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev. B
HUF75639S3R4851
Spice Thermal Model
TH
REV 19 Oct 1999
JUNCTION
R4851
CTHERM1 TH 6 5.0e-3
CTHERM2 6 5 1.9e-2
CTHERM3 5 4 7.95e-3
CTHERM4 4 3 9.0e-3
CTHERM5 3 2 2.95e-2
CTHERM6 2 TL 12.55
RTHERM1 TH 6 5.04e-3
RTHERM2 6 5 1.25e-2
RTHERM3 5 4 3.54e-2
RTHERM4 4 3 1.98e-1
RTHERM5 3 2 2.99e-1
RTHERM6 2 TL 3.97e-2
Saber Thermal Model
CTHERM1
RTHERM1
6
CTHERM2
RTHERM2
5
CTHERM3
RTHERM3
Saber thermal model R4851
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.9e-2
ctherm.ctherm3 5 4 = 7.95e-3
ctherm.ctherm4 4 3 = 9.0e-3
ctherm.ctherm5 3 2 = 2.95e-2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 5.04e-3
rtherm.rtherm2 6 5 = 1.25e-2
rtherm.rtherm3 5 4 = 3.54e-2
rtherm.rtherm4 4 3 = 1.98e-1
rtherm.rtherm5 3 2 = 2.99e-1
rtherm.rtherm6 2 tl = 3.97e-2
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
TL
©2001 Fairchild Semiconductor Corporation
CASE
HUF75639S3R4851 Rev. B
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Rev. H4