Central CMLDM8002AJ Surface mount silicon dual p-channel enhancement-mode mosfet Datasheet

CMLDM8002A
CMLDM8002AG*
CMLDM8002AJ
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFETS
SOT-563 CASE
w w w. c e n t r a l s e m i . c o m
DESCRIPTION:
These CENTRAL SEMICONDUCTOR devices are
dual chip P-Channel enhancement-mode MOSFETs,
manufactured by the P-Channel DMOS Process,
designed for high speed pulsed amplifier and driver
applications. The CMLDM8002A utilizes the USA
pinout configuration, while the CMLDM8002AJ, utilizing
the Japanese pinout configuration, is available as a
special order. These special dual dransistor devices
offer low rDS(on) and low VDS(on).
* Device is Halogen Free by design
MARKING CODES: CMLDM8002A:
C08
CMLDM8002AG*: CG8
CMLDM8002AJ: CJ8
APPLICATIONS:
FEATURES:
• Load/Power Switches
• Power Supply Converter Circuits
• Battery Powered Portable Equipment
•
•
•
•
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Source Current (Body Diode)
Maximum Pulsed Drain Current
Maximum Pulsed Source Current
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
SYMBOL
VDS
VDG
VGS
ID
IS
IDM
ISM
PD
PD
PD
TJ, Tstg
ΘJA
Dual Chip Device
Low rDS(on)
Low VDS(on)
Low Threshold Voltage
• Fast Switching
• Logic Level Compatible
• Small SOT-563 package
50
50
20
280
280
1.5
1.5
350
300
150
-65 to +150
357
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
IGSSF, IGSSR
VGS=20V, VDS=0
100
IDSS
VDS=50V, VGS=0
1.0
IDSS
VDS=50V, VGS=0, TJ=125°C
500
ID(ON)
VGS=10V, VDS=10V
500
BVDSS
VGS=0, ID=10μA
50
VGS(th)
VDS=VGS, ID=250μA
1.0
2.5
VDS(ON)
VGS=10V, ID=500mA
1.5
VDS(ON)
VGS=5.0V, ID=50mA
0.15
VSD
VGS=0, IS=115mA
1.3
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2
UNITS
V
V
V
mA
mA
A
A
mW
mW
mW
°C
°C/W
UNITS
nA
μA
μA
mA
V
V
V
V
V
R7 (8-June 2015)
CMLDM8002A
CMLDM8002AG*
CMLDM8002AJ
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFETS
ELECTRICAL
SYMBOL
rDS(ON)
rDS(ON)
rDS(ON)
rDS(ON)
gFS
Crss
Ciss
Coss
Qg(tot)
Qgs
Qgd
ton, toff
CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VGS=10V, ID=500mA
2.5
Ω
VGS=10V, ID=500mA, TJ=125°C
4.0
Ω
VGS=5.0V, ID=50mA
3.0
Ω
VGS=5.0V, ID=50mA, TJ=125°C
5.0
Ω
VDS =10V, ID=200mA
200
mS
VDS=25V, VGS=0, f=1.0MHz
7.0
pF
VDS=25V, VGS=0, f=1.0MHz
70
pF
VDS=25V, VGS=0, f=1.0MHz
15
pF
VDS=25V, VGS=4.5V, ID=100mA
0.72
nC
VDS=25V, VGS=4.5V, ID=100mA
0.25
nC
VDS=25V, VGS=4.5V, ID=100mA
0.16
nC
VDD=30V, VGS=10V, ID=200mA
RG=25Ω, RL=150Ω
20
ns
SOT-563 CASE - MECHANICAL OUTLINE
CMLDM8002A (USA Pinout)
CMLDM8002AG*
CMLDM8002AJ (Japanese Pinout)
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODES:
CMLDM8002A: C08
CMLDM8002AG*: CG8
MARKING CODE: CJ8
* Device is Halogen Free by design
R7 (8-June 2015)
w w w. c e n t r a l s e m i . c o m
CMLDM8002A
CMLDM8002AG*
CMLDM8002AJ
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFETS
TYPICAL ELECTRICAL CHARACTERISTICS
R7 (8-June 2015)
w w w. c e n t r a l s e m i . c o m
CMLDM8002A
CMLDM8002AG*
CMLDM8002AJ
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFETS
SERVICES
• Bonded Inventory
• Custom Electrical Screening
• Custom Electrical Characteristic Curves
• SPICE Models
• Custom Packaging
• Package Base Options
• Custom Device Development / Multi Discrete Modules (MDM™)
• Bare Die Available for Hybrid Applications
LIMITATIONS AND DAMAGES DISCLAIMER: In no event shall Central be liable for any collateral, indirect,
punitive, incidental, consequential, or exemplary damages in connection with or arising out of a purchase order
or contract or the use of products provided hereunder, regardless of whether Central has been advised of
the possibility of such damages. Excluded damages shall include, but not be restricted to: cost of removal or
reinstallation, rework, ancillary costs to the procurement of substitute products, loss of profits, loss of savings, loss
of use, loss of data, or business interruption. No claim, suit, or action shall be brought against Central more than
two (2) years after the related cause of action has occurred.
In no event shall Central’s aggregate liability from any warranty, indemnity, or other obligation arising out of or in
connection with a purchase order or contract, or any use of any Central product provided hereunder, exceed the
total amount paid to Central for the specific products sold under a purchase order or contract with respect to which
losses or damages are claimed. The existence of more than one (1) claim against the specific products sold to
Buyer under a purchase order or contract shall not enlarge or extend this limit.
Buyer understands and agrees that the foregoing liability limitations are essential elements of a purchase order
or contract and that in the absence of such limitations, the material and economic terms of the purchase order or
contract would be substantially different.
R7 (8-June 2015)
w w w. c e n t r a l s e m i . c o m
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