LATTICE PALCE20V8H

COM'L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
◆ Pin and function compatible with all PAL® 20V8 devices
◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability
◆ High-speed CMOS technology
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— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for a wide range of 24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
Programmable output polarity
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
Publication# 16491
Amendment/0
Rev: E
Issue Date: November 1998
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
I1 – I10
CLK/I0
10
Programmable AND Array
40 x 64
Input
Mux.
OE/I11 I12
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MC0
MC1
MC2
MC3
MC4
MC5
MC6
MC7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Input
Mux.
I13
16491E
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells
(MC0-MC7). Each macrocell can be configured as a registered output, combinatorial output,
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a fixed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically configured from the user’s
design specification, which can be in a number of formats. The design specification is processed
2
PALCE20V8 Family
by development software to verify the design and create a programming file. This file, once
downloaded to a programmer, configures the device according to the user’s desired function.
The user is given two design options with the PALCE20V8. First, it can be programmed as an
emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL
devices. The PAL device programmer manufacturer will supply device codes for the standard
PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8
to the corresponding PAL device architecture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to them. Alternatively, the device can be
programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This
option provides full utilization of the macrocells, allowing non-standard architectures to be built.
11
OE
0X
10
VCC
To
Adjacent
Macrocell
11
10
00
01
SL0X
SG1
11
0X
D
SL1X
CLK
Q
I/OX
10
Q
10
11
0X
*SG1
SL0X
From
Adjacent
Pin
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
16491E
Figure 1. PALCE20V8 Macrocell
PALCE20V8 Family
3
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, the buffer is always
disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent
I/O.
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction
with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low
or active high.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0
and MC7, SG0 replaces SG1 on the feedback multiplexer.
These configurations are summarized in Table 1 and illustrated in Figure 2.
If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be
used as data inputs.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flipflop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is
loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The
output buffer is enabled by OE.
Combinatorial Configurations
The PALCE20V8 has three combinatorial output configurations: dedicated output in a nonregistered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note:
1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.
4
PALCE20V8 Family
Dedicated Input in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The
feedback signal is an adjacent I/O pin.
Combinatorial I/O in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Table 1. Macrocell Configuration
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
SG0
SG1
Device Uses Registers
SL0X
Cell
Configuration
Devices
Emulated
Device Uses No Registers
0
1
0
Registered Output
PAL20R8, 20R6,
20R4
1
0
0
Combinatorial
Output
PAL20L2, 18L4,
16L6, 14L8
0
1
1
Combinatorial
I/O
PAL20R6, 20R4
1
0
1
Input
PAL20L2, 18L4, 16L6
1
1
1
Combinatorial
I/O
PAL20L8
PALCE20V8 Family
5
OE
OE
D
CLK
Q
D
Q
CLK
Q
Q
b. Registered active high
a. Registered active Low
c. Combinatorial I/O active low
d. Combinatorial I/O active high
VCC
VCC
Note 1
e. Combinatorial output active low
Note 1
f. Combinatorial output active high
Note 2
Notes:
1. Feedback is not available on pins 18 (21) and 19 (23) in
the combinatorial output mode.
2. This macrocell configuration is not available on pins
18 (21) and 19 (23).
Adjacent I/O Pin
g. Dedicated input
16491E
Figure 2. Macrocell Configurations
6
PALCE20V8 Family
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is
selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.
Security Bit
A security bit is provided on the PALCE20V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of
programmable memory that can contain any user-defined data. The signature data is always
available to the user independent of the security bit.
Programming and Erasing
The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE20V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
and post-programming functional yields in the industry.
Technology
The high-speed PALCE20V8H is fabricated with Vantis’ advanced electrically erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.
PCI Compliance
PALCE20V8H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus
Specification published by the PCI Special Interest Group. The PALCE20V8H’s predictable timing
ensures compliance with the PCI AC specifications independent of the design. On the other
hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent
upon routing and product term distribution.
PALCE20V8 Family
7
LOGIC DIAGRAM
0
3 4
7 8
11 12
15 16 19 20
23 24 27 28
31 32 35 36 39
24
VCC
(28)
CLK/I0 1
(2)
23
(27)
1
0
I1 2
(3)
SG0
11
VCC
0X
10
I 13
11
10
00
01
SL0 7
0
SG1
11
0X
D
7
Q
22 I/O7
(26)
10
Q
10
11
0X
I2 3
(4)
SG0
11
VCC
0X
10
SL07
11
10
00
01
SL06
8
SG1
11
0X
D
15
Q
21 I/O6
(25)
10
Q
10
11
0X
I3 4
(5)
SG1
11
VCC
0X
10
SL06
11
10
00
01
SL05
16
SG1
11
0X
D
23
Q
20 I/O5
(24)
10
Q
10
11
0X
I4 5
(6)
SG1
11
VCC
0X
10
SL05
11
10
00
01
SL04
24
SG1
11
0X
D
Q
19 I/O4
(23)
10
Q
31
10
11
0X
I5 6
(7)
SG1
0
3 4
7 8
11 12 15 16 19 20 23 24 27 28
31 32 35 36 39
SL04
CLK OE
16491E
8
PALCE20V8 Family
LOGIC DIAGRAM (CONTINUED)
0
3 4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
CLK OE
11
VCC
0X
10
11
10
00
01
SL03
32
SG1
11
0X
D
39
Q
18 I/O3
(21)
10
Q
10
11
0X
I6 7
(9)
SG1
11
VCC
0X
10
SL0 3
11
10
00
01
SL02
40
SG1
11
0X
D
47
Q
17 I/O2
(20)
10
Q
10
11
0X
I7 8
(10)
SG1
11
VCC
0X
10
SL02
11
10
00
01
SL01
48
SG1
11
0X
D
55
Q
16 I/O 1
(19)
10
Q
10
11
0X
I8 9
(11)
SL01
SG1
11
VCC
0X
10
11
10
00
01
SL00
56
SG1
11
0X
D
63
Q
15 I/O0
(18)
10
Q
10
11
0X
I 9 10
(12)
SG0
0
1
10 11
(13)
SG0
SL00
14 I12
(17)
13 OE/I11
(16)
0
3 4
7 8
11 12 15 16 19 20
23 24 27 28 31 32
35 36
39
16491E-4
(concluded)
PALCE20V8 Family
9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min
VOL
Output LOW Voltage
IOL = 24 mA, VIN = VIH or VIL, VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100
µA
IOZH
Off-State Output Leakage Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–150
mA
ICC
(Static)
Supply Current for -5
Outputs Open (IOUT = 0 mA), VIN = 0 V
VCC = Max
125
mA
ICC
(Dynamic)
Supply Current for -7 and -10
Outputs Open (IOUT = 0 mA),
VCC = Max, f = 25 MHz
115
mA
2.4
V
0.5
2.0
–30
V
V
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
10
PALCE20V8H-5/7/10 (Com’l)
CAPACITANCE
Parameter
Symbol
1
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN = 2.0 V
COUT
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
1
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
-5
Parameter
Symbol
Parameter Description
-7
-10
Min2
Max
Min2
Max
Min2
Max
Unit
5
3
7.5
3
10
ns
tPD
Input or Feedback to Combinatorial Output
1
tS
Setup Time from Input or Feedback to Clock
3
5
7.5
ns
tH
Hold Time
0
0
0
ns
tCO
Clock to Output
1
tSKEWR
Skew Between Registered Outputs (Note 3)
tWL
1
1
5
3
1
7.5
ns
1
ns
LOW
3
4
6
ns
HIGH
3
4
6
ns
142.8
100
66.7
MHz
Clock Width
tWH
fMAX
4
Maximum
Frequency
(Note 4)
External Feedback
1/(tS+tCO)
Internal Feedback
(fCNT)
1/(tS+tCF) (Note 5)
166
125
71.4
MHz
No Feedback
1/(tWH+tWL)
166
125
83.3
MHz
tPZX
OE to Output Enable
1
6
1
6
2
10
ns
tPXZ
OE to Output Disable
1
5
1
6
2
10
ns
tEA
Input to Output Enable Using Product Term Control
2
6
3
9
3
10
ns
tER
Input to Output Disable Using Product Term Control
2
5
3
9
3
10
ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE20V8H-5/7/10 (Com’l)
11
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min
VOL
Output LOW Voltage
IOL = 24 mA, VIN = VIH or VIL, VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100
µA
IOZH
Off-State Output Leakage Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–150
mA
ICC
(Dynamic)
Supply Current for -10
Outputs Open (IOUT = 0 mA),
VCC = Max, f = 15 MHz (Note 4)
55
mA
2.4
V
0.5
2.0
–30
V
V
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is guaranteed worst case under test conditions. Refer to the ICC vs. frequency graph for typical measurements.
12
PALCE20V8Q-10 (Com’l)
CAPACITANCE
Parameter
Symbol
1
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN = 2.0 V
COUT
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
1
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
-10
Parameter
Symbol
Parameter Description
Min2
Max
Unit
10
ns
tPD
Input or Feedback to Combinatorial Output
3
tS
Setup Time from Input or Feedback to Clock
7.5
ns
tH
Hold Time
0
ns
tCO
Clock to Output
3
tWL
ns
LOW
6
ns
HIGH
6
ns
1/(tS+tCO)
66.7
MHz
1/(tS+tCF) (Note 4)
71.4
MHz
1/(tWH+tWL)
83.3
MHz
Clock Width
tWH
fMAX
7.5
External Feedback
Maximum Frequency
Internal Feedback (fCNT)
(Note 3)
No Feedback
tPZX
OE to Output Enable
2
10
ns
tPXZ
OE to Output Disable
2
10
ns
tEA
Input to Output Enable Using Product Term Control
3
10
ns
tER
Input to Output Disable Using Product Term Control
3
10
ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE20V8Q-10 (Com’l)
13
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min
VOL
Output LOW Voltage
IOL = 24 mA, VIN = VIH or VIL, VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100
µA
IOZH
Off-State Output Leakage Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–150
mA
ICC
Supply Current
Outputs Open (IOUT = 0 mA),
VCC = Max, f = 15 MHz
2.4
V
0.5
2.0
–30
V
V
H
90
Q
55
mA
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
14
PALCE20V8H-15/25 Q-15/25 (Com’l)
CAPACITANCE
Parameter
Symbol
1
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN = 2.0 V
COUT
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
1
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
-15
Parameter
Symbol
Parameter Description
Min
-25
Max
Min
Max
Unit
25
ns
tPD
Input or Feedback to Combinatorial Output
tS
Setup Time from Input or Feedback to Clock
12
15
ns
tH
Hold Time
0
0
ns
tCO
Clock to Output
tWL
10
12
ns
LOW
8
12
ns
HIGH
8
12
ns
45.5
37
MHz
50
40
MHz
62.5
41.6
MHz
Clock Width
tWH
fMAX
15
Maximum
Frequency
(Note 2)
External Feedback
1/(tS+tCO)
Internal Feedback (fCNT)
1/(tS+tCF) (Note 3)
No Feedback
1/(tWH+tWL)
tPZX
OE to Output Enable
15
20
ns
tPXZ
OE to Output Disable
15
20
ns
tEA
Input to Output Enable Using Product Term Control
15
25
ns
tER
Input to Output Disable Using Product Term Control
15
25
ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE20V8H-15/25 Q-15/25 (Com’l)
15
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min
VOL
Output LOW Voltage
IOL = 24 mA, VIN = VIH or VIL, VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.5 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100
µA
IOZH
Off-State Output Leakage Current HIGH
VOUT = 5.5 V, VCC = Max , VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage Current LOW
VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–150
mA
ICC
Supply Current
Outputs Open (IOUT = 0 mA),
VCC = Max, f = 15 MHz
2.4
V
0.5
2.0
–30
V
V
H
130
Q
65
mA
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
16
PALCE20V8H-15/25 Q-20/25 (ind)
CAPACITANCE
Parameter
Symbol
1
Parameter Description
Test Conditions
CIN
Input Capacitance
VIN = 2.0 V
COUT
Output Capacitance
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
Typ
Unit
5
pF
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
-15
Parameter
Symbol
Parameter Description
Min
-20
Max
Min
1
-25
Max
Min
Max
Unit
25
ns
tPD
Input or Feedback to Combinatorial Output
tS
Setup Time from Input or Feedback to Clock
12
13
15
ns
tH
Hold Time
0
0
0
ns
tCO
Clock to Output
tWL
20
10
11
12
ns
LOW
8
10
12
ns
HIGH
8
10
12
ns
45.5
41.6
37
MHz
50
45.4
40
MHz
62.5
50.0
41.6
MHz
Clock Width
tWH
fMAX
15
Maximum
Frequency
(Note 2)
External Feedback
1/(tS+tCO)
Internal Feedback
(fCNT)
1/(tS+tCF) (Note 3)
No Feedback
1/(tWH+tWL)
tPZX
OE to Output Enable
15
18
20
ns
tPXZ
OE to Output Disable
15
18
20
ns
tEA
Input to Output Enable Using Product Term Control
15
18
25
ns
tER
Input to Output Disable Using Product Term Control
15
18
25
ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE20V8H-15/25 Q-20/25 (ind)
17
SWITCHING WAVEFORMS
Input or
Feedback
Input or
Feedback
VT
VT
tS
tPD
tH
VT
Combinatorial
Output
Clock
VT
tCO
Registered
Output
VT
16491E-5
16491E-6
b. Registered output
a. Combinatorial output
VT
Input
tWH
tER
Clock
VT
tEA
VOH – 0.5V
Output
VT
VOL + 0.5V
tWL
16491E-8
16491E-7
c. Clock width
d. Input to output disable/enable
VT
OE
tPXZ
tPZX
VOH – 0.5V
Output
VOL + 0.5V
e. OE to output disable/enable
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
18
PALCE20V8 Family
VT
16491E-9
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
R2
CL
16491E-10
Commercial
Specification
tPD, tCO
tPZX, tEA
tPXZ, tER
S1
CL
R1
R2
Closed
Z → H: Open
1.5 V
L → Z: Closed
390 Ω
50 pF
Z → L: Closed
H → Z: Open
Measured Output Value
200 Ω
5 pF
PALCE20V8 Family
H-5: 200 Ω
1.5 V
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
19
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
150
20V8H-5
125
100
ICC (mA)
20V8H-7
75
20V8H-10
20V8H-15/25
50
20V8Q-15/25
25
0
0
10
20
30
Frequency (MHz)
40
50
16491E-11
ICC vs. Frequency
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
20
PALCE20V8 Family
ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
Symbol
Parameter
tDR
Min Pattern Data Retention Time
N
Max Reprogramming Cycles
Test Conditions
Value
Unit
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
Normal Programming Conditions
100
Cycles
ROBUSTNESS FEATURES
The PALCE20V8X-X/5 have some unique features that make them extremely robust, especially
when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins
cause unconnected pins to default to a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely insensitive to any positive overshoot
that has a pulse width of less than about 100 ns for the /5 versions.
PALCE20V8 Family
21
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE20V8H-7
AND PALCE20V8H-5
VCC
VCC
> 50 kΩ
ESD
Protection
and
Clamping
Programming
Pins only
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Typical Input
VCC
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload
Circuitry
Feedback
Input
16491E-12
Typical Output
Device
Rev Letter
PALCE20V8H-7
A
PALCE20V8H-5
A
22
PALCE20V8 Family
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /4 VERSIONS
VCC
100 kΩ
VCC
0.5 kW
ESD
Protection
Input
VCC
VCC
100 kΩ
0.5 kΩ
16491E-13
Preload
Circuitry
Feedback
Input
I/O
Topside Marking:
Device
Rev Letter
PALCE20V8H-10
M
PALCE20V8H-15
L, M
PALCE20V8H-15
M
PALCE20V8H--25
M
PALCE20V8H-25
M
Lattice/Vantis CMOS PLDs are marked on top of the
package in the following manner:
PALCEXXX
Datecode (3 numbers) Lot ID (4 characters)––(Rev Letter)
The Lot ID and Rev Letter are separated by two spaces.
PALCE20V8 Family
23
POWER-UP RESET
The PALCE20V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways VCC can rise to its steady state, two conditions are required to ensure a valid
power-up reset. These conditions are:
◆ The VCC rise must be monotonic.
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
◆
Parameter Symbol
Parameter Descriptions
tPR
Power-Up Reset Time
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
Min
Max
Unit
1000
ns
See Switching Characteristics
VCC
4V
Power
tPR
Registered
Output
tS
Clock
tWL
Figure 2. Power-Up Reset Waveform
24
PALCE20V8 Family
16491E-15
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
PDID
PLCC
Unit
θjc
Thermal impedance, junction to case
19
19
°C/W
θj a
Thermal impedance, junction to ambient
73
55
°C/W
200 lfpm air
61
45
°C/W
400 lfpm air
53
41
°C/W
600 lfpm air
50
38
°C/W
800 lfpm air
47
36
°C/W
θj m a
Thermal impedance, junction to ambient with air flow
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE20V8 Family
25
CONNECTION DIAGRAMS
Top View
23
I13
I2
3
22
I/O7
I3
4
21
I/O6
I4
5
20
I5
6
I6
2
1
28 27 26
5
25
I/O6
I/O5
I4
6
24
I/O5
19
I/O4
I5
7
23
I/O4
7
18
I/O3
NC
8
22
GND/NC *
I7
8
17
I/O2
I6
9
21
I/O3
I8
9
16
I/O1
20
10
15
I/O0
I7
10
I9
I/O2
I10
11
14
I12
I8
11
19
I/O1
GND
12
13
OE/I11
= Clock
NC
= No Connect
GND = Ground
OE
= Output Enable
I
= Input
VCC
= Supply Voltage
I/O
= Input/Output
PALCE20V8 Family
I/O0
16491E-17
I12
OE/I11
NC
GND
I10
16491E-16
I9
12 13 14 15 16 17 18
PIN DESIGNATIONS
26
3
I3
Note:
Pin 1 is marked for orientation.
CLK
4
I/O7
2
I13
I1
VCC
VCC
PLCC
NC
24
CLK/I0
1
I1
CLK/I0
I2
SKINNYDIP
ORDERING INFORMATION
Commercial and Industrial Products
Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options.
The order number (Valid Combination) is formed by a combination of:
PAL
CE
20 V 8 H -5 J C /5
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4 = First Revision
/5 = Second Revision
(Same Algorithm as /4)
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF FLIP-FLOPS
OR OUTPUTS
OPERATING CONDITIONS
C
= Commercial (0°C to +75°C)
I
= Industrial (-40°C to +85°C)
POWER
H = Half Power (90–125 mA ICC)
Q = Quarter Power (55 mA ICC)
PACKAGE TYPE
P
= 24-Pin 300 mil Plastic SKINNY
DIP (PD3024)
J
= 28-Pin Plastic Leaded Chip
Carrier (PL 028)
SPEED
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
Valid Combinations
PALCE20V8H-5
JC
/5
PALCE20V8H-7
PC, JC
PALCE20V8H-10
/4
PALCE20V8H-15
PC, JC, PI, JI
PALCE20V8Q-15
PC, JC
PALCE20V8Q-20
PI, JI
/4
PALCE20V8H-25
PC, JC, PI, JI
PALCE20V8Q-25
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office
to confirm availability of specific valid combinations and to check on newly released combinations.
PALCE20V8 Family
27