PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25 PALCE22V10Z COM'L: -25 IND: -15/25 PALCE22V10 and PALCE22V10Z Families 24-Pin EE CMOS (Zero Power) Versatile PAL Device DISTINCTIVE CHARACTERISTICS ◆ As fast as 5-ns propagation delay and 142.8 MHz fMAX (external) ◆ Low-power EE CMOS ◆ 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs ◆ Varied product term distribution allows up to 16 product terms per output for complex ◆ ◆ ◆ ◆ ◆ ◆ functions Peripheral Component Interconnect (PCI) compliant (-5/-7/-10) Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability Extensive third-party software and programmer support 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC 5-ns and 7.5-ns versions utilize split leadframes for improved performance GENERAL DESCRIPTION The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z is an advanced PAL® device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell. Publication# 16564 Amendment/0 Rev: E Issue Date: November 1998 BLOCK DIAGRAM I1 - I11 CLK/I0 1 11 PROGRAMMABLE AND ARRAY (44 x 132) RESET 8 10 12 14 16 16 14 12 10 OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL 8 OUTPUT LOGIC MACRO CELL PRESET I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 FUNCTIONAL DESCRIPTION The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming EE cells to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product term disable. Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations registered output or combinatorial I/O, active high or active low (see Figure 1). The configuration choice is made according to the user’s design specification and corresponding programming of the configuration bits S0 - S1. Multiplexer controls are connected to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path. The device is produced with an EE cell link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easilyimplemented programming algorithm, these products can be rapidly programmed to any customized pattern. 2 PALCE22V10 and PALCE22V10Z Families Variable Input/Output Pin Ratio The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. 1 1 0 0 AR D Q Q CLK 0 1 0 1 I/On S1 S0 0 0 Registered/Active Low 0 1 Registered/Active High 0 1 0 Combinatorial/Active Low 1 1 1 Combinatorial/Active High SP S1 S0 Output Configuration 0 = Programmed EE bit 1 = Erased (charged) EE bit 16564E-004 Figure 1. Output Logic Macrocell Diagram Registered Output Configuration Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. Combinatorial I/O Configuration Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin. PALCE22V10 and PALCE22V10Z Families 3 S0 = 0 S1 = 0 AR D S0 = 0 S1 = 1 Q Q CLK SP b. Combinatorial/active low a. Registered/active low AR D S0 = 1 S1 = 1 S0 = 1 S1 = 0 Q Q CLK SP d. Combinatorial/active high c. Registered/active high 16564E-005 Figure 2. Macrocell Configuration Options Programmable Three-State Outputs Each output has a three-state output buffer with three-state control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as a dedicated input if the buffer is always disabled. Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high (S0 = 1). Preset/Reset For initialization, the PALCE22V10 has preset and reset product terms. These terms are connected to all registered outputs. When the synchronous preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the asynchronous reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. 4 PALCE22V10 and PALCE22V10Z Families Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE22V10 will depend on the programmed output polarity. The VCC rise must be monotonic, and the reset delay time is 1000ns maximum. Register Preload The register on the PALCE22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit After programming and verification, a PALCE22V10 design can be secured by programming the security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security bit is programmed, the array will read as if every bit is erased, and preload will be disabled. The bit can only be erased in conjunction with erasure of the entire pattern. Programming and Erasing The PALCE22V10 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE22V10 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE22V10 is fabricated with Vantis’ advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance The PALCE22V10H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE22V10H’s predictable timing ensures compliance with the PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCE22V10Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALCE22V10Z will go into standby mode, shutting down PALCE22V10 and PALCE22V10Z Families 5 most of its internal circuitry. The current will go to almost zero (ICC < 30 µA). The outputs will maintain the states held before the device went into the standby mode. When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. This saving is illustrated in the ICC vs. frequency graph. Product-Term Disable On a programmed PALCE22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the ICC vs. frequency graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs. 6 PALCE22V10 and PALCE22V10Z Families LOGIC DIAGRAM CLK/I 0 1 (2) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 24 (28) VCC 43 AR 0 1 1 D AR 9 Q Q 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 23 I/O 9 (27) SP 0 1 10 D AR Q 20 Q 22 I/O 8 (26) SP I1 0 1 2 (3) 21 D AR Q Q 33 I2 3 (4) 21 I/O 7 (25) SP 0 1 34 D AR Q Q 20 I/O 6 (24) SP 48 I3 4 (5) 0 1 49 D AR Q Q 19 I/O 5 (23) SP 65 I4 5 (6) 0 1 66 D AR Q Q 18 I/O 4 (21) SP 82 I5 6 (7) 0 1 83 D AR Q Q 17 I/O 3 (20) SP 97 I6 7 (9) 0 1 98 D AR Q Q SP 110 I7 8 (10) 0 1 111 D AR Q Q 121 I8 9 (11) 16 I/O 2 (19) 15 I/O 1 (18) SP 0 1 122 D AR Q 130 Q 14 I/O 0 (17) SP I9 10 (12) I 11 (13) 10 0 1 SP 131 13 GND I11 (16) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 12 (14) 16564E-006 PALCE22V10 and PALCE22V10Z Families 7 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 1.0 V DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 1.0 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC (Static) Supply Current ICC (Dynamic) Supply Current Min Max 2.4 Unit V 0.4 2.0 V V 0.8 V 10 µA -100 µA 10 µA -100 µA -130 mA Outputs Open, (IOUT = 0 mA), VCC = Max 125 mA Outputs Open, (IOUT = 0 mA), VCC = Max, f = 25 MHz 140 mA -30 Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 8 PALCE22V10H-5 (Com’l) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ VCC = 5.0 V TA = 25°C f = 1 MHz Unit 5 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -5 Parameter Symbol Parameter Description Min Max Unit 5 ns tPD Input or Feedback to Combinatorial Output tS1 Setup Time from Input or Feedback 3 ns tS2 Setup Time from SP to Clock 4 ns 0 tH Hold Time tCO Clock to Output tSKEWR tAR ns 4 ns Skew Between Registered Outputs (Note 2) 0.5 ns Asynchronous Reset to Registered Output 7.5 ns tARW Asynchronous Reset Width 4.5 ns tARR Asynchronous Reset Recovery Time 4.5 ns tSPR Synchronous Preset Recovery Time 4.5 ns 2.5 ns tWL tWH Clock Width LOW HIGH External Feedback fMAX Maximum Frequency (Note 3) Internal Feedback (fCNT) 1/(tS + tCO) 1/(tS + tCF) (Note 4) No Feedback 1/(tWH + tWL) 2.5 ns 142.8 MHz 150 MHz 200 MHz tEA Input to Output Enable Using Product Term Control 6 ns tER Input to Output Disable Using Product Term Control 5.5 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. Skew is measured with all outputs switching in the same direction. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10H-5 (Com’l) 9 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 1.0 V DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 1.0 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Symbol Parameter Description Test Conditions VOH Output HIGH Voltage VOL Output LOW Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH IOZL Min Max 2.4 V 0.4 2.0 Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) Unit V V 0.8 V 10 µA -100 µA VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) -100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max TA = 25°C (Note 3) -130 mA ICC (Static) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max 115 mA ICC (Dynamic) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max, f = 25 MHz 140 mA -30 Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 10 PALCE22V10H-7 (Com’l) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -7 PDIP Parameter Symbol Parameter Description PLCC Min Max Min Max Unit 7.5 3 7.5 ns tPD Input or Feedback to Combinatorial Output 3 tS1 Setup Time from Input or Feedback 5 tS2 Setup Time from SP to Clock 6 6 ns tH Hold Time 0 0 ns tCO Clock to Output 2 tSKEWR Skew Between Registered Outputs (Note 2) tAR Asynchronous Reset to Registered Output tARW Asynchronous Reset Width 7 7 ns tARR Asynchronous Reset Recovery Time 7 7 ns tSPR Synchronous Preset Recovery Time 7 7 ns LOW 3.5 3.0 ns HIGH 3.5 3.0 ns tWL tWH fMAX Clock Width Maximum Frequency (Note 3) 4.5 5 2 1 10 ns 4.5 ns 1 ns 10 ns External Feedback 1/(tS + tCO) 100 111 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) 125 133 MHz No Feedback 1/(tWH + tWL) 142.8 166 MHz tEA Input to Output Enable Using Product Term Control 7.5 7.5 ns tER Input to Output Disable Using Product Term Control 7.5 7.5 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. Skew is measured with all outputs switching in the same direction. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10H-7 (Com’l) 11 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 1.0 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 1.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Test Conditions Min 2.4 Output LOW Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max TA = 25°C (Note 3) ICC (Dynamic) Supply Current Outputs Open , (IOUT = 0 mA), VCC = Max, f = 25 MHz Max V 0.4 -30 Unit V V 0.8 V 10 µA -100 µA 10 µA -100 µA -130 mA 120 mA Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 12 PALCE22V10H-10 (Com’l) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -10 Parameter Symbol Parameter Description Min Max Unit 10 ns tPD Input or Feedback to Combinatorial Output tS1 Setup Time from Input or Feedback 6 ns tS2 Setup Time from SP to Clock 7 ns tH Hold Time 0 tCO Clock to Output 6 ns tAR Asynchronous Reset to Registered Output 13 ns tARW Asynchronous Reset Width 8 ns tARR Asynchronous Reset Recovery Time 8 ns tSPR Synchronous Preset Recovery Time 8 ns LOW 4 ns HIGH 4 ns tWL tWH fMAX Clock Width Maximum Frequency (Note 2) External Feedback ns 1/(tS + tCO) 1/(tS + tCF) (Note 3) 83.3 MHz Internal Feedback (fCNT) 110 MHz No Feedback 1/(tWH + tWL) 125 MHz tEA Input to Output Enable Using Product Term Control 10 ns tER Input to Output Disable Using Product Term Control 9 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10H-10 (Com’l) 13 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 1.0 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 1.0 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max VIN = VIL or VIH (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = 5 V TA = 25°C (Note 3) ICC (Static) Supply Current VIN = 0 V, Outputs Open (IOUT = 0mA), VCC = Max (Note 4) Min Max 2.4 V 0.4 2.0 -30 Unit V V 0.8 V 10 µA -100 µA 10 µA -100 µA -130 mA 55 mA Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test condition. Refer to the ICC vs. frequency graph for typical ICC characteristics. 14 PALCE22V10Q-10 (Com’l) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -10 Parameter Symbol Parameter Description Min Max Unit 10 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 6 ns tH Hold Time 0 ns tCO Clock to Output 6 ns tAR Asynchronous Reset to Registered Output 13 ns tARW Asynchronous Reset Width 8 ns tARR Asynchronous Reset Recovery Time 8 ns tSPR Synchronous Preset Recovery Time tWL tWH fMAX Clock Width Maximum Frequency (Note 2) 8 ns LOW 4 ns HIGH 4 ns External Feedback 83 MHz 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCO) (Note 3) No Feedback 1/(tWH + tWL) 110 MHz 125 MHz tEA Input to Output Enable Using Product Term Control 10 ns tER Input to Output Disable Using Product Term Control 9 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10Q-10 (Com’l) 15 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground (H/Q-15) . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground (H/Q-25) . . . . . . . +4.5 V to +5.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH IOZL Max 2.4 Unit V 0.4 2.0 V V 0.8 V 10 µA -100 µA VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) 10 µA Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) -100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = 5 V TA = 25°C (Note 3) -130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = Max -30 H 90 Q 55 mA Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 16 PALCE22V10H-15/25, Q-15/25 (Com’l) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -15 Parameter Symbol Parameter Description Min -25 Max Min Unit 25 ns Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 10 15 ns tH Hold Time 0 0 ns tCO Clock to Output 10 15 ns tAR Asynchronous Reset to Registered Output 20 25 ns tARW Asynchronous Reset Width 15 25 ns tARR Asynchronous Reset Recovery Time 10 25 ns tSPR Synchronous Preset Recovery Time tWL tWH fMAX Clock Width Maximum Frequency (Note 2) 15 Max tPD 10 25 ns LOW 8 13 ns HIGH 8 13 ns 50 33.3 MHz External Feedback tEA Internal Feedback (fCNT) Input to Output Enable Using Product Term Control tER Input to Output Disable Using Product Term Control 1/(tS + tCO) 1/(tS + tCF) (Note 3) 58.8 35.7 MHz 15 25 ns 15 25 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10H-15/25, Q-15/25 (Com’l) 17 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may vary. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min IOL = 16 mA, VIN = VIH or VIL, VCC = Min VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current IIL Input LOW Leakage Current IOZH IOZL Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIL or VIH (Note 2) Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current ICC (Static) Supply Current ICC (Dynamic) Supply Current Min 2.4 2.0 H-20/25 V = 0 V, Outputs Open IN H-10/15 (IOUT = 0 mA), VCC = Max VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz -30 Unit V 0.4 VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 0.5 V, VCC = 5 V TA = 25°C (Note 3) Max V V 0.8 V 10 µA -100 µA 10 µA -100 µA -130 mA 100 110 130 mA mA Notes: 1. These are absolute values with respect to the device ground, and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time, and the duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 18 PALCE22V10H-10/15/20/25 (Ind) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1 -10 Parameter Symbol Parameter Description Min -15 Max Min 10 -20 Max Min 15 -25 Max Min 20 Max Unit 25 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 7 10 12 15 ns tH Hold Time 0 0 0 0 ns tCO Clock to Output 6 10 12 15 ns tAR Asynchronous Reset to Registered Output 13 20 25 25 ns tARW Asynchronous Reset Width 8 15 20 25 ns tARR Asynchronous Reset Recovery Time 8 10 20 25 ns tSPR Synchronous Preset Recovery Time 8 25 ns tWL LOW 4 8 10 13 ns HIGH 4 8 10 13 ns 83.3 50 41.6 33.3 MHz 110 58.8 45.4 35.7 MHz 125 83.3 50 38.5 MHz tWH fMAX Clock Width Maximum Frequency (Note 2) External Feedback 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) No Feedback 1/(tWH + tWL) 10 14 tEA Input to Output Enable Using Product Term Control 10 15 20 25 ns tER Input to Output Disable Using Product Term Control 9 15 20 25 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10H-10/15/20/25 (Ind) 19 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) . . . . . . . . . . -40°C to +85°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Parameter Symbol VOH VOL Parameter Description Test Conditions Output HIGH Voltage VIN = VIH or VIL VCC = Min Output LOW Voltage VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Leakage Current IIL Input LOW Leakage Current IOZH Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current LOW ISC Output Short-Circuit Current ICC Supply Current IOH = -6 mA IOH = -20 µA Min V VCC-0.1 V 0.5 VIN = VCC, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA) VCC = Max -5 V 0.33 V 0.1 V 2.0 Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1, 2) VOUT = VCC, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) Unit 3.84 IOL = 16 mA IOL = 6 mA IOL = 20 µA Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1, 2) Max V 0.9 V 10 µA -10 µA 10 µA -10 µA -150 mA f = 0 MHz 30 µA f = 15 MHz 100 mA Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. Represents the worst case of HC and HCT standards, allowing compatibility with either. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation 20 PALCE22V10Z-15 (Ind) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1 -15 Parameter Symbol Parameter Description Min Max Unit 15 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 10 ns tH Hold Time 0 ns tCO Clock to Output 10 ns tAR Asynchronous Reset to Registered Output 20 ns tARW Asynchronous Reset Width 15 ns tARR Asynchronous Reset Recovery Time 10 ns tSPR Synchronous Preset Recovery Time tWL tWH fMAX Clock Width Maximum Frequency (Note 2) 10 ns LOW 8 ns HIGH 8 ns 50 MHz External Feedback 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCF) (Note 3) 58.8 MHz No Feedback 1/(tWH + tWL) 62.5 MHz tEA Input to Output Enable Using Product Term Control 15 ns tER Input to Output Disable Using Product Term Control 15 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10Z-15 (Ind) 21 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Ambient Temperature (TA) . . . . . . . . . -40°C to +85°C Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40°C to +85°C) . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Parameter Symbol VOH VOL Parameter Description Test Conditions Output HIGH Voltage VIN = VIH or VIL VCC = Min Output LOW Voltage VIN = VIH or VIL VCC = Min Min IOH = -6 mA IOH = -20 µA VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Leakage Current IIL Input LOW Leakage Current IOZH Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current LOW ISC Output Short-Circuit Current ICC Supply Current 3.84 V V 0.5 V 0.33 V 0.1 V 2.0 Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1, 2) VIN = VCC, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) f = 0 MHz Outputs Open (IOUT = 0 mA) VCC = Max f = 15 MHz Unit VCC-0.1 IOL = 16 mA IOL = 6 mA IOL = 20 µA Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1, 2) Max -5 V 0.9 V 10 µA -10 µA 10 µA -10 µA -150 mA 30 µA 120 mA Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. Represents the worst case of HC and HCT standards, allowing compatibility with either. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 22 PALCE22V10Z-25 (Com’l, Ind) CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 VCC = 5.0 V TA = 25°C f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES 1 -25 Parameters Symbol Parameter Description Min Max Unit tPD Input or Feedback to Combinatorial Output (Note 2) tS Setup Time from Input, Feedback or SP to Clock 15 ns tH Hold Time 0 ns tCO Clock to Output tAR Asynchronous Reset to Registered Output tARW Asynchronous Reset Width 25 ns tARR Asynchronous Reset Recovery Time 25 ns tSPR Synchronous Preset Recovery Time 25 ns LOW 10 ns HIGH 10 ns tWL tWH Clock Width 25 ns 15 ns 25 ns External Feedback 1/(tS + tCO) 33.3 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) 35.7 MHz No Feedback 1/(tWH + tWL) fMAX Maximum Frequency (Notes 3) tEA Input to Output Enable Using Product Term Control 25 ns tER Input to Output Disable Using Product Term Control 25 ns 50 MHz Notes: 1. See “Switching Test Circuit” for test conditions. 2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be 5 ns faster. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. PALCE22V10Z-25 (Com’l, Ind) 23 SWITCHING WAVEFORMS Input, I/O, or Feedback Input, I/O, or Feedback VT VT tPD tS Combinatorial Output VT tH VT Clock tCO Registered Output VT 16564-007 16564-008 a. Combinatorial output b. Registered output tWH VT Input Clock tEA tER tWL VOH - 0.5V Output VT VOL + 0.5V 16564-009 c. Clock width Input Asserting Asynchronous Preset 16564-010 d. Input to output disable/enable Input Asserting Synchronous Preset tARW VT VT tS tAR Registered Output VT tH VT Clock tCO tARR VT Clock Registered Output VT 16564-011 e. Asynchronous reset 16564-012 f. Synchronous preset Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical. 24 tSPR PALCE22V10 and PALCE22V10Z Families KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State 16564E-013 SWITCHING TEST CIRCUIT 5V S1 R1 Test Point Output R2 CL 16564-014 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 1.5 V Closed Z → H: Open 50 pF Z → L: Closed H → Z: Open L → Z: Closed Measured Output Value 300 Ω 5 pF PALCE22V10 and PALCE22V10Z Families All except H-5/7: 390 Ω 1.5 V H-5/7: 300 Ω H → Z: VOH - 0.5 V L →Z: VOL + 0.5 V 25 TYPICAL ICC CHARACTERISTICS VCC = 5.0 V, TA = 25°C 150 125 22V10H-5 22V10H-7 22V10H-10 100 ICC (mA) 22V10H-15 22V10H-25 22V10Q-10 75 22V10Q-25 50 25 0 0 10 20 30 40 50 Frequency (MHz) ICC vs. Frequency 16564E-015 The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC., From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. 26 PALCE22V10 and PALCE22V10Z Families TYPICAL ICC CHARACTERISTICS FOR THE PALCE22V10Z-15 VCC = 5.0 V, TA = 25°C 110 100%* 50%* 75 60 25%* ICC (mA) 45 30 15 0 0 15 *Percent of product terms used. 30 Frequency (MHz) 45 60 16564E-016 ICC vs. Frequency Graph for the PALCE22V10Z-15 TYPICAL ICC CHARACTERISTICS FOR THE PALCE22V10Z-25 VCC = 5.0 V, TA = 25°C 120 100%* 50%* 100 25%* 80 ICC (mA) 60 40 20 0 5 0 *Percent of product terms used. 10 15 20 25 30 35 40 Frequency (MHz) 45 50 16564E-017 ICC vs. Frequency Graph for the PALCE22V10Z-25 PALCE22V10 and PALCE22V10Z Families 27 ENDURANCE CHARACTERISTICS The PALCE22V10 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. Symbol Parameter Test Conditions Value Unit tDR Min Pattern Data Retention Time Max Storage Temperature 10 Years N Max Reprogramming Cycles Normal Programming Conditions 100 Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR SELECTED /4 DEVICES* VCC 100 kΩ VCC ESD Protection Input VCC VCC VCC 100 kΩ * Preload Feedback Circuitry Input Device Rev Letter Output PALCE22V10H-15 PALCE22V10H-20H H PALCE22V10H-25 PALCE22V10Q-25I 28 I PALCE22V10 and PALCE22V10Z Families 16564E-018 ROBUSTNESS FEATURES The PALCE22V10X-X/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 version. INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION DEVICES VCC VCC > 50 kΩ ESD Protection and Clamping Programming Pins only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC VCC > 50 kΩ Provides ESD Protection and Clamping Preload Circuitry Feedback Input 16564-16 Typical Output PALCE22V10 and PALCE22V10Z Families 29 INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE22V10Z VCC ESD Input Protection Transition and Detection Clamping Programming Pins only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC Provides ESD Protection and Clamping Preload Circuitry Feedback Input Input Transition Detection Typical Output 30 PALCE22V10 and PALCE22V10Z Families 16564E-020 POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ◆ The VCC rise must be monotonic. ◆ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Description tPR Power-up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW Unit 1000 ns See Switching Characteristics VCC 4V Power Max VCC Off tPR Registered Active-Low Output tS Clock tWL 16564E-021 Figure 3. Power-Up Reset Waveform PALCE22V10 and PALCE22V10Z Families 31 TYPICAL THERMAL CHARACTERISTICS PALCE22V10 Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ SKINNY DIP PLCC Unit θjc Thermal impedance, junction to case 20 18 °C/W θja Thermal impedance, junction to ambient 73 55 °C/W 200 lfpm air 66 48 °C/W 400 lfpm air 61 43 °C/W 600 lfpm air 55 40 °C/W 800 lfpm air 52 37 °C/W θjma Parameter Description Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 32 PALCE22V10 and PALCE22V10Z Families CONNECTION DIAGRAMS Top View SKINNYDIP/SOIC I1 CLK/I0 NC VCC 4 3 2 1 28 27 26 23 I/O9 I2 3 22 I/O8 I3 4 21 I/O7 I3 5 25 I/O7 I4 5 20 I/O6 I4 6 24 I/O6 I5 6 19 I/O5 I5 7 23 I/O5 I6 7 18 I/O4 NC 8 22 GND/NC * I7 8 17 I/O3 I6 9 21 I/O4 I8 9 16 I/O2 I7 10 20 I/O3 I9 10 15 I/O1 I8 11 19 I/O2 I10 11 14 I/O0 12 13 14 15 16 17 18 GND 12 13 I11 16564E-002 I/O1 I/O0 I/O8 2 I/O9 I1 I11 VCC NC 24 GND 1 I10 CLK/I0 I9 I2 PLCC 16564E-003 *For -5, this pin must be grounded for guaranteed data sheet performance. If not grounded, AC timing may degrade by about 10%. Note: Pin 1 is marked for orientation. PIN DESIGNATIONS CLK GND I I/O NC VCC = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage PALCE22V10 and PALCE22V10Z Families 33 ORDERING INFORMATION Commercial and Industrial Products Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 22 V 10 H -5 J C /5 FAMILY TYPE PAL = Programmable Array Logic PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4) TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (-40°C to +85°C) NUMBER OF OUTPUTS PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) S = 24-Pin Plastic Gull-Wing Small Outline Package (SO 024) POWER Q = Quarter Power (90-140 mA ICC) H = Half Power (90-140 mA ICC) Z = Zero Power (30 µA ICC standby) Valid Combinations 34 PALCE22V10H-5 JC PALCE22V10H-7 PC, JC PALCE22V10H-10 PC, JC, SC, PI, JI PALCE22V10Q-10 PC, JC PALCE22V10H-15 PC, JC, PI, JI, SC /4 PALCE22V10Q-15 PC, JC /5 PALCE22V10H-20 PI, JI /4 PALCE22V10H-25 PC, JC, SC, PI, JI PALCE22V10Q-25 PC, JC PALCE22V10Z-15 PI, JI PALCE22V10Z-25 PC, JC, SC, PI, JI, SI /5 /4 -5 -7 -10 -15 -20 -25 SPEED = 5 ns tPD = 7.5 ns tPD = 10 ns tPD = 15 ns tPD = 20 ns tPD = 25 ns tPD Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE22V10 and PALCE22V10Z Families