IDT IDT72221L35LB Cmos syncfifo 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 Datasheet

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241
CMOS SyncFIFO
64 X 9, 256 x 9, 512 x 9,
1024 X 9, 2048 X 9 and 4096 x 9
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 x 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1024 x 9-bit organization (IDT72221)
2048 x 9-bit organization (IDT72231)
4096 x 9-bit organization (IDT72241)
12 ns read/write cycle time (IDT72421/72201/72211)
15 ns read/write cycle time (IDT72221/72231/72241)
Read and write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be set to any depth
Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance
state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC),
ceramic leadless chip carrier (LCC), and 32-pin Thin
Quad Flat Pack (TQFP)
For Through-Hole product please see the IDT72420/
72200/72210/72220/72230/72240 data sheet
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241
SyncFIFO are very high-speed, low-power First-In, First-
FUNCTIONAL BLOCK DIAGRAM
Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211/72221/72231/72241 have a 64,
256, 512, 1024, 2048, and 4096 x 9-bit memory array,
respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks
and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and two
write enable pins (WEN1, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (REN1,
REN2). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF), are provided for improved system
control. The programmable flags default to Empty+7 and Full7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is
initiated by asserting the load pin (LD).
The IDT72421/72201/72211/72221/72231/72241 are
fabricated using IDT’s high-speed submicron CMOS
technology. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
D0 - D8
WCLK
LD
WEN1
WEN2
INPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
WRITE POINTER
EF
PAE
PAF
FF
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RS
RCLK
REN1
REN2
OE
Q0 - Q8
2655 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1995
DSC-2655/6
5.07
1
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2
D8
3
D7
4
D6
5
D5
D1
D4
32 31 30 29 28 27 26 25
D3
INDEX
INDEX
D2
RS
D8
D7
D6
D5
D4
D3
D2
PIN CONFIGURATION
1
32 31 30
29
RS
D1
1
24
WEN1
6
28
WEN1
D0
D0
2
23
WCLK
PAF
7
27
WCLK
3
PAF
22
WEN2/LD
PAE
4
21
PAE
8
26
WEN2/LD
VCC
Q8
GND
9
25
VCC
REN1
10
24
Q8
RCLK
11
23
Q7
REN2
12
22
Q6
OE
13
21
Q5
18
7
17
8
Q7
Q6
Q5
14 15 16 17 18 19 20
EF
Q4
Q3
Q2
Q1
FF
Q0
OE
EF
9 10 11 12 13 14 15 16
2655 drw 02a
LCC/PLCC
TOP VIEW
TQFP
TOP VIEW
Q4
19
6
Q3
REN2
5
Q2
RCLK
Q1
REN1
20
Q0
GND
FF
PR32-1
J32-1
L32-1
2655 drw 02
PIN DESCRIPTIONS
Symbol
D0-D8
RS
Name
Data Inputs
Reset
WCLK
Write Clock
WEN1
Write Enable 1
WEN2/LD
Write Enable 2/
Load
Q0-Q8
RCLK
Data Outputs
Read Clock
REN1
Read Enable 1
REN2
Read Enable 2
OE
Output Enable
EF
Empty Flag
PAE
I/O
Description
I
Data inputs for a 9-bit bus.
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
I
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin.
When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag
offsets.
O Data outputs for a 9-bit bus.
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are
asserted.
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7. PAE is synchronized to RCLK.
FF
Programmable
Almost-Empty
Flag
Programmable
O
Almost-Full Flag
Full Flag
O
VCC
GND
Power
Ground
PAF
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7. PAF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2655 tbl 01
5.07
2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
TBIAS
TSTG
IOUT
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +135
°C
50
50
mA
Symbol
VCCM
Parameter
Military Supply Voltage
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
VCCC
Commercial
Supply Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
4.5
5.0
5.5
V
0
2.0
0
—
0
—
V
V
2.2
—
—
V
—
—
0.8
V
GND
VIH
VIH
VIL
2655 tbl 03
2655 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
CIN(2)
(1,2)
COUT
Parameter
Conditions
Max.
Unit
Input Capacitance
VIN = 0V
10
pF
VOUT = 0V
10
pF
Output Capacitance
2655 tbl 04
NOTES:
1. With output deselected (OE = HIGH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
Symbol
Parameter
IDT72421
IDT72201
IDT72211
Commercial
tCLK = 12, 15, 20, 25,35, 50ns
Min.
Typ.
Max.
IDT72421
IDT72201
IDT72211
Military
tCLK = 20, 25,35, 50ns
Min.
Typ.
Max.
Unit
–1
—
1
–10
—
10
µA
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage, IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage, IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC(3)
Active Power Supply Current
—
—
80
—
—
100
ILI(1)
Input Leakage Current (Any Input)
ILO(2)
mA
2655 tbl 05
Symbol
Parameter
IDT72221
IDT72231
IDT72241
Commercial
tCLK = 15, 20, 25, 35, 50ns
Min.
Typ.
Max.
IDT72221
IDT72231
IDT72241
Military
tCLK = 25, 35, 50ns
Min.
Typ.
Max.
Unit
ILI(1)
Input Leakage Current (Any Input)
–1
—
1
–10
—
10
µA
ILO(2)
Output Leakage Current
–10
—
10
–10
—
10
µA
VOH
Output Logic “1” Voltage, IOH = –2mA
2.4
—
—
2.4
—
—
V
VOL
Output Logic “0” Voltage, IOL = 8mA
—
—
0.4
—
—
0.4
V
ICC1(4)
Active Power Supply Current
—
—
80
—
—
100
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3 & 4.
Measurements are made with outputs unloaded. Tested at fCLK = 20MHz.
(3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA
(4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA
fCLK = 1/tCLK.
CL = external capacitive load (30pF typical)
5.07
mA
2655 tbl 06
3
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Com'l.
Commercial & Military
72421L12 72421L15
72201L12 72201L15
72211L12 72211L15
Symbol
Parameter
72421L20
72201L20
72211L20
72421L25 72421L35
72201L25 72201L35
72211L25 72211L35
Min. Max. Min. Max. Min. Max. Min. Max.
72421L50
72201L50
72211L50
Min. Max. Min. Max.
Unit
fS
Clock Cycle Frequency
—
83.3
—
66.7
—
50
—
40
—
28.6
—
20
MHz
tA
Data Access Time
2
8
2
10
2
12
3
15
3
20
3
25
ns
tCLK
Clock Cycle Time
12
—
15
—
20
—
25
—
35
—
50
—
ns
tCLKH
Clock High Time
5
—
6
—
8
—
10
—
14
—
20
—
ns
tCLKL
Clock Low Time
5
—
6
—
8
—
10
—
14
—
20
—
ns
tDS
Data Set-up Time
3
—
4
—
5
—
6
—
8
—
10
—
ns
tDH
Data Hold Time
0
—
1
—
1
—
1
—
2
—
2
—
ns
tENS
Enable Set-up Time
3
—
4
—
5
—
6
—
8
—
10
—
ns
tENH
Enable Hold Time
0
—
1
—
1
—
1
—
2
—
2
—
ns
tRS
Reset Pulse Width(1)
12
—
15
—
20
—
25
—
35
—
50
—
ns
tRSS
Reset Set-up Time
12
—
15
—
20
—
25
—
35
—
50
—
ns
tRSR
Reset Recovery Time
12
—
15
—
20
—
25
—
35
—
50
—
ns
tRSF
Reset to Flag and Output Time
—
12
—
15
—
20
—
25
—
35
—
50
ns
tOLZ
Output Enable to Output in Low-Z(2)
0
—
0
—
0
—
0
—
0
—
0
—
ns
tOE
Output Enable to Output Valid
3
7
3
8
3
10
3
13
3
15
3
28
ns
tOHZ
Output Enable to Output in High-Z(2)
3
7
3
8
3
10
3
13
3
15
3
28
ns
tWFF
Write Clock to Full Flag
—
8
—
10
—
12
—
15
—
20
—
30
ns
tREF
Read Clock to Empty Flag
—
8
—
10
—
12
—
15
—
20
—
30
ns
tAF
Write Clock to Almost-Full Flag
—
8
—
10
—
12
—
15
—
20
—
30
ns
tAE
Read Clock to Almost-Empty Flag
—
8
—
10
—
12
—
15
—
20
—
30
ns
tSKEW1
Skew time between Read Clock &
Write Clock for Empty Flag &Full Flag
5
—
6
—
8
—
10
—
12
—
15
—
ns
tSKEW2
Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
22
—
28
—
35
—
40
—
42
—
45
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
2655 tbl 07
5.07
4
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Commercial and Military
72221L15
72221L20 72221L25 72221L35 72221L50
72231L15
72231L20 72231L25 72231L35 72231L50
72241L15
72241L20 72241L25 72241L35 72241L50
Symbol
Parameter
fS
Clock Cycle Frequency
tA
tCLK
Min. Max. Min. Max.
—
66.7
—
50
Data Access Time
2
Clock Cycle Time
15
10
2
—
20
tCLKH
Clock HIGH Time
tCLKL
Clock LOW Time
6
—
6
—
tDS
Data Set-up Time
4
tDH
Data Hold Time
tENS
Enable Set-up Time
tENH
tRS
Min. Max. Min. Max. Min. Max.
—
40
12
3
—
25
8
—
8
—
—
5
1
—
4
—
Enable Hold Time
1
Reset Pulse Width(1)
15
Unit
—
28.6
—
20
MHz
15
3
—
35
20
3
25
ns
—
50
—
ns
10
—
10
—
14
—
20
—
ns
14
—
20
—
—
6
ns
—
8
—
10
—
ns
1
—
5
—
1
—
2
—
2
—
ns
6
—
8
—
10
—
ns
—
1
—
1
—
2
—
2
—
ns
—
20
—
25
—
35
—
50
—
ns
tRSS
Reset Set-up Time
15
—
20
—
25
—
35
—
50
—
ns
tRSR
Reset Recovery Time
15
—
20
—
25
—
35
—
50
—
ns
tRSF
Reset to Flag Time and Output Time
—
15
—
20
—
25
—
35
—
50
ns
tOLZ
Output Enable to Output in Low-Z(2)
0
—
0
—
0
—
0
—
0
—
ns
ns
tOE
Output Enable to Output Valid
3
8
3
10
3
13
3
15
3
28
tOHZ
Output Enable to Output in High-Z(2)
3
8
3
10
3
13
3
15
3
28
ns
tWFF
Write Clock to Full Flag
—
10
—
12
—
15
—
20
—
30
ns
tREF
Read Clock to Empty Flag
—
10
—
12
—
15
—
20
—
30
ns
tPAF
Write Clock to Programmable Almost-Full Flag
—
10
—
12
—
15
—
20
—
30
ns
tPAE
Read Clock to Programmable Almost-Empty Flag
—
10
—
12
—
15
—
20
—
30
ns
tSKEW1 Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
6
—
8
—
10
—
12
—
15
—
ns
tSKEW2 Skew Time Between Read Clock and Write Clock
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
28
—
35
—
40
—
42
—
45
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
2655 tbl 08
5V
1.1K
D.U.T.
680Ω
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
30pF*
GND to 3.0V
3ns
2655 drw 03
Input Timing Reference Levels
1.5V
or equivalent circuit
Output Reference Levels
1.5V
Figure 1. Output Load
Output Load
See Figure 1
*Includes jig and scope capacitances.
2655 tbl 09
5.07
5
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D0 - D8) — Data inputs for 9-bit wide data.
CONTROLS:
Reset (RS) — Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF) will be reset to HIGH after tRSF. The Empty Flag (EF) and
Programmable Almost-Empty Flag (PAE) will be reset to LOW
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK) — A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (WEN1) — If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is low, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
Read Enables (REN1, REN2) — When both Read Enables
(REN1, REN2) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
Output Enable (OE) — When Output Enable (OE) is
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
Write Enable 2/Load (WEN2/LD) — This is a dualpurpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which
allows depth expansion. If Write Enable 2/Load (WEN2/LD)
is set high at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/
LD) is HIGH, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) and Write
Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset
(RS=low). The IDT72421/72201/72211/72221/72231/72241
devices contain four 8-bit offset registers which can be loaded
with data on the inputs, or read on the outputs. See Figure 3
for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/
LD) are set low, data on the inputs D is written into the Empty
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
5.07
6
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the Write Enable 2/Load (WEN2/LD) pin HIGH, the
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence
is written.
The contents of the offset registers can be read on the
output lines when the Write Enable 2/Load (WEN2/LD) pin is
set low and both Read Enables (REN1, REN2) are set LOW.
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
A read and write should not be performed simultaneously
to the offset registers.
72421 - 64 x 9-BIT
6 5
0
Empty Offset (LSB) Reg.
8
0
WEN1
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Selection
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
NOTE:
2655 drw 04
1. The same selection sequence applies to reading from the registers. REN1
and REN2 are enabled and read is performed on the LOW-to-HIGH
transition of RCLK.
Figure 2. Write Offset Register
72201 - 256 x 9-BIT
8
72211 - 512 x 9-BIT
7
Default Value 007H
8
WCLK(1)
LD
0
8
0
7
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
8
0
1
8
0
(MSB)
0
6 5
8
0
8
8
0
7
Full Offset (LSB) Reg.
Default Value 007H
8
0
7
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
0
8
Default Value 007H
0
1
8
0
(MSB)
0
72221 - 1024 x 9-BIT
8
8
8
8
72231 - 2048 x 9-BIT
7
0
8
72241 - 4096 x 9-BIT
7
0
8
0
7
Empty Offset (LSB) Reg.
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
0
1
8
0
2
3
8
0
(MSB)
(MSB)
(MSB)
00
000
0000
7
0
8
7
0
Full Offset (LSB) Reg.
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
0
1
8
8
0
7
Full Offset (LSB)
Default Value 007H
0
2
8
3
0
(MSB)
(MSB)
(MSB)
00
000
0000
Figure 3. Offset Register Location and Default Values
5.07
2655 drw 05
7
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUTS:
Full Flag (FF) — The Full Flag (FF) will go LOW, inhibiting
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 64 writes for the IDT72421, 256 writes for the IDT72201,
512 writes for the IDT72211, 1024 writes for the IDT72221,
2048 writes for the IDT72231, and 4096 writes for the IDT72241.
The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK).
Empty Flag (EF) — The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag ( PAF ) — The
Programmable Almost-Full Flag (PAF) will go LOW when the
FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS), the Programmable Almost-Full
Flag (PAF) will go LOW after (64-m) writes for the IDT72421,
(256-m) writes for the IDT72201, (512-m) writes for the
IDT72211, (1024-m) writes for the IDT72221, (2048-m) writes
for the IDT72231, and (4096-m) writes for the IDT72241. The
offset “m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable
Almost-Full Flag (PAF) will go LOW at Full-7 words.
The Programmable Almost-Full Flag (PAF) is synchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
Programmable Almost-Empty Flag (PAE) — The
Programmable Almost-Empty Flag (PAE) will go LOW when
the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty offset registers. If no
reads are performed after Reset the Programmable AlmostEmpty Flag (PAE) will go HIGH after "n+1" for the IDT72421/
72201/72211/72221/72231/72241.
If there is no Empty offset specified, the Programmable
Almost-Empty Flag (PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty Flag ( PAE ) is
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).
Data Outputs (Q0 - Q8) — Data outputs for a 9-bit wide
data.
TABLE 1: STATUS FLAGS
72421
0
1 to n (1)
(n+1) to (64-(m+1))
(64-m)(2) to 63
64
NUMBER OF WORDS IN FIFO
72201
0
1 to n (1)
(n+1) to (256-(m+1))
(256-m)(2) to 255
256
72211
0
1 to n (1)
(n+1) to (512-(m+1))
(512-m)(2) to 511
512
FF
PAF
PAE
EF
H
H
H
H
L
L
L
H
H
H
L
H
L
L
H
H
H
H
H
H
2655 tbl 10
NUMBER OF WORDS IN FIFO
72221
72231
72241
FF
PAF
PAE
EF
0
0
0
H
H
L
L
1 to n(1)
1 to n(1)
1 to n(1)
H
H
L
H
(n+1) to (1024-(m+1))
(n+1) to (2048-(m+1))
(n+1) to (4096-(m+1))
H
H
H
H
(1024-m)(2) to 1023
(2048-m)(2) to 2047
(4096-m)(2) to 4095
H
L
H
H
1024
2048
4096
L
L
H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
H
2655 tbl 11
5.07
8
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tRS
RS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN1,
REN2
WEN1
WEN2/LD
(1)
tRSF
EF, PAE
tRSF
FF, PAF
tRSF
OE = 1
Q0 - Q8
OE = 0
(2)
2655 drw 06
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as
a load enable for the programmable flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
5.07
9
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
tDH
tDS
D0 - D 8
DATA IN VALID
tENS
tENH
WEN1
NO OPERATION
WEN2/
(If Applicable)
NO OPERATION
tWFF
tWFF
FF
tSKEW1(1)
RCLK
REN1,
REN2
2655 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 5. Write Cycle Timing
5.07
10
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKL
tCLKH
RCLK
tENH
REN1,
REN2
tENS
NO OPERATION
tREF
tREF
EF
tA
Q0 - Q8
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW1 (1)
WCLK
WEN1
WEN2
2655 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle
Timing
Figure 6. Read Cycle Timing
5.07
11
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
D0 - D8
D1
D2
D3
D0 (First Valid
tENS
WEN1
WEN2
(If Applicable)
tFRL (1)
tSKEW1
RCLK
tREF
EF
REN1,
REN2
tA
Q 0 - Q8
tA
D0
D1
tOLZ
tOE
OE
2655 drw 09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
5.07
12
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK
tDS
tSKEW1
tDS
tSKEW1
DATA WRITE
D0 - D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(If Applicable)
RCLK
tENS
REN1,
REN2
OE
tENH
tENS
tENH
tA
LOW
tA
Q0 - Q8
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.07
13
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
tDS
DATA WRITE 1
D 0 - D8
DATA WRITE 2
tENH
tENH
tENS
tENS
WEN1
tENS
tENH
tENH
tENS
WEN2
(If Applicable)
(1)
tFRL(1)
tFFL
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN1,
REN2
OE
Q 0 - Q8
LOW
tA
DATA READ
DATA IN OUTPUT REGISTER
2655 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
5.07
14
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
tCLKH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKL
(4)
WCLK
tENS
tENH
tENS
tENH
WEN1
WEN2
(If Applicable)
tPAF
(1)
PAF
Full - m words in FIFO(2)
Full - (m+1) words in FIFO
tSKEW2 (3)
tPAF
RCLK
REN1,
REN2
tENS
tENH
2655 drw 12
NOTES:
1. PAF offset = m.
2. 64 - m words in for IDT72421, 256 - m words in FIFO for IDT72201, 512 - m words for IDT72211, 1024 - m words for IDT72221, 2048 - m words for IDT72231,
4096 - m words for IDT72241.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.07
15
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
tCLKH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLKL
WCLK
tENS
tENH
tENS
tENH
WEN1
WEN2
(If Applicable)
(1)
PAE
n words in FIFO
tSKEW2 (2)
n+1 words in FIFO
tPAE
tPAE
(3)
RCLK
tENS tENH
REN1,
REN2
2655 drw 13
NOTES:
1. PAE offset = n.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
5.07
16
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN1
tDS
tDH
D 0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
2655 drw 14
Figure 12. Write Offset Registers Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN1,
REN2
tA
Q0 - Q7
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
2655 drw 15
Figure 13. Read Offset Registers Timing
5.07
17
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IDT72421/
72201/72211/72221/72231/72241 may be used when the
application requirements are for 64/256/512/1024/2048/4096
words or less. When the IDT72421/72201/72211/72221/
72231/72241 are in a Single Device Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure
14). In this configuration, the Write Enable 2/Load (WEN2/LD)
pin is set LOW at Reset so that the pin operates as a control
to load and read the programmable flag offsets.
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D0 - D8)
FULL FLAG (FF)
PROGRAMMABLE ALMOST FULL (PAF)
READ CLOCK (RCLK)
IDT
72421/
72201/
72211/72221/
72231/
72241
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
DATA OUT (Q0 - Q8)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST EMPTY (PAE)
READ ENABLE 2 (REN2)
2655 drw 16
Figure 14. Block Diagram of Single 64 x 9/256 x 9/512 x 9/1024 x 9/2048 x 9/4096 x 9 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may
be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should
be created for each of the end-point status flags (EF and FF).
The partial status flags (AE and AF) can be detected from any
one device. Figure 15 demonstrates a 18-bit word width by
using two IDT72421/72201/72211/72221/72231/72241s. Any
word width can be attained by adding additional IDT72421/
72201/72211/72221/72231/72241s.
When the IDT72421/72201/72211/72221/72231/72241 are
in a Width Expansion Configuration, the Read Enable 2
(REN2) control input can be grounded (see Figure 15). In this
configuration, the Write Enable 2/Load (WEN2/LD) pin is set
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
RESET (RS)
RESET (RS)
DATA IN (D)
18
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE1 (WEN1)
WRITE ENABLE2/LOAD (WEN2/LD)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
PROGRAMMABLE (PAF)
OUTPUT ENABLE (OE)
IDT
72421/
72201/
72211/
72221/
72231/
72241
IDT
72421/
72201/
72211/
72221/
72231/
72241
9
READ ENABLE 2 (REN2)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9 DATA OUT (Q)
READ ENABLE 2 (REN2)
18
2655 drw 17
Figure 15. Block Diagram of 64 x 18/256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO
Used in a Width Expansion Configuration
5.07
18
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT72421/7221/72211/72221/
72231/72241 can be adapted to applications when the requirements are for greater than 64/256/512/1024/2048/4096
words. The existence of two enable pins on the read and write
port allow depth expansion. The Write Enable 2/Load pin is
used as a second write enable in a depth expansion configuration thus the Programmable flags are set to the default
values. Depth expansion is possible by using one enable
input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical
application would have the expansion logic alternate data
access from one device to the next in a sequential manner.
The IDT72421/7221/72211/72221/72231/72241 operates in
the Depth Expansion configuration when the following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
operates a second Write Enable.
2. External logic is used to control the flow of data.
Please see the Applicatioin Note" DEPTH EXPANSION OF
IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER
APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
Military (–55°C to +125°C)
B
Compliant to MIL-STD-883, Class B
5.07
J
L
PF
Plastic Leaded Chip Carrier (PLCC)
Leadless Chip Carrier (LCC)
Thin Quad Flat Pack (TQFP)
12
15
20
25
35
50
Com'l. (72421/72201/72211) Only
Com'l. Only
All except 72221/72231/72241 Military
L
Low Power
72421
72201
72211
72221
64 x 9 Synchronous FIFO
256 x 9 Synchronous FIFO
512 x 9 Synchronous FIFO
1024 x 9 Synchronous FIFO
2048 x 9 Synchronous FIFO
4096 x 9 Synchronous FIFO
Clock Cycle
Time (tCLK)
Speed in ns
2655 drw 18
19
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