STMicroelectronics M48T59Y-70PC1TR 64 kbit 8kb x8 timekeeper sram Datasheet

M48T58
M48T58Y
64 Kbit (8Kb x8) TIMEKEEPER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
BYTEWIDE RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T58: 4.5V ≤ VPFD ≤ 4.75V
– M48T58Y: 4.2V ≤ VPFD ≤ 4.5V
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48T58/58Y TIMEKEEPER® RAM is an 8K x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packages
to provide a highly integrated battery backed-up
memory and real time clock solution.
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
FT
Frequency Test Output (Open Drain)
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
July 1999
SNAPHAT (SH)
Battery/Crystal
28
28
1
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
SOH28 (MH)
Figure 1. Logic Diagram
VCC
13
8
A0-A12
DQ0-DQ7
W
E1
M48T58
M48T58Y
FT
E2
G
VSS
AI01374B
1/17
M48T58, M48T58Y
Figure 2A. DIP Pin Connections
FT
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7
M48T58 22
8 M48T58Y 21
20
9
19
10
18
11
17
12
13
16
14
15
Figure 2B. SOIC Pin Connections
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
FT
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
27
2
26
3
25
4
24
5
23
6
22
7
M48T58Y
21
8
20
9
19
10
18
11
17
12
16
13
15
14
AI01375B
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
AI01376B
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
TSLD
(2)
Parameter
Value
Unit
Ambient Operating Temperature
0 to 70
°C
–40 to 85
°C
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
260
°C
VIO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode
VCC
Deselect
Deselect
Write
4.75V to 5.5V
or
4.5V to 5.5V
Read
Read
Deselect
Deselect
VSO to VPFD (min)
≤ VSO
(2)
E1
E2
G
W
DQ0-DQ7
Power
VIH
X
X
X
High Z
Standby
X
VIL
X
X
High Z
Standby
VIL
VIH
X
VIL
DIN
Active
VIL
VIH
VIL
VIH
DOUT
Active
VIL
VIH
VIH
VIH
High Z
Active
X
X
X
X
High Z
CMOS Standby
X
X
X
X
High Z
Battery Back-up Mode
Notes: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
2/17
M48T58, M48T58Y
Figure 3. Block Diagram
FT
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8184 x 8
SRAM ARRAY
LITHIUM
CELL
E1
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
E2
VPFD
W
G
VCC
DESCRIPTION (cont’d)
The M48T58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48T58/58Y silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
VSS
AI01377C
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF or 5pF
AI01030
3/17
M48T58, M48T58Y
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
CIO
(3)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 6. DC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI (1)
ILO
(1)
Parameter
Test Condition
Input Leakage Current
Output Leakage Current
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
50
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
E1 = VIH, E2 = VIL
3
mA
ICC2
Supply Current (Standby) CMOS
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
3
mA
VIL (2)
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
IOL = 2.1mA
0.4
V
IOL = 10mA
0.4
V
VOL
Output Low Voltage
Output Low Voltage (FT)
VOH
(3)
Output High Voltage
IOH = –1mA
2.4
V
Notes: 1. Outputs Deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
3. The FT pin is Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage (M48T58)
4.5
4.6
4.75
V
VPFD
Power-fail Deselect Voltage (M48T58Y)
4.2
4.35
4.5
V
VSO
Battery Back-up Switchover Voltage
tDR(2)
Expected Data Retention Time
3.0
7
V
YEARS
Notes: 1. All voltages referenced to VSS.
2. At 25°C
DESCRIPTION (cont’d)
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT ) p art number is "M4T28BR12SH1".
As Figure 3 shows, the static memory array and the
q ua rt z co nt rol led clock o sci lla t or of t h e
M48T58/58Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
4/17
BYTEWIDE clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year), 30, and 31 day months are made
automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration
setting.
M48T58, M48T58Y
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C)
Symbol
Parameter
Min
Max
Unit
0
µs
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSO VCC Fall Time
10
µs
tR
VPFD(min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSO to VPFD (min) VCC Rise Time
1
µs
tREC
VPFD(max) to Inputs Recognized
40
tPD
E1 or W at VIH or E2 at VIL before Power Down
tF (1)
tFB
(2)
200
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
5/17
M48T58, M48T58Y
Table 9. Read Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T58 / M48T58Y
Symbol
Parameter
Min
tAVAV
Unit
-70
Read Cycle Time
Max
70
ns
tAVQV (1)
Address Valid to Output Valid
70
ns
tE1LQV (1)
Chip Enable 1 Low to Output Valid
70
ns
(1)
Chip Enable 2 High to Output Valid
70
ns
tGLQV (1)
Output Enable Low to Output Valid
35
ns
tE2HQV
(2)
Chip Enable 1 Low to Output Transition
5
ns
tE2HQX (2)
Chip Enable 2 High to Output Transition
5
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tE1HQZ
(2)
Chip Enable 1 High to Output Hi-Z
25
ns
Chip Enable 2 Low to Output Hi-Z
25
ns
Output Enable High to Output Hi-Z
25
ns
tE1LQX
tE2LQZ (2)
tGHQZ
(2)
tAXQX (1)
Address Transition to Output Transition
10
ns
Notes: 1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tE1LQV
tE1HQZ
E1
tE1LQX
tE2HQV
tE2LQZ
E2
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00962
Note: Write Enable (W) = High.
6/17
M48T58, M48T58Y
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T58 / M48T58Y
Symbol
Parameter
Unit
-70
Min
Max
tAVAV
Write Cycle Time
70
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVE1L
Address Valid to Chip Enable 1 Low
0
ns
tAVE2H
Address Valid to Chip Enable 2 High
0
ns
tWLWH
Write Enable Pulse Width
50
ns
tE1LE1H
Chip Enable 1 Low to Chip Enable 1 High
55
ns
tE2HE2L
Chip Enable 2 High to Chip Enable 2 Low
55
ns
tWHAX
Write Enable High to Address Transition
0
ns
tE1HAX
Chip Enable 1 High to Address Transition
0
ns
tE2LAX
Chip Enable 2 Low to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
30
ns
tDVE1H
Input Valid to Chip Enable 1 High
30
ns
tDVE2L
Input Valid to Chip Enable 2 Low
30
ns
tWHDX
Write Enable High to Input Transition
5
ns
tE1HDX
Chip Enable 1 High to Input Transition
5
ns
tE2LDX
Chip Enable 2 Low to Input Transition
5
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to Write Enable High
60
ns
tAVE1H
Address Valid to Chip Enable 1 High
60
ns
tAVE2L
Address Valid to Chip Enable 2 Low
60
ns
5
ns
tWHQX
(1, 2)
Write Enable High to Output Transition
Notes: 1. CL = 5pF (see Figure 4).
2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
7/17
M48T58, M48T58Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A12
tAVWH
tWHAX
tAVE1L
E1
tAVE2H
E2
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00963
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVE1H
tAVE1L
tE1LE1H
tE1HAX
E1
tAVE2L
tAVE2H
tE2HE2L
tE2LAX
E2
tAVWL
W
tE1HDX
tE2LDX
DQ0-DQ7
DATA INPUT
tDVE1H
tDVE2L
8/17
AI00964B
M48T58, M48T58Y
E2 and G access times are not met, valid data will
be available after the latter of the Chip Enable
Access times (tE1LQV or tE2HQV) or Output Enable
Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for Output Data
Hold time (tAXQX) but will go indeterminate until the
next Address Access.
DESCRIPTION (cont’d)
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T58/58Y includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T58/58Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
WRITE MODE
The M48T58/58Y is in the Write Mode whenever W
and E1 are low and E2 is high. The start of a write
is referenced from the latter occurring falling edge
of W or E1, or the rising edge of E2. A write is
terminated by the earlier rising edge of W or E1, or
the falling edge of E2. The addresses must be held
valid throughout the cycle. E1 or W must return high
or E2 low for a minimum of tE1HAX or tE2LAX from
Chip Enable or tWHAX from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E1 and G and a high on E2, a low on W will
disable the outputs tWLQZ after W falls.
READ MODE
The M48T58/58Y is in the Read Mode whenever
W (Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E1,
E2, and G access times are also satisfied. If the E1,
Table 11. Register Map
Data
Address
D7
1FFFh
D6
D5
D4
D3
10 Years
10 M.
D1
D0
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day
01-07
Hours
Hour
00-23
1FFEh
0
0
1FFDh
0
0
1FFCh
0
FT
1FFBh
0
0
1FFAh
0
10 Minutes
Minutes
Minutes
00-59
1FF9h
ST
10 Seconds
Seconds
Seconds
00-59
1FF8h
W
R
0
D2
Function/Range
BCD Format
10 Date
0
0
10 Hours
S
0
Day
Calibration
Control
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to ’0’
9/17
M48T58, M48T58Y
DATA RETENTION MODE
With valid VCC applied, the M48T58/58Y operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T58/58Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T58/58Y for
an accumulated period of at least 7 years when VCC
is less than VSO. As system power returns and VCC
rises above VSO, the battery is disconnected, and
the power supply is switched to external VCC. Write
protection continues until VCC reaches VPFD (min)
plus tREC (min). E1 should be kept high or E2 low
as VCC rises past VPFD(min) to prevent inadvertent
write cycles prior to system stabilization. Normal
RAM operation can resume tREC after VCC exceeds
VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data
registers, and not the actual clock counters, updating the registers can be halted without disturbing
the clock itself.
Updating is halted when a ’1’ is written to the READ
bit, D6 in the Control register (1FF8h). As long as
a ’1’ remains in that position, updating is halted.
After a halt is issued, the registers reflect the count;
that is, the day, date, and the time that were current
at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Setting the Clock
Bit D7 of the Control register (1FF8h) is the WRITE
bit. Setting the WRITE bit to a ’1’, like the READ bit,
halts updates to the TIMEKEEPER registers. The
user can then load them with the correct day, date,
and time data in 24 hour BCD format (see Table
10). Resetting the WRITE bit to a ’0’ then transfers
the values of all time registers (1FF9h-1FFFh) to
the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
marked as ’0’ in Table 10 must be written to ’0’ to
allow for normal TIMEKEEPER and RAM operation. After the WRITE bit is reset, the next clock
update will occur within one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
10/17
M48T58, M48T58Y
Stopping and Starting the Oscillator
tracted, negative calibration) or split (added, positive calibration) depends upon the value loaded
into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ’1’
indicates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a
binary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and
so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or - 5.35 seconds per month
which corresponds to a total range of +5.5 or - 2.75
minutes per month.
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T58/58Y is
shipped from STMicroelectronics with the STOP bit
set to a ’1’. When reset to a ’0’, the M48T58
oscillator starts within one second.
Calibrating the Clock
The M48T58/58Y is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 ppm (parts
per million) oscillator frequency error at 25°C,
which equates to about ± 1.53 minutes per month.
With the calibration bits properly set, the accuracy
of each M48T58 improves to better than ±4 ppm at
25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips compensate for crystal frequency and temperature shift
error with cumbersome trim capacitors. The
M48T58/58Y design, however, employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9.
The number of times pulses are blanked (sub-
Figure 10. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
-60
T0 = 25 °C
-80
-100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
°C
AI02124
11/17
M48T58, M48T58Y
CLOCK OPERATIONS (cont’d)
Two methods are available for ascertaining how
much calibration a given M48T58/58Y may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known
accurate reference (like WWV broadcasts). While
that may seem crude, it allows the designer to give
the end user the ability to calibrate his clock as his
environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple
utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register, is set to a ’1’, and the oscillator is running
at 32,768 Hz, the Frequency Test (Pin 1) will toggle
at 512 Hz. Any deviation from 512 Hz indicates the
degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of
512.01024 Hz would indicate a +20 ppm oscillator
frequency error, requiring a -10 (WR001010) to be
loaded into the Calibration Byte for correction. Note
that setting or changing the Calibration Byte does
not affect the Frequency test output frequency.
The FT bit must be set using the same method used
to set the clock, using the Write bit.
The Frequency Test pin is an open drain output
which requires a pull-up resistor for proper operation. A 500-10kΩ resistor is recommended in order
to control the rise time.
For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 11) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 11. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
12/17
M48T58, M48T58Y
ORDERING INFORMATION SCHEME
Example:
Supply Voltage and Write
Protect Voltage
58 (1)
58Y
VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
M48T58Y
-70 MH
Speed
-70 70ns
1
Package
PC
PCDIP28
MH (2) SOH28
TR
Temp. Range
1
0 to 70 °C
Shipping Method
for SOIC
blank Tubes
TR
Tape & Reel
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Notes: 1. The M48T58 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form.
Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since this will drain the lithium
button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
13/17
M48T58, M48T58Y
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Symb
Typ
inches
Min
Max
A
8.89
A1
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
A2
A1
B1
B
Typ
e1
A
L
C
eA
e3
D
N
E
1
Drawing is not to scale.
14/17
PCDIP
M48T58, M48T58Y
SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
A2
0.004
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
15/17
M48T58, M48T58Y
SH - 4-pin SNAPHAT Housing for 49mAh Battery
mm
Symb
Typ
Min
A
inches
Max
Typ
Min
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A1
eA
A2
A
A3
B
L
eB
D
E
SHTK-A
Drawing is not to scale.
16/17
Max
M48T58, M48T58Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 1999 STMicroelectronics - All Rights Reserved
® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics
 CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics
STMicroelectronics GROUP OF COMPANIES
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Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
17/17
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