LT1711/LT1712 Single/Dual 4.5ns, 3V/5V/±5V, Rail-to-Rail Comparators U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®1711/LT1712 are UltraFastTM 4.5ns comparators featuring rail-to-rail inputs, rail-to-rail complementary outputs and an output latch. Optimized for 3V and 5V power supplies, they operate over a single supply voltage range from 2.4V to 12V or from ±2.4V to ±6V dual supplies. Ultrafast: 4.5ns at 20mV Overdrive 5.5ns at 5mV Overdrive Rail-to-Rail Inputs Rail-to-Rail Complementary Outputs (TTL/CMOS Compatible) Specified at 2.7V, 5V and ±5V Supplies Output Latch Inputs Can Exceed Supplies Without Phase Reversal LT1711: 8-Lead MSOP Package LT1712: 16-Lead Narrow SSOP Package The LT1711/LT1712 are designed for ease of use in a variety of systems. In addition to wide supply voltage flexibility, rail-to-rail input common mode range extends 100mV beyond both supply rails, and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink 10mA to within 0.5V of GND or source 10mA to within 0.7V of V +. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Speed Automatic Test Equipment Current Sense for Switching Regulators Crystal Oscillator Circuits High Speed Sampling Circuits High Speed A/D Converters Pulse Width Modulators Window Comparators Extended Range V/F Converters Fast Pulse Height/Width Discriminators Line Receivers High Speed Triggers The LT1711/LT1712 have internal TTL/CMOS compatible latches for retaining data at the outputs. Each latch holds data as long as the latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT1711 is available in the 8-pin MSOP package. The LT1712 is available in the 16-pin narrow SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. U ■ TYPICAL APPLICATIO A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator 5V 1N4148 1M 1M 2k 390Ω 1M* MV-209 VARACTOR DIODE 3.9k* LT1711/LT1712 Propagation Delay vs Input Overdrive VIN 0V TO 5V 1M 0.047µF C SELECT (CHOOSE FOR CORRECT PLL LOOP RESPONSE) Y1** 15pF 100pF LT1711 – FREQUENCY OUTPUT 2k TA = 25°C V+ = 5V V – = 0V VSTEP = 100mV 5.5 100pF + 6.0 1k* PROPAGATION DELAY (ns) 5V 47k* LT1004-2.5 171112 TA01 5.0 tPD+ 4.5 tPD– 4.0 3.5 3.0 0 200pF * 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz 10 20 40 50 30 INPUT OVERDRIVE (mV) 60 171112 TA02 1 LT1711/LT1712 W W W AXI U U ABSOLUTE RATI GS (Note 1) Supply Voltage V + to V – ............................................................ 12.6V V + to GND ........................................................ 12.6V V – to GND .............................................– 10V to 0.3V Differential Input Voltage ................................... ±12.6V Latch Pin Voltage ...................................................... 7V Input and Latch Current ..................................... ±10mA Output Current (Continuous) .............................. ±20mA Operating Temperature Range ................ – 40°C to 85°C Specified Temperature Range (Note 2) ... – 40°C to 85°C Junction Temperature .......................................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER LT1711CMS8 LT1711IMS8 TOP VIEW V+ +IN –IN V– 1 2 3 4 8 7 6 5 Q Q GND LATCH ENABLE TOP VIEW –IN A 1 +IN A 2 LATCH ENABLE A 15 GND V– 3 14 Q A + 4 13 Q A V+ 5 12 Q B – 6 11 Q B +IN B 7 –IN B 8 10 GND LATCH 9 ENABLE B V V MS8 PACKAGE 8-LEAD PLASTIC MSOP MS8 PART MARKING TJMAX = 150°C, θJA = 250°C/ W (NOTE 12) LTTC LTTD 16 ORDER PART NUMBER LT1712CGN LT1712IGN GN PART MARKING 1712 1712I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 120°C/ W (NOTE 12) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V + = 2.7V or V + = 5V, V – = 0V, VCM = V +/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER V+ Positive Supply Voltage Range VOS Input Offset Voltage (Note 4) ∆VOS/∆T Input Offset Voltage Drift IOS Input Offset Current CONDITIONS MIN ● RS = 50Ω, VCM = V +/2 RS = 50Ω, VCM = V +/2 RS = 50Ω, VCM = 0V RS = 50Ω, VCM = V + TYP MAX 0.5 5.0 6.0 2.4 7 0.7 1 10 µV/°C 0.2 3 6 µA µA –5 5 10 µA µA V + + 0.1 V ● IB VCM CMRR PSRR+ 2 Input Bias Current (Note 5) Input Voltage Range (Note 9) Common Mode Rejection Ratio Positive Power Supply Rejection Ratio V + = 5V, 0V ≤ VCM ≤ 5V V + = 5V, 0V ≤ VCM ≤ 5V V + = 2.7V, 0V ≤ VCM ≤ 2.7V V + = 2.7V, 0V ≤ VCM ≤ 2.7V 2.4V ≤ V + ≤ 7V, VCM = 0V ● – 18 – 35 ● – 0.1 65 ● 56 53 54 50 58 56 75 ● ● V mV mV mV mV ● ● UNITS 65 dB dB dB dB dB dB LT1711/LT1712 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V + = 2.7V or V + = 5V, V – = 0V, VCM = V +/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS PSRR– – 7V ≤ V – Negative Power Supply Rejection Ratio ≤ 0V, V + = 5V, V MIN TYP 60 58 80 ● dB dB 1 15 V/mV V+ – 0.5 V+ – 0.7 V+ – 0.2 V+ – 0.4 CM = 5V AV Small-Signal Voltage Gain (Note 10) VOH Output Voltage Swing HIGH IOUT = 1mA, VOVERDRIVE = 50mV IOUT = 10mA, VOVERDRIVE = 50mV ● ● VOL Output Voltage Swing LOW IOUT = – 1mA, VOVERDRIVE = 50mV IOUT = – 10mA, VOVERDRIVE = 50mV ● ● I+ Positive Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V Negative Supply Current (Per Comparator) V + = 5V, VOVERDRIVE = 1V Latch Pin High Input Voltage ● VIL Latch Pin Low Input Voltage ● IIL Latch Pin Current VLATCH = V + tPD Propagation Delay (Note 6) ∆VIN = 100mV, VOVERDRIVE = 20mV ∆VIN = 100mV, VOVERDRIVE = 20mV ∆VIN = 100mV, VOVERDRIVE = 5mV V V 0.4 0.5 V V 15 19 26 mA mA 8 10 13 mA mA 0.8 V ● VIH UNITS 0.20 0.35 ● I– MAX 2.4 V ● 4.5 ● 15 µA 6.0 8.5 ns ns ns 1.5 ns 5.5 ∆tPD Differential Propagation Delay (Note 6) ∆VIN = 100mV, VOVERDRIVE = 20mV tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5 ns tSU Latch Setup Time (Note 7) 1 ns tH Latch Hold Time (Note 7) 0 ns tDPW Minimum Latch Disable Pulse Width (Note 7) fMAX Maximum Toggle Frequency VIN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 psRMS 0.5 5 ns The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V + = 5V, V – = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ Positive Supply Voltage Range ● 2.4 7 V V– Negative Supply Voltage Range (Note 3) ● –7 0 V VOS Input Offset Voltage (Note 4) ∆VOS/∆T Input Offset Voltage Drift IOS Input Offset Current RS = 50Ω, VCM = 0V RS = 50Ω, VCM = 0V RS = 50Ω, VCM = 5V RS = 50Ω, VCM = –5V 0.5 0.7 1 mV mV mV mV 10 µV/°C ● 0.2 3 6 µA µA –5 5 10 µA µA ● IB Input Bias Current (Note 5) VCM Input Voltage Range CMRR Common Mode Rejection Ratio – 5V ≤ VCM ≤ 5V PSRR+ Positive Power Supply Rejection Ratio 2.4V ≤ V + ≤ 7V, VCM = – 5V PSRR– Negative Power Supply Rejection Ratio 5.0 6.0 ● – 18 – 35 ● – 5.1 75 ● 61 58 dB dB 58 56 85 ● dB dB 60 58 80 ● dB dB – 7V ≤ V – ≤ 0V, VCM = 5V 5.1 V 3 LT1711/LT1712 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V + = 5V, V – = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS AV Small-Signal Voltage Gain VOH Output Voltage Swing HIGH (Note 8) IOUT = 1mA, VOVERDRIVE = 50mV IOUT = 10mA, VOVERDRIVE = 50mV ● ● VOL Output Voltage Swing LOW (Note 8) IOUT = – 1mA, VOVERDRIVE = 50mV IOUT = – 10mA, VOVERDRIVE = 50mV ● ● I+ Positive Supply Current (Per Comparator) VOVERDRIVE = 1V MIN TYP 1 15 V/mV 4.5 4.3 4.8 4.6 V V Negative Supply Current (Per Comparator) VOVERDRIVE = 1V 0.4 0.5 V V 17 22 30 mA mA 9 12 15 mA mA 0.8 V ● VIH Latch Pin High Input Voltage ● VIL Latch Pin Low Input Voltage ● IIL Latch Pin Current VLATCH = V+ tPD Propagation Delay (Notes 6, 11) ∆VIN = 100mV, VOVERDRIVE = 20mV ∆VIN = 100mV, VOVERDRIVE = 20mV ∆VIN = 100mV, VOVERDRIVE = 5mV 2.4 V ● ∆VIN = 100mV, VOVERDRIVE = 20mV UNITS 0.20 0.30 ● I– MAX 4.5 ● 15 µA 6.0 8.5 ns ns ns 1.5 ns 5.5 ∆tPD Differential Propagation Delay (Notes 6, 11) tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5 ns tSU Latch Setup Time (Note 7) 1 ns tH Latch Hold Time (Note 7) 0 ns tDPW Minimum Latch Disable Pulse Width (Note 7) 5 ns fMAX Maximum Toggle Frequency VIN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 psRMS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1711C/LT1712C are guaranteed to meet specified performance from 0°C to 70°C. They are designed, characterized and expected to meet specified performance from – 40°C to 85°C but are not tested or QA sampled at these temperatures. The LT1711I/LT1712I are guaranteed to meet specified performance from –40°C to 85°C. Note 3: The negative supply should not be greater than the ground pin voltage and the maximum voltage across the positive and negative supplies should not be greater than 12V. Note 4: Input offset voltage (VOS) is measured with the LT1711/LT1712 in a configuration that adds external hysteresis. It is defined as the average of the two hysteresis trip points. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: ∆tPD = tPD+ – tPD–. Load capacitance is 10pF. Due to test system requirements, the LT1711/LT1712 propagation delay is specified with a 1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V single supplies. Note 7: Latch propagation delay (tLPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the 4 0.5 interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width (tDPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs. Note 8: Output voltage swings are characterized and tested at V + = 5V and V – = 0V. They are guaranteed by design and correlation to meet these specifications at V – = – 5V. Note 9: The input voltage range is tested under the more demanding conditions of V + = 5V and V – = –5V. The LT1711/LT1712 are guaranteed by design and correlation to meet these specifications at V – = 0V. Note 10: The LT1711/LT1712 voltage gain is tested at V+ = 5V and V – = –5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is guaranteed by design and correlation. Note 11: The LT1711/LT1712 tPD is tested at V + = 5V and 2.7V with V – = 0V. Propagation delay at V + = 5V, V – = –5V is guaranteed by design and correlation. Note 12: Care must be taken to make sure that the LT1711/LT1712 do not exceed TJMAX when operating with ±5V supplies over the industrial temperature range. TJMAX is not exceeded for DC inputs, but supply current increases with switching frequency (see Typical Performance Characteristics). LT1711/LT1712 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Offset Voltage vs Temperature 2.0 1.0 VCM = 5V 0.5 VCM = 2.5V 0 VCM = 0V – 0.5 – 1.0 – 1.5 8 TA = 25°C V+ = 5V V – = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV 9 1.5 PROPAGATION DELAY (ns) 8 7 7 tPD+ tPD– 6 5 4 – 2.0 3 –25 50 0 75 25 TEMPERATURE (°C) 100 125 0 80 60 100 40 LOAD CAPACITANCE (pF) 20 171112 G01 5.0 tPD+ 4.5 4.0 TA = 25°C V – = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF 5.5 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 5.5 – tPD 3.5 5.0 tPD+ 4.5 tPD– 4.0 3.5 3.0 –1 0 1 3 4 5 2 INPUT COMMON MODE (V) 3.0 6 0 2 6 8 4 POSITIVE SUPPLY VOLTAGE (V) TA = 25°C V+ = 5V V – = 0V CLOAD = 10pF 30 20 10 0 0 10 20 30 40 50 SWITCHING FREQUENCY (MHz) 60 171112 G07 NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA) POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA) 40 V+ = 5V V – = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF 3 2 0 25 50 75 10 Positive Supply Current vs Positive Supply Voltage 25 V – = – 5V 15 10 5 ∆VIN = 100mV IOUT = 0mA 0 4 6 8 10 2 POSITIVE SUPPLY VOLTAGE (V) 0 8 6 4 I – AT –55°C I – AT 25°C I – AT 85°C 0 0 12 171112 G06 10 10 2 I+ AT –55°C I+ AT 25°C I+ AT 85°C Input Bias Current vs Input Common Mode Voltage V += 5V ∆VIN = 100mV IOUT = 0mA 12 V – = 0V 20 Negative Supply Current vs Negative Supply Voltage 14 125 100 171112 G03 171112 G05 171112 G04 Positive Supply Current vs Switching Frequency 4 TEMPERATURE (°C) Propagation Delay vs Positive Supply Voltage 6.0 TA = 25°C V+ = 5V V – = 0V VOD = 20mV VSTEP = 100mV CLOAD = 10pF tPD+ 5 171112 G02 Propagation Delay vs Input Common Mode Voltage 6.0 6 0 –50 –25 120 POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA) – 2.5 –50 tPD– 1 INPUT BIAS CURRENT (µA) INPUT OFFSET VOLTAGE (mV) 10 V+ = 5V V – = 0V PROPAGATION DELAY (ns) 2.5 Propagation Delay vs Temperature Propagation Delay vs Load Capacitance –6 –3 –4 –5 –1 –2 NEGATIVE SUPPLY VOLTAGE (V) –7 171112 G08 V + = 5V V – = 0V ∆VIN = 0mV 4 –2 –8 –14 –20 IB AT –55°C IB AT 25°C IB AT 125°C –1 3 2 4 0 1 5 INPUT COMMON MODE VOLTAGE (V) 6 171112 G09 5 LT1711/LT1712 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Bias Current vs Temperature –1 4.8 –2 –3 –4 –5 –6 4.7 4.6 4.5 4.4 4.3 4.2 –7 4.0 0 25 50 75 100 125 TEMPERATURE (°C) 0.9 0.8 0.1 V + = 5V V – = 0V ∆VIN = 100mV 0.7 0.6 0.5 0.4 0.3 0.2 VOH AT –55°C VOH AT 25°C VOH AT 125°C 4.1 –8 –50 –25 1.0 V + = 5V V – = 0V ∆VIN = 100mV 4.9 OUTPUT VOLTAGE (V) INPUT BIAS CURRENT (µA) 5.0 V+ = 5V V – = 0V VCM = 2.5V Output Low Voltage vs Sink Current OUTPUT VOLTAGE (V) 0 Output High Voltage vs Source Current VOL AT –55°C VOL AT 25°C VOL AT 125°C 0.1 1.0 10 SOURCE CURRENT (mA) 100 0 171112 G11 0.1 1.0 10 SINK CURRENT (mA) 100 171112 G12 171112 G10 Output Timing Jitter vs Switching Frequency 100 TA = 25°C V + = 5V V – = 0V VCM = 2.5V VIN = 630mVP-P (0dBm) SINE WAVE 90 OUTPUT TIMING JITTER (psRMS) Output Rising Edge, 5V Supply 80 70 60 VIN Output Falling Edge, 5V Supply VIN 50 Q 40 Q 30 30 171112 G14 10 0 0 20 60 40 FREQUENCY (MHz) 80 100 171112 G13 U U U PI FU CTIO S LT1711 V + (Pins 1): Positive Supply Voltage, Usually 5V. + IN (Pin 2): Noninverting Input. – IN (Pin 3): Inverting Input. V – (Pins 4): Negative Supply Voltage, Usually 0V or – 5V. LATCH ENABLE (Pin 5): Latch Enable Input. With a logic high, the output is latched. 6 GND (Pin 6): Ground Supply Voltage, Usually 0V. Q (Pin 7): Noninverting Output. Q (Pin 8): Inverting Output. 171112 G15 LT1711/LT1712 U U U PI FU CTIO S LT1712 – IN A (Pin 1): Inverting Input of A Channel Comparator. + IN A (Pin 2): Noninverting Input of A Channel Comparator. V – (Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins 3 and 6 should be connected together externally. V + (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins 4 and 5 should be connected together externally. + IN B (Pin 7): Noninverting Input of B Channel Comparator. – IN B (Pin 8): Inverting Input of B Channel Comparator. LATCH ENABLE B (Pin 9): Latch Enable Input of B Channel Comparator. With a logic high, the B output is latched. GND (Pin 10): Ground Supply Voltage of B Channel Comparator, Usually 0V. Q B (Pin 11): Noninverting Output of B Channel Comparator. Q B (Pin 12): Inverting Output of B Channel Comparator. Q A (Pin 13): Inverting Output of A Channel Comparator. Q A (Pin 14): Noninverting Output of A Channel Comparator. GND (Pin 15): Ground Supply Voltage of A Channel Comparator, Usually 0V LATCH ENABLE A (Pin 16): Latch Enable Input of A Channel Comparator. With a logic high, the A output is latched. U W U U APPLICATIO S I FOR ATIO Common Mode Considerations The LT1711/LT1712 are specified for a common mode range of – 5.1V to 5.1V on a ±5V supply, or a common mode range of – 0.1V to 5.1V on a single 5V supply. A more general consideration is that the common mode range is from 100mV below the negative supply to 100mV above the positive supply, independent of the actual supply voltage. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at 2.5V with a 5V supply voltage. As with any rail-to-rail differential input stage, the LT1711/LT1712 bias current flows into or out of the device depending upon the common mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of the LT1711/LT1712 comparators retain the input data (output latched) when their respective latch pin goes high. The latch pin will float to a low state when disconnected, but it is better to ground the 7 LT1711/LT1712 U W U U APPLICATIO S I FOR ATIO latch when a flow-through condition is desired. The latch pin is designed to be driven with either a TTL or CMOS output. It has built-in hysteresis of approximately 100mV, so that slow moving or noisy input signals do not impact latch performance. For the LT1712, if only one of the comparators is being used at a given time, it is best to latch the second comparator to avoid any possibility of interactions between the two comparators in the same package. High Speed Design Techniques The extremely fast speed of the LT1711/LT1712 necessitates careful attention to proper PC board layout and circuit design in order to prevent oscillations, as with most high speed comparators. The most common problem involves power supply bypassing which is necessary to maintain low supply impedance. Resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply voltages to move as the supply current changes. This movement of the supply voltages will often result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT1711/LT1712 supply pins. A good high frequency capacitor, such as a 1000pF ceramic, is recommended in parallel with larger capacitors, such as a 0.1µF ceramic and a 4.7µF tantalum in parallel. These bypass capacitors should be soldered to the output ground plane such that the return currents do not pass through the ground plane under the input circuitry. The common tie point for these two ground planes should be at the board ground connection. Such stargrounding and ground plane separation is extremely important for the proper operation of ultra high speed circuits. Poor trace routes and high source impedances are also common sources of problems. Keep trace lengths as short as possible and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, provide proper 8 termination impedances (typically 100Ω to 400Ω) to eliminate any reflections that may occur. Also keep source impedances as low as possible, preferably much less than 1kΩ. The input and output traces should also be isolated from one another. Power supply traces can be used to achieve this isolation as shown in Figure 1, a typical topside layout of the LT1712 on a multilayer PC board. Shown is the topside metal etch including traces, pin escape vias and the land pads for a GN16 LT1712 and its adjacent X7R 0805 bypass capacitors. The V +, V – and GND traces all shield the inputs from the outputs. Although the two V – pins are connected internally, they should be shorted together externally as well in order for both to function as shields. The same is true for the two V + pins. The two GND pins are not connected internally, but in most applications they are both connected directly to the ground plane. 171112 F01 Figure 1. Typical LT1712 Topside Metal for Multilayer PCB Layout Hysteresis Another important technique to avoid oscillations is to provide positive feedback, also known as hysteresis, from the output to the input. Increased levels of hysteresis, however, reduce the sensitivity of the device to input voltage levels, so the amount of positive feedback should be tailored to particular system requirements. The LT1711/LT1712 are completely flexible regarding the application of hysteresis, due to rail-to-rail inputs and the complementary outputs. Specifically, feedback resistors can be connected from one of the outputs to its corresponding input without regard to common mode considerations. Figure 2 shows several configurations. LT1711/LT1712 U W U U APPLICATIO S I FOR ATIO 100k 50k Q + VIN Q 50Ω LT1711 VIN+ + VIN – LT1711 VREF Q 50k VIN– – V + = 5V V – = –5V VHYST = 5mV (ALL 3 CASES) 50Ω 50Ω 50Ω Q + LT1711 – Q Q 100k 171112 F02 Figure 2. Various Configurations for Introducing Hysteresis U TYPICAL APPLICATIO S Simultaneous Full Duplex 75Mbaud Interface with Only Two Wires with a full ±3V (one whole VS up or down) of ground potential difference. The circuit of Figure 3 shows a simple, fully bidirectional, differential 2-wire interface that gives good results to 75Mbaud, using the LT1712. Eye diagrams under conditions of unidirectional and bidirectional communication are shown in Figures 4 and 5. Although not as pristine as the unidirectional performance of Figure␣ 4, the performance under simultaneous bidirectional operation is still excellent. Because the LT1712 input voltage range extends 100mV beyond both supply rails, the circuit works The circuit works well with the resistor values shown, but other sets of values can be used. The starting point is the characteristic impedance, ZO, of the twisted-pair cable. The input impedance of the resistive network should match the characteristic impedance and is given by: RIN = 2 • RO • R1||(R2 + R3) RO + 2 • [R1||(R2 + R3)] 750k 750k 3V 3V 4 + 14 1/2 LE LT1712 RxD 13 16 3 – 2 2 1 1 3V TxD 49.9Ω 8 – 3 3V 100k 7 + 14 1/2 LT1712 LE 15 750k 49.9Ω 4 + R2A 2.55k 5 100k R1C 499Ω R2C 2.55k 100k 3V 7 49.9Ω 1/2 LT1712 8 LE – 12 6 10 49.9Ω 5 + 11 11 1/2 LT1712 – LE 10 12 6 9 R3A 124Ω ROA 140Ω R3B 124Ω R1B 499Ω R2B 2.55k 6-FEET TWISTED PAIR ZO ≈ 120Ω DIODES: BAV99 ×4 16 13 750k 3V R1A 499Ω 15 RxD ROB 140Ω R3C 124Ω R1D 499Ω R3D 124Ω R2D 2.55k TxD 9 100k 171112 F03 Figure 3. 75Mbaud Full Duplex Interface on Two Wires 9 LT1711/LT1712 U TYPICAL APPLICATIO S 171112 F05 171112 F04 Figure 4. Performance of Figure 3’s Circuit When Operated Unidirectionally. Eye is Wide Open Figure 5. Performance When Operated Simultaneous Bidirectionally (Full Duplex). Crosstalk Appears as Noise. Eye is Slightly Shut But Performance is Still Excellent This comes out to 120Ω for the values shown. The Thevenin equivalent source voltage is given by: are often employed where slight variation of a stable carrier is required. This example is specifically intended to provide a 4 × NTSC sub-carrier tunable oscillator suitable for phase locking. This amounts to an attenuation factor of 0.0978 with the values shown. (The actual voltage on the lines will be cut in half again due to the 120Ω ZO.) The reason this attenuation factor is important is that it is the key to deciding the ratio between the R2-R3 resistor divider in the receiver path. This divider allows the receiver to reject the large signal of the local transmitter and instead sense the attenuated signal of the remote transmitter. Note that in the above equations, R2 and R3 are not yet fully determined because they only appear as a sum. This allows the designer to now place an additional constraint on their values. The R2-R3 divide ratio should be set to equal half the attenuation factor mentioned above or: R3/R2 = 1/2 • 0.09761. Having already designed R2 + R3 to be 2.653k (by allocating input impedance across RO, R1 and R2 + R3 to get the requisite 120Ω), R2 and R3 then become 2529Ω and 123.5Ω respectively. The nearest 1% value for R2 is 2.55k and that for R3 is 124Ω. Voltage-Tunable Crystal Oscillator The front page application is a variant of a basic crystal oscillator that permits voltage tuning of the output frequency. Such voltage-controlled crystal oscillators (VCXO) 10 The LT1711 is set up as a crystal oscillator. The varactor diode is biased from the tuning input. The tuning network is arranged so a 0V to 5V drive provides a reasonably symmetric, broad tuning range around the 14.31818MHz center frequency. The indicated selected capacitor sets tuning bandwidth. It should be picked to complement loop response in phase locking applications. Figure 6 is a plot of tuning input voltage versus frequency deviation. Tuning deviation from the 4 × NTSC 14.31818MHz center frequency exceeds ±240ppm for a 0V to 5V input. 1 Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k + 124Ω = 2.674k. 9 14.3217MHz 8 FREQUENCY DEVIATION (kHz) (R2 + R3 – R1) (R2 + R3 + R1) RO • RO + 2 • [R1||(R2 + R3)] VTH = VS • 7 6 5 14.31818MHz 4 3 2 1 14.3140MHz 0 0 1 3 2 INPUT VOLTAGE (V) 5 4 171112 F06 Figure 6. Control Voltage vs Output Frequency for the Front Page Application Circuit. Tuning Deviation from Center Frequency Exceeds ±240ppm LT1711/LT1712 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 7 6 5 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) 1 2 3 4 0.043 (1.10) MAX 0.007 (0.18) 0.034 (0.86) REF 0° – 6° TYP SEATING PLANE 0.021 ± 0.006 (0.53 ± 0.015) 0.009 – 0.015 (0.22 – 0.38) 0.005 ± 0.002 (0.13 ± 0.05) 0.0256 (0.65) BSC MSOP (MS8) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 2 3 4 5 6 7 0.053 – 0.068 (1.351 – 1.727) 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. GN16 (SSOP) 1098 11 LT1711/LT1712 U TYPICAL APPLICATIO 1MHz Series Resonant Crystal Oscillator with Square and Sinusoid Outputs Figure 7 shows a classic 1MHz series resonant crystal oscillator. At series resonance, the crystal is a low impedance and the positive feedback connection is what brings about oscillation at the series resonant frequency. The RC feedback around the other path ensures that the circuit does not find a stable DC operating point and refuse to oscillate. The comparator output is a 1MHz square wave (top trace of Figure 8) with jitter measured at better than 28psRMS on a 5V supply and 40psRMS on a 3V supply. At Pin 2 of the comparator, on the other side of the crystal, is a clean sine wave except for the presence of the small high R10 1k C5 100pF R1 1k R2 1k C3 100pF R7 15.8k 3V/DIV VS 2 3 – VS 1 + 7 LT1711 LE 5 6 Amplitude will be a linear function of comparator output swing, which is supply dependent and therefore adjustable. The important difference here is that any added amplitude stabilization or control loop will not be faced with the classical task of avoiding regions of nonoscillation versus clipping. R6 162Ω 1MHz AT-CUT R4 210Ω VS 2 C4 100pF R5 6.49k frequency glitch (middle trace of Figure 8). This glitch is caused by the fast edge of the comparator output feeding back through crystal capacitance. Amplitude stability of the sine wave is maintained by the fact that the sine wave is basically a filtered version of the square wave. Hence, the usual amplitude control loops associated with sinusoidal oscillators are not necessary.2 The sine wave is filtered and buffered by the fast, low noise LT1806 op amp. To remove the glitch, the LT1806 is configured as a bandpass filter with a Q of 5 and unity-gain center frequency of 1MHz, with its output shown as the bottom trace of Figure␣ 8. Distortion was measured at – 70dBc and – 60dBc on the second and third harmonics, respectively. 4 SQUARE R9 2k 8 VS R3 1k C2 0.1µF 2 – 7 6 LT1806S8 3 + R8 2k 1V/DIV SINE 1 4 1V/DIV 171112 F07 C1 0.1µF 200ns/DIV Figure 7. LT1711 Comparator is Configured as a Series Resonant Xtal Oscillator. LT1806 Op Amp is Configured in a Q = 5 Bandpass with fC = 1MHz 171112 F08 Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is Xtal Feedback to Pin 2 at LT1711 (Note the Glitches). Bottom is Buffered, Inverted and Bandpass Filtered with a Q = 5 by LT1806 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator LT1116 12ns Single Supply Ground Sensing Comparator Single Supply Version of the LT1016 LT1394 7ns, UltraFast Single Supply Comparator 6mA Single Supply Comparator LT1671 60ns, Low Power, Single Supply Comparator 450µA Single Supply Comparator LT1713/LT1714 Single/Dual 7ns, Low Power, 3V/5V/±5V, R-R Comparator 7ns/5mA versions of the LT1711/LT1712 LT1719 4.5ns, Single Supply 3V/5V/±5V Comparator 4mA Comparator with Rail-to-Rail Outputs and Level Shifting LT1720/LT1721 Dual/Quad, 4.5ns, Single Supply Comparator Dual/Quad Version of the LT1719 12 Linear Technology Corporation 171112f LT/TP 0401 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2001