Final Electrical Specifications LT1940 Dual Monolithic 1.4A, 1.1MHz Step-Down Switching Regulator August 2002 DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ The LT®1940 is a dual current mode PWM step-down DC/DC converter with internal 2A power switches. Both converters are synchronized to a single 1.1MHz oscillator and run with opposite phases, reducing input ripple current. The output voltages are set with external resistor dividers, and each regulator has independent shutdown and soft-start circuits. Each regulator generates a powergood signal when its output is in regulation, easing power supply sequencing and interfacing with microcontrollers and DSPs. Wide Input Voltage Range: 3.6V to 25V Two 1.4A Output Switching Regulators with Internal Power Switches Small 16-Lead TSSOP Surface Mount Package Constant 1.1MHz Switching Frequency Anti-Phase Switching Reduces Ripple Independent Shutdown/Soft-Start Pins Independent Power Good Indicators Ease Supply Sequencing Uses Small Inductors and Ceramic Capacitors U APPLICATIO S ■ ■ ■ ■ ■ ■ The LT1940’s 1.1MHz switching frequency allows the use of tiny inductors and capacitors, resulting in a very small dual 1.4A output solution. Constant frequency and ceramic capacitors combine to produce low, predictable output ripple voltage. With its wide input range of 3.6V to 25V, the LT1940 regulates a wide variety of power sources, from 4-cell batteries and 5V logic rails to unregulated wall transformers, lead acid batteries and distributed-power supplies. A current mode PWM architecture provides fast transient response with simple compensation components and cycle-by-cycle current limiting. Frequency foldback and thermal shutdown provide additional protection. Disk Drives DSP Power Supplies Wall Transformer Regulation Distributed Power Regulation DSL Modems Cable Modems , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO VIN 7V TO 25V Efficiency vs Load Current 4.7µF VIN CMDSH-3 BOOST1 CMDSH-3 0.1µF 3.3µH EFFICIENCY (%) UPS140 UPS140 16.5k 10µF 90 4.7µH SW2 SW1 10.0k VIN = 12V OUT2 5V 1.4A BOOST2 LT1940 0.1µF OUT1 3.3V 1.4A 100 30.1k 15k 330pF 1nF FB1 FB2 VC1 VC2 RUN/SS1 PG1 RUN/SS2 PG2 GND 15k 330pF 10µF 10.0k VOUT = 5V 80 VOUT = 3.3V 70 100k 60 1940 F01 POWER GOOD 0 0.5 1.0 LOAD CURRENT (A) Figure 1. 3.3V and 5V Dual Output Step-Down Converter with Output Sequencing 1.5 1940 F01b 1940i Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LT1940 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) VIN Voltage .................................................. (–0.3), 25V BOOST Pin Voltage .................................................. 35V BOOST Pin Above SW Pin ....................................... 25V PG Pin Voltage ......................................................... 25V SHDN, FB Pins ........................................................... 6V SW Voltage ................................................................VIN Maximum Junction Temperature .......................... 125°C Operating Temperature Range (Note 2) ...–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW BOOST1 1 16 FB1 SW1 2 15 VC1 VIN 3 14 PG1 VIN 4 13 RUN/SS1 VIN 5 12 RUN/SS2 VIN 6 11 PG2 SW2 7 10 VC2 BOOST2 8 9 LT1940EFE FB2 FE PACKAGE 16-LEAD PLASTIC TSSOP UNDERSIDE METAL MUST BE SOLDERED TO GROUND TJMAX = 125°C, θJA = 45°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VBOOST = 8V unless otherwise noted. (Note 2) PARAMETER CONDITIONS Minimum Operating Voltage MIN ● TYP MAX UNITS 3.4 3.6 V Quiescent Current Not Switching 3.8 4.8 mA Shutdown Current VRUNSS = 0V 30 45 µA 1.250 1.250 1.250 1.270 1.270 1.270 V V V 240 1200 nA Feedback Voltage 0°C to 70°C –40°C to 85°C FB Pin Bias Current Reference Line Regulation ● ● 1.230 1.225 1.215 ● VIN 5V to 25V 0.005 Error Amp GM 330 Error Amp Voltage Gain 180 %/V uMhos VC Source Current VFB = 1V 42 µA VC Sink Current VFB = 1.5V 60 µA VC Pin to Switch Current Gain 2.4 A/V VC Switching Threshold 0.75 V VC Clamp Voltage 1.8 V Switching Frequency VFB = 1.1V ● Switching Phase Maximum Duty Cycle ● 1 0.95 1.1 1.1 1.25 1.35 MHz MHz 150 180 210 Deg 78 88 % Frequency Shift Threshold on FB fSW = 1MHz 0.5 V Foldback Frequency VFB = 0V 150 kHz Switch Current Limit Note 3 Switch VCESAT ISW = 1A Switch Leakage Current 1.8 2.4 3.2 A 210 320 mV 10 µA 1940i 2 LT1940 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VBOOST = 8V unless otherwise noted. (Note 2) PARAMETER CONDITIONS TYP MAX UNITS Minimum Boost Voltage ISW = 1A MIN 1.8 2.5 V Boost Pin Current ISW = 1A 20 30 mA 2.3 µA 0.3 0.6 V 90 125 160 RUN/SS Current RUN/SS Threshold PG Threshold Offset VFB Rising mV PG Voltage Output Low VFB = 1.25V, IPG = 250µA 0.22 0.4 V PG Pin Leakage VPG = 2V 0.1 1 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1940E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at high duty cycle. U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency, VOUT = 3.3V Efficiency, VOUT = 1.8V 90 VOUT = 1.8V L = 2.2µH (SUMIDA CR43-2R2) VOUT = 5V L = 4.7µH (SUMIDA CR43-4R7) VOUT = 3.3V L = 3.3µH (SUMIDA CR43-3R3) 90 80 90 VIN = 5V 70 EFFICIENCY (%) VIN = 5V EFFICIENCY (%) EFFICIENCY (%) Efficiency, VOUT = 5V 100 100 80 VIN = 12V 70 VIN = 18V VIN = 8V 80 VIN = 12V VIN = 18V 70 60 60 50 0 50 1.5 0.5 1.0 LOAD CURRENT (A) 60 0 1.5 0.5 1.0 LOAD CURRENT (A) Maximum Load Current, VOUT = 1.8V L = 1µH 1.2 L = 4.7µH SWITCH VOLTAGE (mV) L = 1.5µH L = 3.3µH 1.4 L = 2.2µH 1.2 0 2 4 8 10 12 6 INPUT VOLTAGE (V) 14 16 1940 G04 1.0 B 400 1.6 LOAD CURRENT (A) LOAD CURRENT (A) Switch VCESAT 1.8 1.6 1.0 1940 G03 Maximum Load Current, VOUT = 3.3V 1.8 1.4 1.5 1940 G02 1940 G01 L = 2.2µH 0.5 1.0 LOAD CURRENT (A) 0 0 5 15 10 INPUT VOLTAGE (V) 20 25 300 200 100 0 0 0.5 1.0 1.5 2.0 SW CURRENT (A) 1940 G05 1940 G06 1940i 3 LT1940 U W TYPICAL PERFOR A CE CHARACTERISTICS VOUT vs Temperature Current Limit vs Duty Cycle Boost Pin Current 40 3.40 3.0 CHANNEL 1, FIGURE 1, VIN = 12V 20 TYPICAL 3.35 2.0 VOUT (V) CURRENT LIMIT (A) BOOST CURRENT (mA) 2.5 30 MINIMUM 1.5 3.30 1.0 10 3.25 0.5 0 0 0 1.0 1.5 0.5 SWITCH CURRENT (A) 20 0 2.0 60 40 DUTY CYCLE (%) 80 Frequency vs Temperature 3.0 1.2 2.5 1.0 0.8 0.6 0.4 100 75 125 100 125 2.0 1.5 1.0 0.5 0.2 0 75 0 25 50 TEMPERATURE (°C) 50 IRUN/SS vs Temperature 1.4 RUN/SS CURRENT (µA) SWITCHING FREQUENCY (MHz) FREQUENCY (MHz) 1.0 25 1940 G09 Frequency Foldback 1.1 0 1940 G08 1.3 1.2 –25 TEMPERATURE (°C) 1940 G07 0.9 –50 –25 3.20 –50 100 0 0.2 0.4 0.6 0.8 1.0 FEEDBACK VOLTAGE (V) 1.2 1940 G11 1940 G10 0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 1940 G12 RUN/SS Thresholds vs Temperature 1.4 RUNN/SS THRESHOLDS (V) 1.2 1.0 TO SWITCH 0.8 0.6 TO RUN 0.4 0.2 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1940 G13 1940i 4 LT1940 U U U PI FU CTIO S BOOST1, BOOST2 (Pins 1, 8): The BOOST pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar NPN power switches.Tie through a diode from VOUT or from VIN. SW1, SW2 (Pins 2, 7): The SW pins are the outputs of the internal power switches. Connect these pins to the inductors, catch diodes and boost capacitors. VIN (Pins 3, 4, 5, 6): The VIN pins supply current to the LT1940’s internal regulator and to the internal power switches. These pins must be tied to the same source, and must be locally bypassed. FB1, FB2 (Pins 9, 16): The LT1940 regulates each feedback pin to 1.25V. Connect the feedback resistor divider taps to these pins. VC1, VC2 (Pins 10, 15): The VC pins are the outputs of the internal error amps. The voltages on these pins control the peak switch currents. These pins are normally used to compensate the control loops, but can also be used to override the loops. Pull these pins to ground with an open drain to shut down each switching regulator. PG1, PG2 (Pins 11, 14): The Power Good pins are the open collector outputs of an internal comparator. PG remains low until the FB pin is within 10% of the final regulation voltage. As well as indicating output regulation, the PG pins can be used to sequence the two switching regulators. These pins can be left unconnected. The PG outputs are valid when VIN is greater than 2.4V and either of the RUN/SS pins is high. The PG comparators are disabled in shutdown. RUN/SS1, RUN/SS2 (Pins 12, 13): The RUN/SS pins are use to shut down the individual switching regulators and the internal bias circuits. They also provide a soft-start function. To shut down either regulator, pull the RUN/SS pin to ground with an open drain or collector. Tie a capacitor from these pins to ground to limit switch current during start-up. If neither feature is used, leave these pins unconnected. GND (Underside Metal): The underside exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The underside must be soldered to the circuit board for proper operation. 1940i 5 LT1940 W BLOCK DIAGRA VIN 2µA RUN/SS2 INT REG AND REF MASTER OSC CLK1 CLK2 2µA RUN/SS1 VIN IN CIN 0.9V ∑ SLOPE R S C1 BOOST D2 Q SLAVE OSC CLK C3 SW L1 OUT + ERROR AMP 0.5V VC FB R1 – – C1 D1 R2 + CF – RC 1.25V CC RUN/SS + 125mV ILIMIT CLAMP PG + GND 1940 F02 – Figure 2. Block Diagram of the LT1940 with Associated External Components (One of Two Switching Regulators Shown) The LT1940 is a dual, constant frequency, current mode buck regulator with internal 2A power switches. The two regulators share common circuitry including input source, voltage reference and oscillator, but are otherwise independent. This section describes the operation of the LT1940; refer to the Block Diagram. If the RUN/SS (run/soft-start) pins are both tied to ground, the LT1940 is shut down and draws 30µA from the input source tied to VIN. Internal 2µA current sources charge external soft-start capacitors, generating voltage ramps at these pins. If either RUN/SS pin exceeds 0.5V, the internal bias circuits turn on, including the internal regulator, 1.25V reference and 1.1MHz master oscillator. In this state, the LT1940 draws 3.5mA from VIN, whether one or both RUN/SS pins are high. Neither switching regulator will begin to operate until its RUN/SS pin reaches ~0.8V. 1940i 6 LT1940 W BLOCK DIAGRA The master oscillator generates two clock signals of opposite phase. The two switchers are current mode step-down regulators. This means that instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. This current mode control improves loop dynamics and provides cycle-by-cycle current limit. The Block Diagram shows only one of the two switching regulators. A pulse from the slave oscillator sets the RS flip-flop and turns on the internal NPN bipolar power switch. Current in the switch and the external inductor begins to increase. When this current exceeds a level determined by the voltage at VC, current comparator C1 resets the flip-flop, turning off the switch. The current in the inductor flows through the external Schottky diode, and begins to decrease. The cycle begins again at the next pulse from the oscillator. In this way the voltage on the VC pin controls the current through the inductor to the output. The internal error amplifier regulates the output voltage by continually adjusting the VC pin voltage. The threshold for switching on the VC pin is 0.8V, and an active clamp of 1.8V limits the output current. The VC pin is also clamped to the RUN/SS pin voltage. As the internal current source charges the external soft-start capacitor, the current limit increases slowly. Each switcher contains an independent oscillator. This slave oscillator is normally synchronized to the master oscillator. However, during start-up, short-circuit or overload conditions, the FB pin voltage will be near zero and an internal comparator gates the master oscillator clock signal. This allows the slave oscillator to run the regulator at a lower frequency. This frequency foldback behavior helps to limit switch current and power dissipation under fault conditions. The switch driver operates from either the input or from the BOOST pin. An external capacitor and diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to fully saturate the internal bipolar NPN power switch for efficient operation. A power good comparator trips when the FB pin is at 90% of its regulated value. The PG output is an open collector transistor that is off when the output is in regulation, allowing an external resistor to pull the PG pin high. Power good is valid when the LT1940 is enabled (either RUN/SS pin is high) and VIN is greater than ~2.4V. U W U U APPLICATIO S I FOR ATIO FB Resistor Network The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: R1 = R2(VOUT/1.25 – 1) R2 should be 10.0kΩ or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure␣ 2. Input Voltage Range The minimum input voltage is determined by either the LT1940’s minimum operating voltage of ~3.5V, or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC = (VOUT + VD)/(VIN – VSW + VD) where VD is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.3V at maximum load). This leads to a minimum input voltage of: VINMIN = (VOUT + VD)/DCMAX - VD + VSW with DCMAX = 0.78. 1940i 7 LT1940 U W U U APPLICATIO S I FOR ATIO The maximum input voltage is determined by the absolute maximum ratings of the VIN and BOOST pins and by the minimum duty cycle DCMIN = 0.15: VINMAX = (VOUT + VD)/DCMIN – VD + VSW. This limits the maximum input voltage to ~14V with VOUT = 1.8V and ~19V with VOUT = 2.5V. Note that this is a restriction on the operating input voltage; the circuit will tolerate transient inputs up to the absolute maximum rating. Inductor Selection and Maximum Output Current A good first choice for the inductor value is: L = (VOUT + VD)/1.2 where VD is the voltage drop of the catch diode (~0.4V) and L is in µH. With this value the maximum load current will be ~1.4A, independent of input voltage. The inductor’s RMS current rating must be greater than your maximum load current and its saturation current should be about 30% higher. To keep efficiency high, the series resistance (DCR) should be less than 0.1Ω. Table 1 lists several vendors and types that are suitable. Of course, such a simple design guide will not always result in the optimum inductor for your application. A larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. If your load is lower than 1.4A, then you can decrease the value of the inductor and operate with higher ripple current. This allows you to use a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. Be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. There are several graphs in the Typical Performance Characteristics section of this data sheet that show the maximum load current as a function of input voltage and inductor value for several popular output voltages. Also, low inductance may result in discontinuous mode operation, which is okay, but further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology Application Note 44. Finally, for duty cycles greater than 50% (VOUT/VIN < 0.5), there is a minimum inductance required to avoid subharmonic oscillations. See AN19. The discussion below assumes continuous inductor current. The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-topeak inductor ripple current. The LT1940 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT1940 will deliver depends on the current limit, the inductor value, and the input and output voltages. L is chosen based on output current requirements, output voltage ripple requirements, size restrictions and efficiency goals. When the switch is off, the inductor sees the output voltage plus the catch diode drop. This gives the peak-topeak ripple current in the inductor: ∆IL = (1 – DC)(VOUT + VD)/(L • f) where f is the switching frequency of the LT1940 and L is the value of the inductor. The peak inductor and switch current is ISWPK = ILPK = IOUT + ∆IL/2. To maintain output regulation, this peak current must be less than the LT1940’s switch current limit ILIM. ILIM is at least 1.8A at low duty cycle and decreases linearly to 1.5A at DC = 0.8. The maximum output current is a function of the chosen inductor value: IOUTMAX = ILIM – ∆IL/2 = 1.8A • (1 – 0.21 • DC) – ∆IL/2 If the inductor value is chosen so that the ripple current is small, then the available output current will be near the switch current limit. One approach to choosing the inductor is to start with the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. Then use these equations to check that the LT1940 will be able to deliver the required output current. Note again that these equations assume that the inductor current is continuous. Discontinuous operation occurs when IOUT is less than ∆IL/2 as calculated above. 1940i 8 LT1940 U W U U APPLICATIO S I FOR ATIO Table 1. Inductors. Part Number Value (µH) ISAT (A) DC DCR (Ω) Height (mm) CR43-1R4 1.4 2.52 0.056 3.5 CR43-2R2 2.2 1.75 0.071 3.5 CR43-3R3 3.3 1.44 0.086 3.5 CR43-4R7 4.7 1.15 0.109 3.5 CDRH3D16-1R5 1.5 1.55 0.040 1.8 CDRH3D16-2R2 2.2 1.20 0.050 1.8 CDRH3D16-3R3 3.3 1.10 0.063 1.8 CDRH4D28-3R3 3.3 1.57 0.049 3.0 CDRH4D28-4R7 4.7 1.32 0.072 3.0 CDRH5D28-5R3 5.3 1.9 0.028 3.0 CDRH5D18-4R1 4.1 1.95 0.042 2.0 DO1606T-152 1.5 2.10 0.060 2.0 DO1606T-222 2.2 1.70 0.070 2.0 DO1606T-332 3.3 1.30 0.100 2.0 DO1606T-472 4.7 1.10 0.120 2.0 DO1608C-152 1.5 2.60 0.050 2.9 DO1608C-222 2.2 2.30 0.070 2.9 DO1608C-332 3.3 2.00 0.080 2.9 DO1608C-472 4.7 1.50 0.090 2.9 1812PS-222M 2.2 1.7 0.070 3.81 1008PS-182M 1.8 2.1 0.090 2.74 LQH3C1R0M24 1.0 1.00 0.078 2.2 LQH3C2R2M24 2.2 0.79 0.126 2.2 LQH4C1R5M04 1.5 1.00 0.090 2.8 LQH4C2R2M04 2.2 0.90 0.110 2.8 LQH4C3R3M04 3.3 0.80 0.130 2.8 Sumida Coilcraft Murata Input Capacitor Selection Bypass the input of the LT1940 circuit with a 4.7µF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT1940 and to force this very high frequency switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency to do this effectively, and it must have an adequate ripple current rating. With two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor RMS current is not simple. However, a conservative value is the RMS input current for the channel that is delivering most power (VOUT • IOUT). This is given by: CINRMS = IOUT √[VOUT • (VIN – VOUT)]/VIN < IOUT/2 and is largest when VIN = 2VOUT (50% duty cycle). As the second, lower power channel draws input current, the input capacitor’s RMS current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. Considering that the maximum load current from a single channel is ~1.4A, RMS ripple current will always be less than 0.7A. The high frequency of the LT1940 reduces the energy storage requirements of the input capacitor, so that the capacitance required is less than 10µF. The combination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors make them the preferred choice. The low ESR results in very low voltage ripple and the capacitors can handle plenty of ripple current. They are also comparatively robust and can be used in this application at their rated voltage. X5R and X7R types are stable over temperature and applied voltage, and give dependable service. Other types (Y5V and Z5U) have very large temperature and voltage coefficients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. While they will still handle the RMS ripple current, the input voltage ripple may become fairly large, and the ripple current may end up flowing from your input supply or from other bypass capacitors in your system, as opposed to being fully sourced from the local input capacitor. An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1µF ceramic capacitor in parallel with a low-ESR tantalum capacitor. For the electrolytic capacitor, a value larger than 10µF will be required to meet the ESR and ripple current requirements. Because the input capacitor 1940i 9 LT1940 U W U U APPLICATIO S I FOR ATIO is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor. Be sure to place the 1µF ceramic as close as possible to the VIN and GND pins on the IC for optimal noise immunity. A final caution is in order regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the LT1940. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. For details, see AN88. Output Capacitor Selection For 5V and 3.3V outputs with greater than 1A output, a 10µF 6.3V ceramic capacitor (X5R or X7R) at the output results in very low output voltage ripple and good transient response. For lower voltages, 10µF is adequate but increasing COUT to 15µF or 22µF will improve transient performance. Other types and values can be used; the following discusses tradeoffs in output ripple and transient performance. The output capacitor filters the inductor current to generate an output with low voltage ripple. It also stores energy in order satisfy transient loads and to stabilize the LT1940’s control loop. Because the LT1940 operates at a high frequency, you don’t need much output capacitance. Also, the current mode control loop doesn’t require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. Estimate output ripple with the following equations: VRIPPLE = ∆IL/(8f COUT) for ceramic capacitors, and VRIPPLE = ∆IL ESR for electrolytic capacitors (tantalum and aluminum); where ∆IL is the peak-to-peak ripple current in the inductor. The RMS content of this ripple is very low, and the RMS current rating of the output capacitor is usually not of concern. Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. For a 5% overshoot, this requirement becomes COUT > 10L(ILIM/VOUT)^2. Finally, there must be enough capacitance for good transient performance. The last equation gives a good starting point. Alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. This topic is covered more thoroughly in the section on loop compensation. The high performance (low ESR), small size and robustness of ceramic capacitors make them the preferred type for LT1940 applications. However, all ceramic capacitors are not the same. As mentioned above, many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. In particular, Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and temperature extremes. Because the loop stability and transient response depend on the value of COUT, you may not be able to tolerate this loss. Use X7R and X5R types. You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer, lower ESR organic electrolytic capacitors intended for power supply use are suitable, and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may give better transient response for large changes in load current. Table 2 lists several capacitor vendors. 1940i 10 LT1940 U U W U APPLICATIO S I FOR ATIO Table 2. Low-ESR Surface Mount Capacitors Boost Pin Considerations Vendor Type Series Taiyo Yuden Ceramic X5R, X7R AVX Ceramic X5R, X7R Tantalum TPS Kemet Tantalum Ta Organic Al Organic T491,T494,T495 T520 A700 Sanyo Ta or Al Organic POSCAP Panasonic Al Organic SP CAP TDK Ceramic X5R, X7R Catch Diode Use a 1A Schottky diode for the catch diode (D1 in Figure 2). The diode must have a reverse voltage rating greater than the maximum input voltage. The ON Semiconductor MBRM120LT3 (20V) and MBRM130LT3 (30V) are good choices; they have a tiny package with good thermal properties. Many vendors have surface mount versions of the 1N5817 (20V) and 1N5818 (30V) 1A Schottky diodes such as the Microsemi UPS120 that are suitable. The capacitor and diode tied to the BOOST pin generate a voltage that is higher than the input voltage. In most cases a 0.1µF capacitor and fast switching diode (such as the CMDSH-3 or FMMD914) will work well. Figure 3 shows three ways to arrange the boost circuit. The BOOST pin must be more than 2.5V above the SW pin for full efficiency. For outputs of 3.3V and higher the standard circuit (Figure 3a) is best. For outputs between 2.8V and 3.3V, use a small Schottky diode (such as the BAT-54). For lower output voltages the boost diode can be tied to the input (Figure␣ 3b). The circuit in Figure 3a is more efficient because the BOOST pin current comes from a lower voltage source. Finally, as shown in Figure 3c, the anode of the boost diode can be tied to another source that is at least 3V. For example, if you are generating 3.3V and 1.8V and the 3.3V is on whenever the 1.8V is on, the 1.8V boost diode can be connected to the 3.3V output. In any case, you must also be sure that the maximum voltage at the BOOST pin is less than the maximum specified in the Absolute Maximum Ratings section. D2 D2 C3 BOOST VIN VIN VOUT SW VIN VIN SW VBOOST – VSW ≅ VIN MAX VBOOST ≅ 2VIN VBOOST – VSW ≅ VOUT MAX VBOOST ≅ VIN + VOUT (3b) (3a) D2 D2 VIN2 >VIN + 3V VIN2 > 3V BOOST BOOST C3 LT1940 VIN VOUT GND GND VIN C3 BOOST LT1940 LT1940 LT1940 SW VOUT VIN VIN GND SW VOUT GND 1940 F03 VBOOST – VSW ≅ VIN2 MAX VBOOST ≅ VIN2 + VIN MINIMUM VALUE FOR VIN2 = 3V 1940 F03 MAX VBOOST – VSW ≅ VIN2 MAX VBOOST ≅ VIN2 MINIMUM VALUE FOR VIN2 = VIN + 3V (3c) (3d) Figure 3. Generating the Boost Voltage 1940i 11 LT1940 U W U U APPLICATIO S I FOR ATIO bit complicated and the best values depend on the application and in particular the type of output capacitor. A practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. The boost circuit can also run directly from a DC voltage that is higher than the input voltage by more than 3V, as in Figure 3d. The diode is used to prevent damage to the LT1940 in case VIN2 is held low while VIN is present. The circuit saves several components (both BOOST pins can be tied to D2). However, efficiency may be lower and dissipation in the LT1940 may be higher. Also, if VIN2 is absent, the LT1940 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because the switch will not be able to saturate, dropping 1.5V to 2V in conduction. Figure 5 shows an equivalent circuit for the LT1940 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that the output capacitor integrates this current, and that the capacitor on the VC pin (CC) integrates the error amplifier output current, resulting in two poles in the loop. In most cases a zero is required and comes from either the output capacitor ESR or from a resistor in series with CC. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. A phase lead capacitor (CPL) across the feedback divider may improve the transient response. Frequency Compensation The LT1940 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT1940 does not require the ESR of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. Frequency compensation is provided by the components tied to the VC pin. Generally a capacitor and a resistor in series to ground determine loop gain. In addition, there is a lower value capacitor in parallel. This capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. Loop compensation determines the stability and transient performance. Designing the compensation network is a LT1940 CURRENT MODE POWER STAGE gm = 2.5mho VSW OUTPUT ERROR AMPLIFIER R1 CPL FB – gm = 340µmho + 500k GND 1.25V VC ESR + C1 C1 R2 RC CF POLYMER OR TANTALUM CERAMIC CC 1940 F05 Figure 5. Model for Loop Response 1940i 12 LT1940 U U W U APPLICATIO S I FOR ATIO Soft-Start and Shutdown The RUN/SS (Run/Soft-Start) pins are used to place the individual switching regulators and the internal bias circuits in shutdown mode. They also provide a soft-start function. To shut down either regulator, pull the RUN/SS pin to ground with an open-drain or collector. If both RUN/SS pins are pulled to ground, the LT1940 enters its shutdown mode with both regulators off and quiescent current reduced to ~30µA. Internal 2µA current sources pull up on each pin. If either pin reaches ~0.5V, the internal bias circuits start and the quiescent current increases to ~3.5mA. If a capacitor is tied from the RUN/SS pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. This voltage clamps the VC pin, limiting the peak switch current and therefore input current during start up. A good value for the soft-start capacitor is COUT/10,000, where COUT is the value of the output capacitor. The RUN/SS pins can be left floating if the shutdown feature is not used. They can also be tied together with a single capacitor providing soft-start. The internal current sources will charge these pins to ~2.5V. Power Good Indicators and Output Sequence The PG pin is the open collector output of an internal comparator. PG remains low until the FB pin is within 10% of the final regulation voltage. Tie the PG pin to any supply with a pull-up resistor that will supply less than 250µA. Note that this pin will be open when the LT1940 is placed in shutdown mode (both RUN/SS pins at ground) regardless of the voltage at the FB pin. Power good is valid when the LT1940 is enabled (either RUN/SS pin is high) and VIN is greater than ~2.4V. The PG pin can be used to sequence the two switching regulators. The circuit in Figure 6 provides soft-start and sequencing with the fewest components. PG1 is tied to VC2, preventing switcher 2 from operating until output 1 is in regulation. A single capacitor provides the soft-start ramp for both regulators. Shorted Input Protection If the inductor is chosen so that it won’t saturate excessively, the LT1940 will tolerate a shorted output. There is another situation to consider in systems where the output will be held high when the input to the LT1940 is absent. If the VIN and one of the RUN/SS pins are allowed to float, then the LT1940’s internal circuitry will pull its quiescent current through its SW pin. This is fine if your system can tolerate a few mA of load in this state. With both RUN/SS pins grounded, the LT1940 enters shutdown mode and the SW pin current drops to ~30µA. However, if the VIN pin is grounded while the output is held high, then parasitic diodes inside the LT1940 can pull large currents from the output through the SW pin and the VIN pin. A Schottky diode in series with the input to the LT1940 will protect the LT1940 and the system from a shorted or reversed input. VOUT2 PARASITIC DIODE PG2 OFF ON RUN/SS1 VC2 RUN/SS2 PG1 POWER GOOD D4 VIN VIN SW VOUT LT1940 GND 1940 F07 1940 F06 Figure 6. The Power Good Comparator can be used to Sequence the Two Regulators. Switcher 1 will Start First. Figure 7.Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output. 1940i 13 LT1940 U U W U APPLICATIO S I FOR ATIO PCB Layout Thermal Considerations For proper operation and minimum EMI, care must be taken during printed circuit board (PCB) layout. Figure 8 shows the high-di/dt paths in the buck regulator circuit. Note that large, switched currents flow in the power switch, the catch diode and the input capacitor. The loop formed by these components should be as small as possible. These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. Place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor C2. Additionally, the SW and BOOST nodes should be kept as small as possible. Figure 9 shows recommended component placement with trace and via locations. The PCB must also provide heat sinking to keep the LT1940 cool. The exposed metal on the bottom of the package must be soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the LT1940. Place additional vias near the catch diodes. Adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to θJA = 45°C/W. VIN The power dissipation in the other power components— catch diodes, boost diodes and inductors,␣ cause additional copper heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal Considerations section. VIN SW GND SW GND (a) (b) VSW VIN IC1 C1 L1 SW D1 GND C2 1940 F08 (c) Figure 8. Subtracting the Current when the Switch is ON (a) From the Current when the Switch is OFF (b) Reveals the Path of the High Frequency Switching Current (c) Keep This Loop Small. The Voltage on the SW and BOOST Nodes will also be Switched; Keep these Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane. 1940i 14 LT1940 U U W U APPLICATIO S I FOR ATIO VOUT1 VIA TO LOCAL GROUND PLANE VIA TO VIN GND VOUT2 1940 F09 Figure 9. A Good PCB Layout Ensures Proper Low EMI Operation Single, Low-Ripple 2.8A Output The LT1940 can generate a single, low-ripple 2.8A output if the outputs of the two switching regulators are tied together and share a single output capacitor. By tying the two FB pins together and the two VC pins together, the two channels will share the load current. There are several advantages to this two-phase buck regulator. Ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. Although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. This may be important when there are tight height restrictions on the circuit. The Typical Applications section shows circuits with maximum heights of 1.4mm, 1.8mm and 2.1mm. There is one special consideration regarding the twophase circuit. When the difference between the input voltage and output voltage is less than 2.5V, then the boost circuits may prevent the two channels from properly sharing current. If, for example, channel 1 gets started first, it can supply the load current, while channel 2 never switches enough current to get its boost capacitor charged. In this case, channel 1 will supply the load until it reaches current limit, the output voltage drops, and channel 2 gets started. The solution is to generate a boost supply generated from either SW pin that will service both BOOST pins. The low profile, single output 5V to 3.3V converter shown in the Typical Applications section shows how to do this. Other Linear Technology Publications Application notes AN19, AN35 and AN44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design note DN100 shows how to generate a dual (+ and –) output supply using a buck regulator. 1940i 15 LT1940 U TYPICAL APPLICATIO S 3.3V and 1.8V Outputs with Sequencing VIN 4.7V TO 14V C3 4.7µF D3 VIN BOOST1 OUT1 1.8V 1.4A L1 2.2µH D4 LT1940 0.1µF L2 3.3µH 0.1µF SW2 SW1 D1 D2 10.0k C1 22µF OUT2 3.3V 1A (1.4A FOR VIN > 5V) BOOST2 16.5k 22.6k 20k 220pF 1nF C1: TAIYO YUDEN JMK316BJ226ML C2: TAIYO YUDEN JMK316BJ106ML C3: TAIYO YUDEN EMK316BJ475ML FB1 FB2 VC1 VC2 RUN/SS1 PG1 RUN/SS2 PG2 15k C2 10µF 10.0k 330pF GND 100k 1940 TA01 D1, D2: MICROSEMI UPS120 D3, D4: CENTRAL CMDSH-3 L1: SUMIDA CR43-2R2 L2: SUMIDA CR43-3R3 POWER GOOD Start-Up Waveforms VIN 2V/DIV VOUT1 2V/DIV VOUT2 2V/DIV POWER GOOD 2V/DIV 50µs/DIV 1940 TA01b 1940i 16 LT1940 U TYPICAL APPLICATIO S 5V/3.3V with Tantalum Output Capacitors VIN 7V TO 25V C3 4.7µF VIN D3 BOOST1 L1 3.3µH OUT1 3.3V 1.2A D4 LT1940 0.1µF L2 4.7µH 0.1µF SW2 SW1 D1 D2 16.5k C1 + 100µF 6.3V 10.0k OUT2 5V 1.2A BOOST2 30.1k FB1 FB2 VC1 VC2 PG1 PG2 + 10.0k RUN/SS1 RUN/SS2 220pF 100k 20k 1nF GND 10.0k C2 47µF 10V 100pF 1nF 3V3 GOOD 100k 5 GOOD 1940 TA03 C1: AVX TPSC107M010R0150 C2: AVX TPSC476M010R0350 C3: TAIYO YUDEN TMK325BJ475ML D1, D2: MICROSEMI UPS140 OR ON SEMI MBRM140 D3, D4: CENTRAL CMDSH-3 L1: SUMIDA CDRH4D28-3R3 L2: SUMIDA CDRH4D28-4R7 1940i 17 LT1940 U TYPICAL APPLICATIO S 3.3V, ±5V D3B VIN 10V TO 25V C3 4.7µF D5 C4 10µF VIN D3A L1 3.3µH LT1940 0.1µF 47k BOOST2 BOOST1 OUT1 3.3V 1.4A OUT3 –5V 300mA 0.1µF 1µF L2 4.7µH OUT2 5V 600mA SW2 SW1 D1 D2 16.5k C1 10µF 30.1k 15k 10.0k FB1 FB2 VC1 VC2 PG1 PG2 20k RUN/SS1 RUN/SS2 330pF 100k GND 1nF C2 10µF 10.0k 220pF 2.2nF 1940 TA05 PGOOD –5V LOAD SHOULD BE LESS THAN 1/2 5V LOAD (SEE DESIGN NOTE 100). D5: ON SEMI MBR0530 L1: SUMIDA CR43-3R3 L2: COILTRONICS CTX5-1A C1, C2, C4: TAIYO YUDEN JMK316BJ106ML C3: TAIYO YUDEN TMK325BJ475ML D1, D2: MICROSEMI UPS140 OR ON SEMI MBRM140 D3: BAT-54A Low Ripple, Low Profile 12V to 3.3V/2.4A Maximum Height = 2.1mm VIN 6V TO 16V VIN C3 4.7µF RUN/SS1 1nF D3A BOOST1 0.1µF RUN/SS2 SW1 PG1 100k D1 PG2 PGOOD L1 4.1µH OUT2 3.3V 2.4A LT1940 680pF VC1 6.8k D3B BOOST2 VC2 0.1µF FB1 L2 4.1µH 330pF SW2 FB2 16.5k GND 10.0k D2 C1 22µF 1940 TA06 D1, D2: MICROSEMI UPS120 D3: BAT-54A L1, L2: SUMIDA CDRH5D18-4R1 C1: TAIYO YUDEN JMK316BJ226ML C3: TAIYO YUDEN EMK325BJ475MN 1940i 18 LT1940 U PACKAGE DESCRIPTIO FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation BA) 4.95 – 5.05* (.196 – .204) 3.0 (.118) 16 1514 13 12 1110 6.60 ±0.10 9 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 4.50 ±0.10 3.0 (.118) 0.45 ±0.05 6.25 – 6.50 (.246 – .256) 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD 1.15 (.0453) MAX 4.30 – 4.48* (.169 – .176) 0° – 8° 0.105 – 0.180 (.0041 – .0071) 0.50 – 0.70 (.020 – .028) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE16 TSSOP 1101 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1940i 19 LT1940 U TYPICAL APPLICATIO Low Ripple, Low Profile 5V to 3.3V/2.4A Maximum Height = 1.4mm 0.47µF VIN 4.8V TO 16V VIN C3 2.2µF RUN/SS1 1nF D3B 0.1µF RUN/SS2 L1 3.3µH OUT2 3.3V 2.4A SW1 PG1 100k D1 PG2 PGOOD D3A BOOST1 LT1940 1500pF VC1 4.7k D4B D4A BOOST2 VC2 0.1µF FB1 L2 3.3µH 330pF SW2 FB2 16.5k GND D2 10k C1 20µF 1940 TA07 D1, D2: MICROSEMI UPS120 D3, D4: BAT-54S L1, L2: COILCRAFT LPO1704-332M C1: 2X TAIYO YUDEN JMK212BJ106ML C3: 2X TAIYO YUDEN EMK212BJ105MN RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1616 600mA, 1.4MHz Step-Down DC/DC Converter 6-Lead ThinSOTTM Package LTC1628 High Efficiency, 2-Phase Step-Down Switching Regulator Dual Synchronous Controller LT1676/LT1776 Wide Input Range Step-Down Switching Regulators 60V Input, 0.7A Internal Switch LT1763 500mA, Low Noise, LDO Regulator 20µVRMS, IQ = 30µA, 8-Lead SO Package LT1765 3A, 1.25MHz Step-Down DC/DC Converter 8-Lead SO Package LT1766 Wide Input Range Step-Down Switching Regulator 60V Input, 1.5A Internal Switch LT1767 1.5A, 1.25MHz Step-Down DC/DC Converter 8-Lead MSOP Package LTC1772 Constant Frequency Step-Down Controller in ThinSOT Higher Current, 100% Duty Cycle LT1930 1.2MHz Boost DC/DC Converter in ThinSOT 1A, 36V Internal Switch LT1962 300mA, Low Noise, LDO Regulator 20µVRMS, IQ = 30µA, 8-Lead MSOP Package LT1963 1.5A, Low Noise, LDO Regulator 40µVRMS, Fast Transient Response LTC3404 1.4MHz Synchronous Step-Down Regulator High Efficiency, 10µA IQ, 8-Lead MSOP Package LTC3411 2MHz, 1.25A, Synchronous Step-Down DC/DC Converter VIN 2.5V to 5V, VOUT to 0.8V, MS10 Package LT3430 Wide Input Range Step-Down Switching Regulator 60V Input, 3A Internal Switch, TSSOP16E Package ThinSOT is a trademark of Linear Technology Corporation. 1940i 20 Linear Technology Corporation LT/TP 0802 1.5K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001