LTC1148 LTC1148-3.3/LTC1148-5 High Efficiency Synchronous Step-Down Switching Regulators U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1148 series is a family of synchronous stepdown switching regulator controllers featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250kHz using a constant off-time current-mode architecture providing constant ripple current in the inductor. Ultrahigh Efficiency: Over 95% Possible Current-Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over Three Decades of Output Current Low 160µA Standby Current at Light Loads Logic Controlled Micropower Shutdown: IQ < 20µA Wide VIN Range: 3.5V* to 20V Short-Circuit Protection Very Low Dropout Operation: 100% Duty Cycle Synchronous FET Switching for High Efficiency Adaptive Nonoverlap Gate Drives Output Can Be Externally Held High in Shutdown Available in 14-Pin Narrow SO Package The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V* to 18V (20V maximum). Constant off-time architecture provides low dropout regulation limited by only the RDS(ON) of the external MOSFET and resistance of the inductor and current sense resistor. The LTC1148 series combines synchronous switching for maximum efficiency at high currents with an automatic low current operating mode, called Burst Mode operation, which reduces switching losses. Standby power is reduced to only 2mW at VIN = 10V (at IOUT = 0). Load currents in Burst Mode operation are typically 0mA to 300mA. UO APPLICATI ■ ■ ■ ■ ■ ■ S Notebook and Palmtop Computers Portable Instruments Battery-Operated Digital Devices Cellular Telephones DC Power Distribution Systems GPS Systems For operation up to 48V input, see the LTC1149 and LTC1159 data sheets and Application Note 54. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. * LTC1148L and LTC1148L-3.3 only. UO TYPICAL APPLICATI LTC1148-5 Efficiency VIN (5.2V TO 18V) 100 + 1µF 0V = NORMAL >1.5V = SHUTDOWN RC 1k CC 3300pF CT 470pF VIN P-DRIVE LTC1148HV-5 SHUTDOWN SENSE + ITH SENSE – CT N-DRIVE PGND SGND P-CHANNEL Si4431DY L* 62µH VIN = 6V CIN 100µF 95 RSENSE** 0.05Ω VOUT 5V/2A 1000pF N-CHANNEL Si4412DY D1 MBRS140T3 + COUT 390µF EFFICIENCY (%) + VIN = 10V 90 85 LT1148 • TA01 *COILTRONICS CTX62-2-MP **KRL SL-1-C1-0R050J 80 0.02 0.2 LOAD CURRENT (A) 2 LTC1148 • TA01 Figure 1. High Efficiency Step-Down Converter 1 LTC1148 LTC1148-3.3/LTC1148-5 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (Pin 3) LTC1148 and LTC1148L Series ............ 16V to – 0.3V LTC1148HV Series ............................... 20V to – 0.3V Continuous Output Current (Pins 1, 14) .............. 50mA Sense Voltages (Pins 7, 8) LTC1148HV (Adjustable Only) VIN ≥ 12.7V ...................................... 13V to – 0.3V VIN < 12.7V ......................... (VIN + 0.3V) to – 0.3V Operating Ambient Temperature Range ...... 0°C to 70°C Extended Commercial Temperature Range ............................... – 40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW P-DRIVE 1 14 N-DRIVE NC 2 13 NC VIN 3 12 PGND CT 4 11 SGND INTVCC 5 10 SHUTDOWN ITH 6 9 VFB* SENSE – 7 8 SENSE + N PACKAGE 14-LEAD PDIP S PACKAGE 14-LEAD PLASTIC SO *FIXED OUTPUT VERSIONS = NC TJMAX = 125°C, θJA = 70°C/ W (N) TJMAX = 125°C, θJA = 110°C/ W (S) LTC1148CN LTC1148HVCN LTC1148CN-3.3 LTC1148HVCN-3.3 LTC1148CN-5 LTC1148HVCN-5 LTC1148CS LTC1148HVCS LTC1148LCS LTC1148CS-3.3 LTC1148HVCS-3.3 LTC1148LCS-3.3 LTC1148CS-5 LTC1148HVCS-5 Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS TA = 25°C, VIN = 10V, VSHUTDOWN = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS V9 Feedback Voltage (LTC1148, LTC1148L, LTC1148HV) VIN = 9V I9 Feedback Current (LTC1148, LTC1148L, LTC1148HV) VOUT Regulated Output Voltage VIN = 9V LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 ILOAD = 700mA LTC1148-5, LTC1148HV-5 ILOAD = 700mA ∆VOUT Output Voltage Line Regulation 2 Input DC Supply Current (Note 3) LTC1148 Series Normal Mode Sleep Mode Sleep Mode (LTC1148-5) Shutdown LTC1148HV Series Normal Mode Sleep Mode Sleep Mode (LTC1148HV-5) Shutdown LTC1148L Series Normal Mode Sleep Mode Shutdown MIN TYP MAX UNITS 1.21 1.25 1.29 V 0.2 1 µA 3.23 4.90 3.33 5.05 3.43 5.20 V V – 40 0 40 mV 40 60 65 100 mV mV ● ● ● VIN = 7V to 12V, ILOAD = 50mA Output Voltage Load Regulation LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 5mA < ILOAD < 2A LTC1148-5, LTC1148HV-5 5mA < ILOAD < 2A Output Ripple (Burst Mode) ILOAD = 0A IQ ● ● ● 50 mVP-P (Note 7) 4V < VIN < 12V 4V < VIN < 12V 6V < VIN < 12V VSHUTDOWN = 2.1V, 4V < VIN < 12V 1.6 160 160 10 2.1 230 230 20 mA µA µA µA 4V < VIN < 18V 4V < VIN < 18V 6V < VIN < 18V VSHUTDOWN = 2.1V, 4V < VIN < 18V 1.6 160 160 10 2.3 250 250 22 mA µA µA µA 3.5V < VIN < 12V 3.5V < VIN < 12V VSHUTDOWN = 2.1V, 3.5V < VIN < 12V 1.6 160 10 2.1 230 20 mA µA µA LTC1148 LTC1148-3.3/LTC1148-5 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER V8 – V7 Current Sense Threshold Voltage LTC1148, LTC1148HV, LTC1148L TA = 25°C, VIN = 10V, VSHUTDOWN = 0V, unless otherwise noted. CONDITIONS MIN TYP MAX UNITS VSENSE – = 5V, V9 = VOUT/4 + 25mV (Forced) VSENSE – = 5V, V9 = VOUT/4 – 25mV (Forced) ● 130 25 150 170 mV mV LTC1148-3.3, LTC1148HV-3.3 LTC1148L-3.3 VSENSE – = VOUT + 100mV (Forced) VSENSE – = VOUT – 100mV (Forced) ● 130 25 150 170 mV mV LTC1148-5, LTC1148HV-5 VSENSE – = VOUT + 100mV (Forced) VSENSE – = VOUT – 100mV (Forced) ● 130 25 150 170 mV mV 0.5 0.8 2 V10 Shutdown Pin Threshold V I10 Shutdown Pin Input Current 0V < VSHUTDOWN < 8V, VIN = 16V 1.2 5 µA I4 CT Pin Discharge Current VOUT in Regulation, VSENSE – = VOUT VOUT = 0V 50 70 2 90 10 µA µA tOFF Off Time (Note 5) CT = 390pF, ILOAD = 700mA 4 5 6 µs tR, tF Driver Output Transition Times CL = 3000pF (Pins 1, 14), VIN = 6V 100 200 ns – 40°C ≤ TA ≤ 85°C (Note 5), VIN = 10V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V9 Feedback Voltage (LTC1148, LTC1148HV LTC1148L) VIN = 9V 1.20 1.25 1.30 V ∆VOUT Regulated Output Voltage LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 LTC1148-5, LTC1148HV-5 VIN = 9V ILOAD = 700mA ILOAD = 700mA 3.17 4.85 3.33 5.05 3.43 5.20 V V Input DC Supply Current (Note 3) LTC1148 Series Normal Mode Sleep Mode Sleep Mode Shutdown LTC1148HV Series Normal Mode Sleep Mode Sleep Mode Shutdown LTC1148L Series Normal Mode Sleep Mode Shutdown (Note 7) 4V < VIN < 12V 4V < VIN < 12V 6V < VIN < 12V VSHUTDOWN = 2.1V, 4V < VIN < 12V 1.6 160 160 10 2.4 260 260 22 mA µA µA µA 4V < VIN < 18V 4V < VIN < 18V 6V < VIN < 18V VSHUTDOWN = 2.1V, 4V < VIN < 18V 1.6 160 160 10 2.6 280 280 24 mA µA µA µA 3.5V < VIN < 12V 3.5V < VIN < 12V VSHUTDOWN = 2.1V, 3.5V < VIN < 12V 1.6 160 10 2.4 260 22 mA µA µA 125 25 150 175 mV mV LTC1148-3.3, LTC1148HV-3.3, LTC1148L-3.3 VSENSE – = VOUT + 100mV (Forced) VSENSE – = VOUT – 100mV (Forced) 125 25 150 175 mV mV VSENSE – = VOUT + 100mV (Forced) VSENSE – = VOUT – 100mV (Forced) 125 25 150 175 mV mV 0.55 0.8 2 V 3.8 5 6 µs IQ V8 – V7 Current Sense Threshold Voltage LTC1148, LTC1148HV, LTC1148L (Note 4) LTC1148-5, LTC1148HV-5 V10 Shutdown Pin Threshold tOFF Off Time (Note 5) VSENSE – = 5V, V9 = VOUT/4 – 25mV (Forced) VSENSE – = 5V, V9 = VOUT/4 + 25mV (Forced) CT = 390pF, ILOAD = 700mA 3 LTC1148 LTC1148-3.3/LTC1148-5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1148CN, LTC1148CN-3.3, LTC1148CN-5: TJ = TA + (PD × 70°C/W) LTC1148CS, LTC1148CS-3.3, LTC1148CS-5: TJ = TA + (PD × 110°C/W) Note 3: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 4: The LTC1148 and LTC1148HV versions are tested with external feedback resistors resulting in a nominal output voltage of 5V. The LTC1148L version is tested with external feedback resistors resulting in a nominal output voltage of 2.5V. Note 5: In applications where RSENSE is placed at ground potential, the off time increases approximately 40%. Note 6: The LTC1148, LTC1148HV and LTC1148L series are not tested and not quality assurance sampled at –40°C and 85°C. These specifications are guaranteed by design and/or correlation. Note 7: The LTC1148L and LTC1148L-3.3 allow operation to VIN = 3.5V. U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Input Voltage 20 FIGURE 1 CIRCUIT ILOAD = 1A 30 ILOAD = 1A 20 ∆VOUT (mV) 94 92 90 88 ILOAD = 100mA 86 –20 10 0 –10 –40 VIN = 12V –60 –80 –30 82 80 –40 4 0 12 8 INPUT VOLTAGE (V) 16 20 –100 0 8 4 20 1.2 0.9 0.6 14 12 10 8 6 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE LTC1148 • TPC04 0°C 1.2 70°C 25°C 1.0 0.8 0.6 0.4 0.2 0 0 2.5 VOUT = 5V 1.4 2 0 2 1.6 4 SLEEP MODE 1 1.5 LOAD CURRENT (A) Operating Frequency vs (VIN – VOUT) NORMALIZED FREQUENCY SUPPLY CURRENT (µA) ACTIVE MODE 0.3 0.5 LTC1148 • TPC03 VSHUTDOWN = 2V 18 16 1.5 0 20 Supply Current in Shutdown NOT INCLUDING GATE CHARGE CURRENT 1.8 16 LTC1148 • TPC02 DC Supply Current 2.1 12 INPUT VOLTAGE (V) LTC1148 • TPC01 SUPPLY CURRENT (mA) VIN = 6V –20 84 4 FIGURE 1 CIRCUIT RSENSE = 0.05Ω 0 ∆VOUT (mV) 96 EFFICIENCY (%) 40 FIGURE 1 CIRCUIT 98 Load Regulation Line Regulation 100 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) LTC1148 • TPC05 0 0 2 4 8 10 6 (VIN – VOUT) VOLTAGE (V) 12 LTC1148 • TPC06 LTC1148 LTC1148-3.3/LTC1148-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Off Time vs VOUT 80 24 70 Current Sense Threshold Voltage 175 VSENSE – = VOUT 16 12 8 QN + QP = 50nC 4 SENSE VOLTAGE (mV) QN + QP = 100nC 50 40 30 20 LTC1148-3.3 20 260 80 200 140 OPERATING FREQUENCY (kHz) 0 0 2 1 100 75 50 MINIMUM THRESHOLD 0 3 4 5 OUTPUT VOLTAGE (V) LTC1148 • TPC07 125 25 LTC1148-5 10 0 MAXIMUM THRESHOLD 150 60 20 OFF TIME (µs) GATE CHARGE CURRENT (mA) Gate Charge Supply Current 28 LTC1148 • TPC08 0 20 60 40 TEMPERATURE (°C) 80 100 LTC1148 • TPC09 U U U PI FU CTIO S P-DRIVE (Pin 1): High Current Drive for Top P-Channel MOSFET. Voltage swing at this pin is from VIN to ground. NC (Pin 2): No Connection. Can connect to power ground. VIN (Pin 3): Main Supply Pin. Must be closely decoupled to power ground Pin 12. CT (Pin 4): External capacitor CT from Pin 4 to ground sets the operating frequency. The actual frequency is also dependent upon the input voltage. INTVCC (Pin 5): Internal Supply Voltage, Nominally 3.3V. Can be decoupled to signal ground. Do not externally load this pin. ITH (Pin 6): Gain Amplifier Decoupling Point. The current comparator threshold increases with the Pin 6 voltage. SENSE – (Pin 7): Connects to internal resistive divider which sets the output voltage in LTC1148-3.3 and LTC1148-5 versions. Pin 7 is also the (–) input for the current comparator. VFB (Pin 9): For the LTC1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider used to set the output voltage. On LTC1148-3.3 and LTC1148-5 versions this pin is not used. SHUTDOWN (Pin 10): When grounded, the LTC1148 series operates normally. Pulling Pin 10 high holds both MOSFETs off and puts the LTC1148 series in micropower shutdown mode. Requires CMOS logic signal with tR, tF < 1µs, should not be left floating. SGND (Pin 11): Small-Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT. PGND (Pin 12): Driver Power Ground. Connects to source of N-channel MOSFET and the (–) terminal of CIN. NC (Pin 13): No Connection. Can connect to power ground. N-DRIVE (Pin 14): High Current Drive for Bottom N-Channel MOSFET. Voltage swing at Pin 14 is from ground to VIN. SENSE + (Pin 8): The (+) Input to the Current Comparator. A built-in offset between Pins 7 and 8 in conjunction with RSENSE sets the current trip threshold. 5 LTC1148 LTC1148-3.3/LTC1148-5 U U W FU CTIO AL DIAGRA Pin 9 connection shown for LTC1148-3.3 and LTC1148-5; changes create LTC1148. 3 VIN 1 P-DRIVE SGND SENSE+ SENSE – 8 7 11 ADJUSTABLE VERSION VFB 14 N-DRIVE 9 – 12 PGND V + SLEEP – R + S + – 5pF VOS – VTH1 13k T + – VTH2 + S – 25mV TO 150mV C Q ITH 6 G + VIN SENSE – VFB OFF-TIME CONTROL 4 CT SHUTDOWN 10 100k 1.25V REFERENCE 5 INTVCC LTC1148 • FD TEST CIRCUIT + + IRF9Z34 VIN 330µF 1N5818 IRFZ34 1 2 1µF + 3 4 5 6 390pF 10nF 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN PGND CT SGND INTVCC SHUTDOWN ITH NC (VFB) SENSE – SENSE + 14 13 50µH 12 11 10 + V10 25k + 8 + 1k V7 1000pF 100pF 9 + V7 TO V8 RSENSE 0.05Ω 440µF 75k VOUT 6 LTC1148 LTC1148-3.3/LTC1148-5 OPERATIO U The LTC1148 series uses a current mode, constant offtime architecture to synchronously switch an external pair of complementary power MOSFETs. Operating frequency is set by an external capacitor at the timing capacitor Pin 4. The output voltage is sensed by an internal voltage divider connected to SENSE – Pin 7 (LTC1148-3.3 and LTC1148-5) or external divider returned to VFB Pin 9 (LTC1148). A voltage comparator V, and a gain block G, compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1148 series automatically switches between two modes of operation, burst and continuous. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode. During the switch “ON” cycle in continuous mode, current comparator C monitors the voltage between Pins 7 and 8 connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the P-drive output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor connected to Pin 4 is now allowed to discharge at a rate determined by the off-time controller. The discharge current is made proportional to the output voltage (measured by Pin 7) to model the inductor current, which decays at a rate which is also proportional to the output voltage. While the timing capacitor is discharging, the N-drive output goes to VIN, turning on the N-channel MOSFET. When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the N-drive output to go low (turning off the Nchannel MOSFET) and the P-drive output to also go low (turning the P-channel MOSFET back on). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage (Pin 6) to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low and the Nchannel MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode, a majority of the circuitry is turned off, dropping the quiescent current from 1.6mA to 160µA. The load current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and the process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset (VOS) is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the N-drive output can go high, the P-drive output must also be high. Likewise, the P-drive output is prevented from going low while the N-drive output is high. Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as VIN drops below VOUT + 1.5V. In dropout the P-channel MOSFET is turned on continuously (100% duty cycle), providing extremely low dropout operation. 7 LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO The basic LTC1148 series application circuit (fixed output versions) is shown in Figure 1. External component selection is driven by the load requirement, and begins with the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 20V. If the application requires higher input voltage, then the LTC1149 or LTC1159 should be used. 0.20 RSENSE (Ω) 0.15 0.10 0.05 0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) LTC1148 • F02 RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1148 series current comparator has a threshold range which extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE (See CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1148 series and external component values yields: RSENSE = 100mV IMAX A graph for selecting RSENSE versus maximum output current is given in Figure 2. The load current below which Burst Mode operation commences (IBURST) and the peak short-circuit current (ISC(PK)) both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following: IBURST ≈ 15mV RSENSE ISC(PK) = 150mV RSENSE 8 5 Figure 2. Selecting RSENSE The LTC1148 series automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current ISC(AVG) to be reduced to approximately IMAX. L and CT Selection for Operating Frequency The LTC1148 series uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the P-channel MOSFET switch turns on, the voltage on CT is reset to approximately 3.3V. During the off time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the current in inductor L, which likewise decays at a rate proportional to VOUT. Thus the inductor value must track the timing capacitor value. The value of CT is calculated from the desired continuous mode operating frequency, f: CT = 1 2.6(104)f Assumes VIN = 2VOUT, Figure 1 circuit. A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency of the circuit in Figure 1 is given by: LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO 1000 VSENSE – = VOUT = 5V CAPACITANCE (pF) 800 600 400 VIN = 12V VIN = 7V 200 VIN = 10V 0 0 200 100 FREQUENCY (kHz) 300 Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. The highest efficiency will be obtained using ferrite, Kool Mµ® on molypermalloy (MPP) cores. Lower cost powdered iron cores provide suitable performance but cut efficiency by 3% to 7%. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. LTC1148 • F03 Figure 3. Timing Capacitor Value f= 1 tOFF ) 1– VOUT VIN where: tOFF = 1.3(104)CT ) ) ) VREG VOUT VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is the measured output voltage. Thus VREG/VOUT = 1 in regulation. Note that as VIN decreases, the frequency decreases. When the input to output voltage differential drops below 1.5V, the LTC1148 series reduces tOFF by increasing the discharge current in CT. This prevents audible operation prior to dropout. Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/RSENSE of peak-to-peak inductor ripple current. This results in a minimum required inductor value of: LMIN = 5.1(105)RSENSE(CT)VREG As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A consequence of this is that the LTC1148 series may not enter Burst Mode operation and efficiency will be severely degraded at low currents. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered. Do not allow the core to saturate! Kool Mµ (from Magnetics, Inc.) is a very good, low loss core material for toroids, with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high (>200kHz) switching frequencies, but quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available from Coiltronics and Beckman Industrial Corp. which do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1148 series: a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The main selection criteria for the power MOSFETs are the threshold voltage VGS(TH) and on resistance RDS(ON). The minimum input voltage determines whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V) may be used. If VIN is expected to drop below 8V, logicKool Mµ is a registered trademark of Magnetics, Inc. 9 LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO level threshold MOSFETs (VGS(TH) < 2.5V) are strongly recommended. The LTC1148/LTC1148HV series supply voltage must always be less than the absolute maximum VGS ratings for the MOSFETs. The maximum output current IMAX determines the RDS(ON) requirement for the two MOSFETs. When the LTC1148 series is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. The duty cycles for the two MOSFETs are given by: V P-Ch Duty Cycle = OUT VIN N-Ch Duty Cycle = (VIN – VOUT) VIN From the duty cycles the required RDS(ON) for each MOSFET can be derived: P-Ch RDS(ON) = VIN(PP) VOUT(IMAX2)(1 + δP) N-Ch RDS(ON) = VIN(PN) (VIN – VOUT)(IMAX2)(1 + δN) where PP and PN are the allowable power dissipations and dP and dN are the temperature dependencies of RDS(ON). PP and PN will be determined by efficiency and/or thermal requirements (see Efficiency Considerations). (1 + d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but d = 0.007/°C can be used as an approximation for low voltage MOSFETs. The Schottky diode D1 shown in Figure 1 only conducts during the dead-time between the conduction of the two power MOSFETs. D1’s sole purpose in life is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D1 is omitted). Therefore, D1 should be selected for a forward voltage of less than 0.7V when conducting IMAX. 10 CIN and COUT Selection In continuous mode, the source of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ IMAX [VOUT(VIN – VOUT)]1/2 VIN This formula has a maximum at V IN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. An additional 0.1µF to 1µF ceramic capacitor is also required on VIN Pin 3 for high frequency decoupling. The selection of COUT is driven by the required effective series resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1148 series: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE, the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon and United Chemicon should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR/size ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For example, if 200µF/10V is called for in an application requiring 3mm height, two AVX 100µF/10V (P/N TPSD 107K010) could be used. Consult the manufacturer for other specific recommendations. At low supply voltages, a minimum capacitance at COUT is needed to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is made too small, the output ripple at low frequencies will be large enough to trip the voltage comparator. This causes Burst Mode operation to be activated when the LTC1148 series would normally be in continuous operation. The effect is most pronounced with low values of RSENSE and can be improved by operating at higher frequencies with lower values of L. The output remains in regulation at all times. 1000 L = 50µH RSENSE = 0.02Ω COUT (µF) 800 L = 25µH RSENSE = 0.02Ω 600 A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) 400 200 L = 50µH RSENSE = 0.05Ω 0 several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT until the regulator loop adapts to the current change and returns VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The Pin 6 external components shown in the Figure 1 circuit will prove adequate compensation for most applications. 0 1 3 4 2 (VIN – VOUT) VOLTAGE (V) 5 where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power). Checking Transient Response Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC1148 series circuits: 1) LTC1148 DC bias current, 2) MOSFET gate charge current, and 3) I2R losses. The regulator loop response can be checked by looking at the load transient response. Switching regulators take 1. The DC supply current is the current which flows into VIN Pin 3 less the gate charge current. For VIN = 10V the LTC1148 • F04 Figure 4. Minimum Value of COUT 11 LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO 2. MOSFET gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN which is typically much larger than the DC supply current. In continuous mode, IGATECHG = f (QN + QP). The typical gate charge for a 0.1Ω N-channel power MOSFET is 25nC, and for a P-channel about twice that value. This results in IGATECHG = 7.5mA in 100kHz continuous operation, for a 2% to 3% typical mid-current loss with VIN = 10V. Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using larger MOSFETs than necessary to control I2R losses, since overkill can cost efficiency as well as money! 3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor, and current shunt. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the P-channel and N-channel MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω, and RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll-off at high output currents. Figure 5 shows how the efficiency losses in a typical LTC1148 series regulator end up being apportioned. 12 100 I2R GATE CHARGE EFFICIENCY/LOSS (%) LTC1148 DC supply current is 160µA for no load, and increases proportionally with load up to a constant 1.6mA after the LTC1148 series has entered continuous mode. Because the DC bias current is drawn from VIN, the resulting loss increases with input voltage. For VIN = 10V the DC bias losses are generally less than 1% for load currents over 30mA. However, at very low load currents the DC bias current accounts for nearly all of the loss. 95 LTC1148 IQ 90 85 80 0.01 0.03 0.3 1 0.1 OUTPUT CURRENT (A) 3 LTC1148 • F05 Figure 5. Efficiency Loss The gate charge loss is responsible for the majority of the efficiency lost in the mid-current region. If Burst Mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output current is reduced. As expected, the I2R losses dominate at high load currents. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses, Schottky conduction losses during dead time, and inductor core losses, generally account for less than 2% total additional loss. Design Example As a design example, assume VIN = 12V (nominal), VOUT = 5V, IMAX = 2A, and f = 200kHz; RSENSE, CT and L can immediately be calculated: RSENSE = 100mV/2 = 0.05Ω tOFF = (1/200kHz)[1 – (5/12)] = 2.92µs CT = 2.92µs/[(1.3)(104)] = 220pF LMIN = 5.1(105)0.05Ω(220pF)5V = 28µH Assume that the MOSFET dissipations are to be limited to PN = PP = 250mW. If TA = 50°C and the thermal resistance of each MOSFET is 50°C/ W, then the junction temperatures will be 63°C LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO and δP = δN = 0.007(63 – 25) = 0.27. The required RDS(ON) for each MOSFET can now be calculated: P-Ch RDS(ON) = 12(0.25) = 0.12Ω 5(2)2 (1.27) N-Ch RDS(ON) = 12(0.25) = 0.085Ω 7(2)2 (1.27) The P-channel requirement can be met by a Si9430DY, while the N-channel requirement is exceeded by a Si9410DY. Note that the most stringent requirement for the N-channel MOSFET is with VOUT = 0 (i.e., short circuit). During a continuous short circuit, the worst-case N-channel dissipation rises to: PN = ISC(AVG)2(RDS(ON))(1 + δN) With the 0.05Ω sense resistor ISC(AVG) = 2A will result, increasing the 0.085Ω N-channel dissipation to 450mW at a die temperature of 73°C. CIN will require an RMS current rating of at least 1A at temperature, and COUT will require an ESR of 0.05Ω for optimum efficiency. Now allow VIN to drop to its minimum value. At lower input voltages the operating frequency will decrease and the P-channel will be conducting most of the time, causing its power dissipation to increase. At VIN(MIN) = 7V: fMIN = (1/2.92µs)[1 – (5V/7V)] = 98kHz PP = 5V(0.12Ω)(2A)2(1.27) = 435mW 7V This last step is necessary to assure that the power dissipation and junction temperature of the P-channel are not exceeded. To prevent stray pickup a 100pF capacitor is suggested across R1 located close to the LTC1148. For Figure 1 applications with VOUT below 2V, or when RSENSE is moved to ground, the current sense comparator inputs operate near ground. When the current comparator is operated at less than 2V common mode, the off time increases approximately 40%, requiring the use of a smaller timing capacitor CT. Auxiliary Windings – Suppressing Burst Mode Operation The LTC1148 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. Burst Mode operation can be suppressed at low output currents with a simple external network which cancels the 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the SENSE – pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 6. Two 100Ω resistors are inserted in series with the leads from the sense resistor. R2 100Ω SENSE + (PIN 8) 1000pF SENSE – (PIN 7) RSENSE VOUT + R3 LTC1148 Adjustable Applications R1 100Ω COUT LTC1148 • F06 When an output voltage other than 3.3V or 5V is required, the LTC1148 adjustable version is used with an external resistive divider from VOUT to VFB Pin 9 (see Figure 9). The regulated voltage is determined by: ) VOUT = 1.25 1 + R2 R1 Figure 6. Suppression of Burst Mode Operation ) 13 LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO With the addition of R3, a current is generated through R1 causing an offset of: VOFFSET = VOUT ) ) R1 R1 + R3 If VOFFSET > 25mV, the minimum threshold will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be lower: RSENSE ≈ 75mV IMAX To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Pins 7 and 8. Output Crowbar An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. Pulling the timing capacitor Pin 4 above 1.5V when the output voltage is greater than the desired regulated value will turn “on” the N-channel MOSFET. A fault condition which causes the output voltage to go above a maximum allowable value can be detected by external circuitry. Turning on the N-channel MOSFET when this fault is detected will cause large currents to flow and blow the system fuse. The N-channel MOSFET needs to be sized so it will safely handle this overcurrent condition. The typical delay from pulling the CT pin high and the N drive Pin 14 going high is 250ns. Note: Under shutdown conditions, the N-channel is held OFF and pulling the CT pin high will not cause the N-channel MOSFET to crowbar the output. A simple N-channel FET can be used as an interface between the overvoltage detect circuitry and the LTC1148 as shown in Figure 7. 14 5 FROM CROWBAR DETECT CIRCUIT (ACTIVE WHEN VGATE = VIN OFF WHEN VGATE = GROUND) VN2222LL 4 INTVCC LTC1148 CT LTC1148 • F07 Figure 7. Output Crowbar Interface Troubleshooting Hints Since efficiency is critical to LTC1148 series applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the timing capacitor Pin 4. In continuous mode (ILOAD > IBURST) the voltage on the CT pin should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 8a. When load currents are low (ILOAD < IBURST) Burst Mode operation should occur with the CT pin waveform periodically falling to ground as shown in Figure 8b. 3.3V 0V (a) CONTINUOUS MODE OPERATION 3.3V 0V (b) Burst Mode OPERATION LTC1148 • F08 Figure 8. CT Waveforms If Pin 4 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist. LTC1148 LTC1148-3.3/LTC1148-5 U U W U APPLICATIO S I FOR ATIO Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1148 series. These items are also illustrated graphically in the layout diagram of Figure 9. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1148 signal ground Pin 11 must return to the (–) plate of COUT. The power ground returns to the source of the N-channel MOSFET, anode of the Schottky diode, and (–) plate of CIN, which should have as short lead lengths as possible. 2. Does the LTC1148 SENSE – Pin 7 connect to a point close to RSENSE and the (+) plate of COUT? In adjustable applications, the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. 3. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The 1000pF capacitor between Pins 7 and 8 should be as close as possible to the LTC1148. 4. Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET. 5. Is the 1µF VIN decoupling capacitor connected closely between Pin 3 and power ground Pin 12? This capacitor carries the MOSFET driver peak currents. 6. Is the Shutdown Pin 10 actively pulled to ground during normal operation? The Shutdown pin is high impedance and must not be allowed to float. + BOLD LINES INDICATE HIGH CURRENT PATHS CIN + P-CHANNEL VIN D1 N-CHANNEL 1 2 + 1µF 3 4 5 6 CT 10nF 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN CT INTVCC PGND SGND SHDN ITH NC (VFB) SENSE – SENSE + – 14 13 12 L 11 10 – SHUTDOWN R1 9 + VOUT COUT 8 R2 1k RSENSE 1000pF + OUTPUT DIVIDER REQUIRED WITH ADJUSTABLE VERSION ONLY LTC1148 • F09 Figure 9. LTC1148 Layout Diagram (See Board Layout Checklist) 15 LTC1148 LTC1148-3.3/LTC1148-5 U TYPICAL APPLICATIO S VIN 4V TO 18V VIN 5.2V TO 18V + 1/2 Si4532 D1 MBRS140T3 + CIN 100µF 25V 1/2 Si4532 1µF + 2 3 4 CT 390pF 5 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148HV-5 VIN PGND CT SGND INTVCC SHUTDOWN ITH SENSE – NC SENSE + RC 1k 1 14 13 1µF + *L 100µH 2 3 12 4 11 10 CT 300pF SHUTDOWN 9 + 8 COUT 220µF 10V AVX 5 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148HV-3.3 VIN PGND CT SGND INTVCC SHUTDOWN ITH NC SENSE – SENSE + 14 13 *L 50µH 12 11 10 SHUTDOWN 9 + 8 RC 1k RSENSE** 0.1Ω 1000pF CIN 100µF 25V 1/2 Si4532 1/2 Si4532 1 D1 MBRS140T3 1000pF COUT 220µF 10V OS-CON RSENSE** 0.1Ω VOUT 3.3V/1A VOUT 5V/1A *COILTRONICS CTX100-4 Kool Mµ CORE **KRL SP-1/2-A1-0R100 *COILTRONICS CTX50-4 Kool Mµ CORE **IRC LR2010-01-R100-G LTC1148 • F10 Figure 10. 5V/1A High Efficiency Regulator with Extended Input Voltage Range Figure 11. High Efficiency 5V to 3.3V/1A Converter with Extended Input Voltage Range VIN 8V TO 14V + IRF7204 CIN 330µF 20V D1 MBRS140T3 IRF7201 1 + 1µF 2 3 4 5 CT 390pF 10nF 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN PGND CT SGND INTVCC SHUTDOWN ITH SENSE – VFB SENSE + RC 220Ω 14 13 *L 50µH 12 11 10 SHUTDOWN 100pF 9 R1 10k 1% R2 30k 1% 8 0.01µF *COILTRONICS CTX50-2-MP **KRL SL-1-C1-0R033J + COUT 220µF 10V ×2 OS-CON RSENSE** 0.033Ω ( ) VOUT = 1 + R2 1.25V R1 VALUES SHOWN FOR VOUT = 5V Figure 12. High Efficiency Adjustable 3A Regulator 16 LTC1148 • F11 VOUT 5V/3A LTC1148 • F12 LTC1148 LTC1148-3.3/LTC1148-5 U TYPICAL APPLICATIO S VIN 3.5V TO 14V + MMSF3P02HD D1 MBRS140T3 CIN 100µF 20V MMSF5N02HD 1 1µF + P-DRIVE 2 NC LTC1148L-3.3 VIN PGND 4 CT 5 11 SGND ITH 7 10 SHUTDOWN COUT 220µF 10V ×2 AVX 9 NC SENSE – *L 25µH 12 INTVCC SHUTDOWN 6 CC 3300pF 13 NC 3 CT 270pF 14 N-DRIVE + 8 SENSE + RC 1k 1000pF RSENSE** 0.05Ω VOUT 3.3V/2A *COILTRONICS CTX25-5 Kool Mµ CORE **IRC LR2512-01-R050-G LTC1148 • F13 Figure 13. 5V Input Voltage, 3.3V/2A Low Dropout, High Efficiency Regulator VIN 4V TO 9V VIN: ACTIVE 0V: SHUTDOWN TP0610L Si4431DY + D1 MBRS140T3 CIN 220µF 20V Si4412DY 1 1µF + 2 3 4 5 CT 560pF 10nF 6 CC 6800pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN PGND CT SGND INTVCC SHUTDOWN ITH SENSE – VFB SENSE + 14 13 *L 50µH 12 11 10 1M 200pF 9 8 RC 1k 1000pF RSENSE** 0.05Ω *COILTRONICS CTX50-2-MP **KRL SL-1-C1-0R050J VOUT –5V/1.4A R1 25k 1% R2 75k 1% + COUT 220µF 10V ×2 OS-CON LTC1148 • F14 Figure 14. 4V to 9V Input Voltage to – 5V/1A Regulator 17 LTC1148 LTC1148-3.3/LTC1148-5 U TYPICAL APPLICATIO S VIN 5V CIN 100µF 20V ×2 + Si9803DY D1 MBRS140T3 Si9804DY 1 0.1µF 2 3 4 CT 270pF NPO 5 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148-3.3 VIN PGND CT SGND INTVCC SHUTDOWN ITH NC SENSE – SENSE + 14 13 *L 10µH 12 11 10 SHUTDOWN COUT 220µF 10V AVX ×2 9 + 8 RC 470Ω 1000pF RSENSE** 0.02Ω VOUT 3.3V/4.5A *COILTRONICS CTX10-5P **KRL SP-1-C1-0R020 LTC1148 • F15 Figure 15. High Efficiency 5V to 3.3V/4.5A Converter VIN 4V TO 14V + Si4435DY 2 + 3 4 CT 390pF 5 1N4148 VOUT 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN CT PGND SGND INTVCC SHUTDOWN ITH SENSE – VFB SENSE + RC 1k 14 13 L2 50µH + 1 1µF CIN 100µF 20V 12 220µF* 10V OS-CON L1 50µH 11 10 SHUTDOWN Si4412DY D1 MBRS140T3 9 VOUT 5V/1A R2 75k 1% + 8 0.1µF RSENSE** 0.082Ω R1 25k 1% 100pF *LOW ESR REQUIRED **KRL NP-1A-C1-0R082J LTC1148 • F16 Figure 16. 4V to 14V Input Voltage to 5V/1A Regulator with Current Foldback 18 COUT 220µF 10V OS-CON LTC1148 LTC1148-3.3/LTC1148-5 U TYPICAL APPLICATIO S VIN 5.2V TO 14V + NDS9435A CIN 100µF 20V D1 MBRS140T3 NDS9410A 1 1µF + 2 3 4 5 CT 390pF 10nF 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148 VIN PGND CT SGND INTVCC SHUTDOWN ITH VFB SENSE – SENSE + RC 1k 14 13 *L 50µH VN2222LL 12 0V: VOUT = 3.3V 5V: VOUT = 5V 11 10 SHUTDOWN 100pF R1A 33k 1% R1B 43k 1% 9 R2 56k 1% 8 1000pF COUT 220µF 10V ×2 OS-CON + RSENSE** 0.05Ω *COILTRONICS CTX50-2-MP **KRL SL-1-C1-0R050R LTC1148 • F17 VOUT 3.3V/2A OR 5V/2A Figure 17. Logic Selectable 5V/1A or 3.3V/1A High Efficiency Regulator U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 14-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) +0.035 0.325 –0.015 ( +0.889 8.255 –0.381 ) 0.005 (0.125) MIN 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 0.770* (19.558) MAX 14 13 12 11 10 9 8 1 2 3 4 5 6 7 0.255 ± 0.015* (6.477 ± 0.381) 0.018 ± 0.003 (0.457 ± 0.076) N14 1197 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) S Package 14-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0.337 – 0.344* (8.560 – 8.738) 0.004 – 0.010 (0.101 – 0.254) 14 13 12 11 10 9 8 0° – 8° TYP 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) S14 0695 1 2 3 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4 5 6 7 19 LTC1148 LTC1148-3.3/LTC1148-5 U TYPICAL APPLICATION VIN 10V TO 18V 1N4148 + 220Ω 2N3906 20k 220Ω CIN 2700µF 35V ×2 100 VIN = 10V 470nF 90 MUR110 N-CH IRFZ44 EFFICIENCY (%) 2N2222 D1 1N5818 VN2222LL VIN = 14V 80 70 1 1µF + 2 3 4 CT 820pF 5 6 CC 3300pF 7 P-DRIVE N-DRIVE NC NC LTC1148HV-5 VIN PGND CT SGND INTVCC SHUTDOWN ITH SENSE NC – SENSE + RC 510Ω 14 13 N-CH IRFZ44 0.1 12 1 LOAD CURRENT (A) 10 LTC1148 • F19 11 10 Figure 19. All N-Channel 5V/8A Efficiency SHUTDOWN 9 8 + 100Ω 1000pF 100Ω *COILTRONICS CTX33-10-KM **DALE LVR-3-0.01 60 *L 33µH 22k COUT 2200µF 16V ×3 For additional high efficiency application circuits, see Application Notes 54, 58 and 66 RSENSE** 0.01Ω VOUT 5V/8A LTC1148 • F18 Figure 18. All N-Channel 5V/8A High Efficiency Regulator (Burst Mode Operation Suppressed) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1142 Dual High Efficiency Synchronous Step-Down Switching Regulator Dual LTC1148 LTC1143 Dual High Efficiency Step-Down Switching Regulator Controller Nonsynchronous Dual Output LTC1147 High Efficiency Step-Down Switching Regulator Controller Nonsynchronous Equivalent to LTC1148, 8-Pin LTC1149 High Efficiency Synchronous Step-Down Switching Regulator VIN < 48V, Standard Threshold MOSFETs LTC1159 High Efficiency Synchronous Step-Down Switching Regulator VIN < 40V, Logic Level MOSFETs LTC1174 High Efficiency Step-Down and Inverting DC/DC Converter Nonsynchronous 8-Pin Internal Switch LTC1265 1.2A, High Efficiency Step-Down DC/DC Converter Nonsynchronous Internal Switch LTC1435A High Efficiency Low Noise Synchronous Step-Down Switching Regulator Synchronous N-Channel, Constant Frequency LTC1538-AUX Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator Auxiliary Linear Regulator, 5V Standby in Shutdown 20 Linear Technology Corporation 114835fc LT/GP 1098 2K REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1993