LTC1400 Complete SO-8, 12-Bit, 400ksps ADC with Shutdown U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Complete 12-Bit ADC in SO-8 Single Supply 5V or ±5V Operation Sample Rate: 400ksps Power Dissipation: 75mW (Typ) 72dB S/(N + D) and – 80dB THD at Nyquist No Missing Codes over Temperature Nap Mode with Instant Wake-Up: 6mW Sleep Mode: 30µW High Impedance Analog Input Input Range (1mV/LSB): 0V to 4.096 or ± 2.048V Internal Reference Can Be Overdriven Externally 3-Wire Interface to DSPs and Processors (SPI and MICROWIRETM Compatible) U APPLICATIONS ■ ■ ■ ■ ■ ■ ■ High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Audio and Telecom Processing Digital Radio Spectrum Analysis Low Power and Battery-Operated Systems Handheld or Portable Instruments The LTC1400 converts 0V to 4.096V unipolar inputs from a single 5V supply and ±2.048V bipolar inputs from ±5V supplies. Maximum DC specs include ±1LSB INL, ±1LSB DNL and 45ppm/°C drift over temperature. Guaranteed AC performance includes 70dB S/(N + D) and – 76dB THD at an input frequency of 100kHz, over temperature. The 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcontrollers and DSPs. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corp. U ■ The LTC ®1400 is a complete 400ksps, 12-bit A/D converter which draws only 75mW from a 5V or ± 5V supplies. This easy-to-use device comes complete with a 200ns sample-and-hold and a precision reference. Unipolar and bipolar conversion modes add to the flexibility of the ADC. The LTC1400 has two power saving modes: Nap and Sleep. In Nap mode, it consumes only 6mW of power and can wake up and convert immediately. In the Sleep mode, it consumes 30µW of power typically. Upon power-up from Sleep mode, a reference ready (REFRDY) signal is available in the serial data word to indicate that the reference has settled and the chip is ready to convert. TYPICAL APPLICATION Power Consumption vs Sample Rate Single 5V Supply, 400kHz, 12-Bit Sampling A/D Converter 100 5V 10µF VCC VSS 8 10 0.1µF MPU LTC1400 2 ANALOG INPUT (0V TO 4.096V) 2.42V REFOUT 10µF 3 + 0.1µF 4 AIN CONV VREF CLK GND DOUT 7 P1.4 6 P1.3 5 P1.2 SERIAL DATA LINK SUPPLY CURRENT (mA) 1 + NORMAL CONVERSION NAP MODE BETWEEN CONVERSION 1 SLEEP AND NAP MODE BETWEEN CONVERSION 0.1 SLEEP MODE BETWEEN CONVERSION 0.01 LTC1400 • TA01 6.4MHz CLOCK 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M SAMPLE RATE (Hz) LTC1400 • TA02 1 LTC1400 W U PACKAGE/ORDER INFORMATION W W U W (Notes 1, 2) Supply Voltage (VCC) ................................................. 7V Negative Supply Voltage (VSS).................... – 6V to GND Total Supply Voltage (VCC to VSS) Bipolar Operation Only ........................................ 12V Analog Input Voltage (Note 3) Unipolar Operation .................. – 0.3V to (VCC + 0.3V) Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ................................– 0.3V to 12V Bipolar Operation.........................(VSS – 0.3V) to 12V Digital Output Voltage Unipolar Operation .................. – 0.3V to (VCC + 0.3V) Bipolar Operation........... (VSS – 0.3V) to (VCC + 0.3V) Power Dissipation.............................................. 500mW Operation Temperature Range LTC1400C................................................ 0°C to 70°C LTC1400I............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C UW POWER REQUIRE E TS SYMBOL VCC PARAMETER Positive Supply Voltage (Note 6) VSS ICC Negative Supply Voltage (Note 6) Positive Supply Current ISS Negative Supply Current PD Power Dissipation U U A ALOG I PUT ORDER PART NUMBER TOP VIEW VCC 1 8 VSS AIN 2 7 CONV VREF 3 6 CLK GND 4 5 DOUT S8 PACKAGE 8-LEAD PLASTIC SO LTC1400CS8 LTC1400IS8 S8 PART MARKING TJMAX = 150°C, θJA = 130°C/ W 1400 1400I Consult factory for PDIP packages and Military grade parts. (Note 5) CONDITIONS Unipolar Bipolar Bipolar Only fSAMPLE = 400ksps Nap Mode Sleep Mode fSAMPLE = 400ksps, VSS = – 5V Nap Mode Sleep Mode fSAMPLE = 400ksps Nap Mode Sleep Mode MIN 4.75 4.75 – 2.45 TYP 15 1.0 5.0 0.3 0.2 1 75 6 30 ● ● ● ● ● ● ● ● ● MAX 5.25 5.25 – 5.25 30 3.0 20.0 0.6 0.5 5 160 20 125 UNITS V V V mA mA µA mA mA µA mW mW µW (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 7) 4.75V ≤ VCC ≤ 5.25V (Unipolar) 4.75V ≤ VCC ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar) ● ● IIN Analog Input Leakage Current During Conversions (Hold Mode) ● CIN Analog Input Capacitance Between Conversions (Sample Mode) During Conversions (Hold Mode) 2 U ABSOLUTE MAXIMUM RATINGS MIN TYP MAX 0 to 4.096 ±2.048 V V ±1 45 5 UNITS µA pF pF LTC1400 U CO VERTER CHARACTERISTICS PARAMETER With internal reference (Notes 5, 8) CONDITIONS MIN Resolution (No Missing Codes) ● Integral Linearity Error (Note 9) Differential Linearity Error Offset Error TYP 12 Bits ±1 LSB ● ±1 LSB ● ±6 ±8 LSB LSB ±15 LSB ±10 ±45 ppm/°C MIN TYP MAX UNITS 70 69 72 Full-Scale Error IOUT(REF) = 0 W U DY A IC ACCURACY ● VCC = 5V, VSS = – 5V, fSAMPLE = 400kHz SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal Commercial Industrial ● ● 200kHz Input Signal THD IMD dB dB 72 dB Total Harmonic Distortion Up to 5th Harmonic 100kHz Input Signal 200kHz Input Signal ● – 82 – 80 – 76 dB dB Peak Harmonic or Spurious Noise 100kHz Input Signal 200kHz Input Signal ● – 84 – 82 – 76 dB dB Intermodulation Distortion fIN1 = 99.51kHz, fIN2 = 102.44kHz fIN1 = 199.12kHz, fIN2 = 202.05kHz – 82 – 70 Full Power Bandwidth Full Linear Bandwidth (S/(N + D) ≥ 68dB) U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Tempco IOUT = 0 VREF Line Regulation 4.75V ≤ VCC ≤ 5.25V – 5.25V ≤ VSS ≤ 0V VREF Load Regulation VREF Wake-Up Time from Sleep Mode (Note 7) U U SYMBOL PARAMETER 4 MHz 900 kHz (Note 5) MIN TYP MAX 2.400 2.420 2.440 ±10 ±45 ● UNITS V ppm/°C LSB/ V LSB/ V 0 ≤ IOUT ≤ 1mA 2 LSB/mA CVREF = 10µF 4 ms (Note 5) CONDITIONS MIN VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIN Digital Input Current VIN = 0V to VCC ● CIN Digital Input Capacitance VOH High Level Output Voltage Low Level Output Voltage dB dB 0.01 0.01 DIGITAL I PUTS AND OUTPUTS VOL UNITS ● (Note 10) Full-Scale Tempco MAX VCC = 4.75V, IO = – 10µA VCC = 4.75V, IO = – 200µA ● VCC = 4.75V, IO = 160µA VCC = 4.75V, IO = 1.6mA ● TYP MAX 2.0 UNITS V 0.8 V ±10 µA 5 pF 4.7 V V 4.0 0.05 0.10 0.4 V V 3 LTC1400 U U DIGITAL I PUTS AND OUTPUTS (Note 5) SYMBOL PARAMETER CONDITIONS MIN IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VCC TYP ● MAX UNITS ±10 µA COZ Hi-Z Output Capacitance DOUT (Note 7) 15 pF ISOURCE Output Source Current VOUT = 0 – 10 mA ISINK Output Sink Current VOUT = VCC 10 mA WU TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Frequency (Note 6) ● MIN tCONV Conversion Time fCLK = 6.4MHz ● tACQ Acquisition Time (Unipolar Mode) (Bipolar Mode VSS = – 5V) (Note 7) ● ● fCLK CLK Frequency tCLK CLK Pulse Width (Note 7) tWK(NAP) Time to Wake Up from Nap Mode (Note 7) t1 TYP MAX 400 UNITS kHz 230 200 2.1 µs 300 270 ns ns 6.4 MHz ● 0.1 ● 50 CLK Pulse Width to Return to Active Mode ● 50 ns t2 CONV↑ to CLK↑ Setup Time ● 80 ns t3 CONV↑ After Leading CLK↑ t4 CONV Pulse Width (Note 11) t5 Time from CLK↑ to Sample Mode (Note 7) t6 Aperture Delay of Sample-and-Hold Jitter < 50ps (Note 7) t7 Minimum Delay Between Conversion (Unipolar Mode) (Bipolar Mode VSS = – 5V) t8 Delay Time, CLK↑ to DOUT Valid t9 Delay Time, CLK↑ to DOUT Hi-Z t10 Time from Previous Data Remains Valid After CLK↑ The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: When these pin voltages are taken below VSS (ground for unipolar mode) or above VCC, they will be clamped by internal diodes. This product can handle input currents greater than 40mA below VSS (ground for unipolar mode) or above VCC without latch-up. Note 4: When these pin voltages are taken below VSS (ground for unipolar mode), they will be clamped by internal diodes. This product can handle input currents greater than 40mA below VSS (ground for unipolar mode) without latch-up. These pins are not clamped to VCC. Note 5: VCC = 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise specified. 4 ns 350 ns ● 0 ns ● 50 ns 80 ns ● 45 65 ns ● ● 265 235 385 355 ns ns CLOAD = 20pF ● 40 80 ns CLOAD = 20pF ● 40 80 ns CLOAD = 20pF ● 14 25 ns Note 6: Recommended operating conditions. Note 7: Guaranteed by design, not subject to test. Note 8: Linearity, offset and full-scale specifications apply for unipolar and bipolar modes. Note 9: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 10: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 11: The rising edge of CONV starts a conversion. If CONV returns low at a bit decision point during the conversion, it can create small errors. For best performance ensure that CONV returns low either within 120ns after conversion starts (i.e., before the first bit decision) or after the 14 clock cycle. (Figure 13 Timing Diagram). LTC1400 U W TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code Integral Nonlinearity vs Output Code 1.00 80 fSAMPLE = 400kHz VIN = 0dB fSAMPLE = 400kHz 0.50 0.25 0 –0.25 –0.50 –0.75 0.75 SIGNAL/(NOISE + DISTORTION) (dB) 0.75 INTEGRAL NONLINEARITY (LSBs) DIFFERENTIAL NONLINEARITY (LSBs) 1.00 S/(N + D) vs Input Frequency and Amplitude 0.50 0.25 0 –0.25 –0.50 –0.75 70 60 VIN = –20dB 50 40 30 20 VIN = – 60dB 10 fSAMPLE = 400kHz –1.00 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE LTC1400 • TPC01 Acquisition Time vs Source Impedance 4500 0 SPURIOUS-FREE DYNAMIC RANGE (dB) 60 50 40 30 20 10 fSAMPLE = 400kHz fSAMPLE = 400kHz –10 –20 –30 –40 –50 –60 –70 3500 3000 2500 2000 1500 –80 1000 –90 500 –100 0 10 0 10 1000 100 INPUT FREQUENCY (kHz) 100 INPUT FREQUENCY (kHz) 2.425 2.420 2.415 2.410 2.405 2.400 2.395 2.390 –8 –7 –6 –5 –4 –3 –2 –1 LOAD CURRENT (mA) 0 1 2 LTC1400 • TPC03 100 1000 RSOURCE (Ω) 10000 LTC1400 • TPC05 Power Supply Feedthrough vs Ripple Frequency Supply Current vs Temperature 20 0 fSAMPLE = 400kHz –10 fSAMPLE = 400kHz –20 SUPPLY CURRENT (mA) 2,430 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) 2.435 10 1000 LTC1400 • TPC08 LTC1400 • TPC07 Reference Voltage vs Load Current TA = 25°C 4000 ACQUISITION TIME (ns) 70 SIGNAL-TO-NOISE RATIO (dB) LTC1400 • TPC06 Peak Harmonic or Spurious Noise vs Input Frequency 80 1000 100 INPUT FREQUENCY (kHz) LTC1400 • TPC02 Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency REFERENCE VOLTAGE (V) 10 –30 –40 –50 VSS (VRIPPLE = 10mV) –60 –70 15 10 5 –80 VCC (VRIPPLE = 1mV) –90 –100 1 10 100 RIPPLE FREQUENCY (kHz) 1M LTC1400 • TPC07.5 0 –50 –25 50 75 0 25 TEMPERATURE (°C) 100 125 LTC1400 • TPC04 5 LTC1400 U U U PIN FUNCTIONS VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10µF tantalum in parallel with 0.1µF ceramic). AIN (Pin 2): Analog Input. 0V to 4.096V (Unipolar), ±2.048V (Bipolar). VREF (Pin 3): 2.42V Reference Output. Bypass to GND (10µF tantalum in parallel with 0.1µF ceramic). GND (Pin 4): Ground. GND should be tied directly to an analog ground plane. DOUT (Pin 5): The A/D conversion result is shifted out from this pin. CLK (Pin 6): Clock. This clock synchronizes the serial data transfer. A minimum CLK pulse of 50ns will cause the ADC to wake up from Nap or Sleep mode. CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK low and pulsing CONV two/four times will put the ADC into Nap/Sleep mode. VSS (Pin 8): Negative Supply. – 5V for bipolar operation. Bypass to GND with 0.1µF ceramic. VSS should be tied to GND for unipolar operation. W FUNCTIONAL BLOCK DIAGRA U ZEROING SWITCH U CSAMPLE VCC AIN GND VSS VREF 2.42V REF 12-BIT CAPACITIVE DAC COMP CLK CONV 12 CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO SERIAL CONVERTER DOUT LTC1400 • BD01 TEST CIRCUITS 5V 3k DOUT DOUT 3k Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD CLOAD Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z LTC1400 • TC01 6 LTC1400 U W U U APPLICATIONS INFORMATION Conversion Details Dynamic Performance The LTC1400 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output based on a precision internal reference. The control logic provides easy interface to microprocessors and DSPs through 3-wire connections. The LTC1400 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a typical LTC1400 FFT plot. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquired phase and the comparator offset is nulled by the feedback switch. In this acquire phase, it typically takes 200ns for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switches connect CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the input voltage, are output through the serial pin DOUT. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from DC to half the sampling frequency. Figure 2a shows a typical spectral content with a 400kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 200kHz as shown in Figure 2b. 0 fSAMPLE = 400kHz fIN = 94.824kHz SINAD = 72.5dB THD = – 82dB –10 –20 –30 AMPLITUDE (dB) A rising edge on the CONV input starts a conversion. At the start of a conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. –40 –50 – 60 –70 –80 –90 –100 –110 –120 SAMPLE 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) S1 SAMPLE CSAMPLE – AIN HOLD LTC1400 • F02a + DAC Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency in Bipolar Mode COMP Effective Number of Bits CDAC VDAC S A R DOUT The effective number of bits (ENOBs) is a measurement of the effective resolution of an ADC and is directly related to the S/(N + D) by the equation: LTC1400 • F01 Figure 1. AIN Input N= S /(N + D) – 1.76 6.02 7 LTC1400 U W U U APPLICATIONS INFORMATION 0 fSAMPLE = 400kHz fIN = 199.121kHz SINAD = 72.1dB THD = – 80dB –10 –20 AMPLITUDE (dB) –30 THD = 20 log –40 V22 + V32 + V42 + …Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1400 has good distortion performance up to the Nyquist frequency and beyond. –50 – 60 –70 –80 –90 –100 –120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) LTC1400 • F02b Figure 2b. LTC1400 Nonaveraged, 4096 Point FFT Plot with 200kHz Input Frequency in Bipolar Mode where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1400 maintains very good ENOBs up to the Nyquist input frequency of 200kHz (refer to Figure 3). EFFECTIVE NUMBER OF BITS 10 9 NYQUIST FREQUENCY 62 56 50 8 7 6 5 4 3 2 1 fSAMPLE = 400kHz 0 100k 10k INPUT FREQUENCY (Hz) SIGNAL/(NOISE + DISTORTION) (dB) 68 11 1M LTC1400 • F03 Figure 3. Effective Bits and Signal-to-Noise + Distortion vs Input Frequency in Bipolar Mode Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is expressed as: 8 0 –10 fSAMPLE = 400kHz –20 –30 –40 –50 –60 –70 3RD HARMONIC THD –80 –90 –100 10k 2ND HARMONIC 100k INPUT FREQUENCY (Hz) 1M LTC1400 • F04 Figure 4. Distortion vs Input Frequency in Bipolar Mode 74 12 AMPLITUDE (dB BELOW THE FUNDAMENTAL) –110 Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while the 3rd order IMD terms includes (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula. IMD( fa ± fb) = 20log Amplitude at (fa ± fb) Amplitude at fa LTC1400 U U W U APPLICATIONS INFORMATION 0 fSAMPLE = 400kHz fa = 99.512kHz fb = 102.441kHz –10 –20 fa fb AMPLITUDE (dB) –30 –40 –50 – 60 2fa + fb 2fa – fb 2fb + fa fb – fa 3fb –70 –80 –90 3fa 2fa 2fb – fa fa + fb 2fb –100 –110 –120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) LTC1400 • F05 Figure 5. Intermodulation Distortion Plot in Bipolar Mode Figure 5 shows the IMD performance at a 100kHz input. Peak Harmonic or Spurious Noise in 200ns to small load current transient will allow maximum speed operation. If a slower op amp is used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the LT ® 1360 and the LT1363 op amps. LTC1400 comes with a built-in unipolar/bipolar detection circuit. If VSS potential is forced below GND, the internal circuitry will automatically switch to bipolar mode. The following list is a summary of the op amps that are suitable for driving the LTC1400, more detailed information is available in the Linear Technology databooks and the LinearViewTM CD-ROM. LT 1215/LT1216: Dual and quad 23MHz, 50V/µs single supply op amps. Single 5V to ±15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a fullscale input signal. LT1223: 100MHz video current feedback amplifier. ±5V to ±15V supplies, 6mA supply current. Low distortion up to and above 400kHz. Low noise. Good for AC applications. Full Power and Full Linear Bandwidth LT1227: 140MHz video current feedback amplifier. ±5V to ±15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. The full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1400 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The analog input of the LTC1400 is easy to drive. It draws only one small current spike while charging the sampleand-hold capacitor at the end of a conversion. During conversion, the analog input draws only a small leakage current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. ±2V to ±15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V supplies. 3.8mA supply current. Good AC and DC specs. 70ns settling to 0.5LSB. LT1363: 50MHz, 450V/µs op amps. ±5V to ±15V supplies. 6.3mA supply current. Good AC and DC specs. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and quad 50MHz, 450V/µs op amps. ±5V to ±15V supplies, 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. Internal Reference The LTC1400 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory 9 LTC1400 U W U U APPLICATIONS INFORMATION UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT Figure 8 shows the ideal input/output characteristics for the LTC1400. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, … FS – 1.5LSB). The output code is natural binary with 1LSB = 4.096/4096 = 1mV. Figure 9 shows the input/output transfer characteristics for the bipolar mode in two’s complement format. 1LSB = FS = 4.096 4096 4096 111...111 111...110 111...101 OUTPUT CODE trimmed to 2.42V. It is internally connected to the DAC and is available at Pin 3 to provide up to 1mA of current to an external load. For minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10µF tantalum in parallel with a 0.1µF ceramic). The VREF pin can be driven with a DAC or other means to provide input span adjustment in bipolar mode. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should not be driven to more than 5V. Figure 6 shows an LT 1306 op amp driving the reference pin. Figure 7 shows a typical reference, the LT1019A-5 connected to the LTC1360. This will provide an improved drift (equal to the maximum 5ppm/°C of the LT1019A-5) and a ±4.231V full scale. If VREF is forced lower than 2.42V, the REFRDY bit in the serial data output will be forced to low. 111...100 UNIPOLAR ZERO 000...011 000...010 000...001 5V 000...000 INPUT RANGE ±0.846VREF(OUT) 0V AIN VCC 1 LSB FS – 1LSB INPUT VOLTAGE (V) LTC1400 • F08 + VREF(OUT) ≥ 2.45V LTC1400 Figure 8. LTC1400 Unipolar Transfer Characteristics VREF LT1360 – 3Ω 10µF 011...111 GND VSS BIPOLAR ZERO 011...110 LTC1400 • F06 Figure 6. Driving the VREF with the LT1360 Op Amp 5V INPUT RANGE ±4.231V (= ±0.846VREF) AIN VCC OUTPUT CODE –5V 000...001 000...000 111...111 111...110 100...001 100...000 10V LTC1400 VIN VREF VOUT LT1019A-5 –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB LTC11400 • F09 3Ω Figure 9. LTC1400 Bipolar Transfer Characteristics 10µF GND GND VSS –5V LTC1400 • F07 Figure 7. Supplying a 5V Reference Voltage to the LTC1400 with the LT1019A-5 10 Unipolar Offset and Full-Scale Error Adjustments In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Figure 10a shows the extra components required for full-scale LTC1400 U U W U APPLICATIONS INFORMATION error adjustment. Figure 10b shows offset and full-scale adjustment. Offset error must be adjusted before fullscale error. Zero offset is achieved by applying 0.5mV (i.e., 0.5LSB) at the input and adjusting the offset trim until the LTC1400 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 4.0945V (FS – 1.5LSB or last code transition) at the input and adjust R5 until the LTC1400 output code flickers between 1111 1111 1110 and 1111 1111 1111. R1 50Ω + VIN A1 – AIN R4 100Ω R2 10k LTC1400 R3 10k FULL-SCALE ADJUST GND ADDITIONAL PINS OMITTED FOR CLARITY ±20LSB TRIM RANGE LTC1400 • F10a Figure 10a. LTC1400 Full-Scale Adjust Circuit ANALOG INPUT 0V TO 4.096V Bipolar Offset and Full-Scale Error Adjustments R1 10k + 10k AIN A1 R2 10k – 5V R4 100k LTC1400 R9 20Ω R5 4.3k FULL-SCALE ADJUST R3 100k 5V R7 100k R8 10k OFFSET ADJUST R6 400Ω LTC1400 • F10b Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit ANALOG INPUT ±2.048V R1 10k + R2 10k A1 – AIN R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R6 200Ω R7 100k LTC1400 5V R8 20k OFFSET ADJUST –5V LTC1400 • F10c Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Bipolar offset error adjustment is achieved by applying an input voltage of – 0.5mV (– 0.5LSB) to the input in Figure 10c and adjusting the op amp until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.0465V (FS – 1.5LSBs) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1400, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by GND. High quality tantalum and ceramic bypass capacitors should be used at the VCC and VREF pins as shown in the Typical Application on the first page of this data sheet. For the bipolar mode, a 0.1µF ceramic provides adequate bypassing for the VSS pin. For optimum performance, a 10µF surface mount AVX capacitor with a 0.1µF ceramic is recommended for the VCC and VREF pins. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. In unipolar mode operation, VSS should be isolated from any noise source before shorting to the GND pin. 11 LTC1400 U U W U APPLICATIONS INFORMATION Input signal leads to AIN and signal return leads from GND (Pin 4) should be kept as short as possible to minimize noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. ANALOG SUPPLY –5V GND DIGITAL SUPPLY 5V GND 5V nated at the LTC1400 GND pin. The ground return from the LTC1400 Pin 4 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. Power-Down Mode + VSS GND LTC1400 + VCC + GND VCC DIGITAL CIRCUITRY LTC1400 • F11 Figure 11. Power Supply Connection Figure 11 shows the recommended system ground connections. All analog circuitry grounds should be termi- Upon power-up, the LTC1400 is initialized to the active state and is ready for conversion. However, the chip can be easily placed into the Nap or Sleep mode by exercising the right combination of CLK and CONV signal. In the Nap mode all power is off except the internal reference, which is still active and provides 2.42V output voltage to the other circuitry. In this mode, the ADC draws only 6mW of power instead of 75mW (for minimum power, the logic inputs must be within 500mV of the supply rails). The wake-up time from the Nap mode to the active mode is CLK t1 t1 CONV NAP SLEEP VREF REFRDY LTC1400 • F08 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD. Figure 12. Nap Mode and Sleep Mode Waveforms 12 LTC1400 U U W U APPLICATIONS INFORMATION 350ns. In the Sleep mode, power consumption is reduced to a minimum by cutting off the supply to all internal circuitry including the reference. Figure 12 shows the ways to power down the LTC1400. The chip can enter the Nap mode by keeping the CLK signal low and pulsing the CONV signal twice. For Sleep mode operation, CONV signal should be activated four times while CLK is kept low. DIGITAL INTERFACE The digital interface requires only three digital lines. CLK and CONV are both inputs, and the DOUT output provides the conversion result in serial form. Figure 13 shows the digital timing diagram of the LTC1400 during the A/D conversion. The CONV rising edge starts the conversion. Once initiated, it can not be restarted until the conversion is completed. If the time from CONV signal to CLK rising edge is less than t2, the digital output will be delayed by one clock cycle. The LTC1400 can be returned to active mode easily. The rising edge of CLK will wake-up the LTC1400. During the transition from Sleep mode to active mode, the VREF voltage ramp-up time is a function of the loading conditions. With a 10µF bypass capacitor, the wake-up time from Sleep mode is typically 4ms. A REFRDY signal will be activated once the reference has settled and is ready for an A/D conversion. This REFRDY bit is output to the DOUT pin before the rest of the A/D converted code. The digital output data is updated on the rising edge of the CLK line. DOUT data should be captured by the receiving system on the rising CLK edge. Data remains valid for a minimum time of t10 after the rising CLK edge to allow capture to occur. t2 t7 t3 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 2 CLK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD SAMPLE HOLD t8 DOUT Hi-Z REFRDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z REFRDY tCONV tSAMPLE LTC1400 • F13 Figure 13. ADC Digital Timing Diagram CLK CLK VIH VIH t8 t9 t 10 90% VOH D OUT D OUT VOL 10% LTC1400 • F14 Figure 14. CLK to DOUT Delay 13 LTC1400 U TYPICAL APPLICATIONS Hardware Interface to TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX) TMS320C50 5V 1 + 0.1µF 10µF UNIPOLAR INPUT 2 CLK 6 7 CONV LTC1400 5 3 VREF DOUT + 10µF VCC TCLKX TCLKR TFSX TFSR 0.1µF AIN VSS GND 8 4 TDR LTC1400 • TA04a Logic Analyzer Waveforms Show 3.2µs Throughput Rate (Input Voltage = 3.046V, Output Code = 1011 1110 0110 = 304610) Data from LTC1400 Loaded into TMS320C50’s TRCV Register X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Data Stored in TMS320C50’s Memory (in Right Justified Format) 0 14 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LTC1400 U TYPICAL APPLICATIONS TMS320C50 Code for Circuit THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO TMS320C50 FRAME SYNC PULSE IS GENERATED FROM TFSX *Initialization* .mmregs ;- - Initialized data memory to zero .ds 0F00h DATA0 .word 0 DATA1 .word 0 DATA2 .word 0 DATA3 .word 0 DATA4 .word 0 DATA5 .word 0 ;- - Set up the ISR vector .ps 080Ah rint : B RECEIVE xint : B TRANSMIT trnt : B TREC txnt : B TTRANX ;- - Setup the reset vector .ps 0A00h .entry START: ; Defines global symbolic names ; Initialize data to zero ; Begin sample data location ;. ; Location of data ;. ;. ; End sample data location ; Serial ports interrupts ; 0A; ; 0C; ; 0E; ; 10; *TMS32C050 Initialization* SETC INTM ; Temporarily disable all interrupts LDP #0 ; Set data page pointer to zero OPL #0834h, PMST ; Set up the PMST status and control register LACC #0 SAMM CWSR ; Set software wait state to 0 SAMM PDWSR ; *Configure Serial Port* SPLK #0038h, TSPC ; Set TDM Serial Port ; TDM = 0 Stand Alone mode ; DLB=0 Not loop back ; FO=0 16 Bits ; FSM=1 Burst Mode ; MCM=1 CLKX is generated internally ; TXM=1 FSX as output pin ; Put serial port into reset ; (XRST=RRST=0) SPLK #00F8h, TSPC ; Take Serial Port out of reset ; (XRST=RRST=1) SPLK #0FFFFh, IFR ; Clear all the pending interrupts *Start Serial Communication* SACL TDXR ; Generate frame sync pulse SPLK #040h, IMR ; Turn on TRNT receiver interrupt CLRC INTM ; Enable interrupt CLRC SXM ; For Unipolar input, set for right shift ; with no sign extension MAR *AR7 ; Load the auxiliary register pointer with seven LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h ; as the begin address for data storage WAIT: NOP ; Wait for a receive interrupt NOP ; NOP ; SACL TDXR ; !! regenerate the frame sync pulse B WAIT ; ; - - - - - - - end of main program - - - - - - - - - - ; *Receiver Interrupt Service Routine* TREC: LAMM TRCV ; Load the data received from LTC1400 SFR ; Shift right two times SFR ; AND #1FFFh, 0 ; ANDed with #1FFFh ; For converting the data to right ; justified format ; SACL *+, 0 ; Write to data memory pointed by AR7 and ; increase the memory address by one LACC AR7 ; SUB #0F05h,0 ; Compare to end sample address #0F05h BCND END_TRCV, GEQ ; If the end sample address has exceeded jump to END_TRCV ; SPLK #040h, IMR ; Else Re-enable the TRNT receive interrupt RETE ; Return to main program and enable interrupt *After Obtained the Data from LTC1400, Program Jump to END_TRCV* END_TRCV: SPLK #002h, IMR ; Enable INT2 for program to halt CLRC INTM SUCCESS: B SUCCESS *Fill the Unused Interrupt with RETE, to avoid program get “lost”* TTRANX: RETE RECEIVE: RETE TRANSMIT: RETE INT2: B halt ; Halts the running CPU 15 LTC1400 U TYPICAL APPLICATIONS LTC1400 Interface to ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0) ADSP2181 5V 1 + 10µF UNIPOLAR INPUT 0.1µF 2 AIN CONV LTC1400 3 VREF DOUT + 0.1µF 10µF CLK VCC VSS GND 8 4 6 SCLKO 7 RFSO 5 DR0 LTC1400 • TA05a Logic Analyzer Waveforms Show 2.88µs Throughput Rate (Input Voltage = 2.240V, Output Code = 1000 1100 0000 = 224010) Data from LTC1400 (Normal Mode) X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X LTC1400 • TA05c Data Stored in ADSP2181’s Memory (Normal Mode, SLEN = D) 0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LTC1400 • TA05d 16 LTC1400 U TYPICAL APPLICATIONS ADSP2181 Code for Circuit THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181 FRAME SYNC PULSE IS GENERATED FROM RFS0 /*Section 1: Initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 TX int*/ ax0 = rx0; /*Section 5*/ dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/ rti; /* */ /* */ /*end of SPORT0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 TX (IRQ1) int*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 RX (IRQ0) int*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ rti; rti; rti; rti; /*code vectors here upon POWER DOWN int*/ /*Section 2: Configure SPORT0*/ start: /*to configure SPORT0 control reg*/ /*SPORT0 address = 0X3FF6*/ /*RFS is used for frame sync generation*/ /*RFS0 is internal, TFS is not use*/ /*bit 0-3 = Slen*/ /*F = 15 = 1111*/ /*E = 14 = 1110*/ /*D = 13 = 1101*/ /*bit 4,5 data type right justified zero filled MSB*/ /*bit 6 INVRFS = 0*/ /*bit 7 INVTFS = 0*/ /*bit 8 IRFS=1 receive internal frame sync*/ /*bit 9,10,11 are for TFS (don’t care)*/ /*bit 12 TFSW=1 receive is Normal mode*/ /*bit 13 RTFS=1 receive is framed mode*/ /*bit 14 ISCLK internal = 1*/ /*bit 15 multichannel mode = 0*/ ax0 = 0x6B0D; /*normal mode, bit12=0*/ /*if alternate mode bit12=1, ax0=0x7F0E*/ dm (0x3FF6) =ax0; /*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/ /*to configure CLKDIV reg*/ ax0= 2; dm(0x3FF5) =ax0; /*set the serial clock divide modulus reg SCLKDIV*/ /*the input clock frequency = 16.67MHz*/ /*CLKOUT frequency = 2x = 33MHz*/ /*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/ /*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/ /*to Configure RFSDIV*/ ax0 = 15; /*set the RFSDIV reg = 15*/ /*=> the frame sync pulse for every 16 SCLK*/ /*if frame sync pulse in every 15 SCLK, ax0=14*/ dm(0x3FF4) =ax0; /*to setup interrupt*/ ifc= 0x0066; /*clear any extraneous SPORT interrupts*/ icntl= 0; /*IRQXB = level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ /*bit 1 = SPORT1 or IRQ0B int = 0*/ /*bit 2 = SPORT1 or IRQ1B int = 0*/ /*bit 3 = BDMA int = 0*/ /*bit 4 = IRQEB int = 0*/ /*bit 5 = SPORT0 receive int = 1*/ /*bit 6 = SPORT0 transmit int = 0*/ /*bit 7 = IRQ2B int = 0*/ /*enable SPORT0 receive interrupt*/ /*Section 4: Configure System Control Register and Start Communication*/ /*to configure system control reg*/ ax0 = dm(0x3FFF); /*read the system control reg*/ ay0 = 0xFFF0; ar = ax0 AND ay0; /*set wait state to zero*/ ay0 = 0x1000; ar = ar OR ay0; /*bit12 = 1, enable SPORT0*/ dm(0x3FFF) = ar; /*frame sync pulse regenerated automatically*/ cntr = 5000; do waitloop until ce; nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod; 17 LTC1400 U TYPICAL APPLICATIONS Quick Look Circuit for Converting Data to Parallel Format 5V 5V 1 V CC + 10µF VSS 8 CONV 0.1µF LTC1400 2.42V REFERENCE OUTPUT ANALOG INPUT (0V TO 4.096V) 2 CONV AIN 3 V REF + 10µF 0.1µF 4 GND CLK DOUT 7 12 10 SRCLR QA QB 11 QC SRCK 74HC595 QD 14 QE SER QF 13 QG G QH QH' 6 5 3-WIRE SERIAL INTERFACE LINK 12 CLK RCK 10 SRCLR QA QB 11 QC SRCK 74HC595 QD 14 QE SER QF 13 QG G QH QH' RCK 15 1 2 3 4 5 6 7 9 15 1 2 3 4 5 6 7 9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 REFRDY LTC1400 • TA03 18 LTC1400 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC SO8 0695 19 LTC1400 U TYPICAL APPLICATIONS LTC1400 Interface to TMS320C50 TMS320C50 5V 1 + UNIPOLAR INPUT 0.1µF 10µF VCC 2 6 CLK 7 CONV LTC1400 5 3 VREF DOUT AIN + 10µF TCLKX TCLKR TFSX TFSR 0.1µF VSS GND 8 4 TDR LTC1400 • TA04a LTC1400 Interface to ADSP2181 ADSP2181 5V 1 + 10µF 0.1µF UNIPOLAR INPUT 2 AIN CONV LTC1400 3 VREF DOUT + 10µF CLK VCC 0.1µF VSS GND 8 4 6 7 5 SCLKO RFSO DR0 LTC1400 • TA05a RELATED PARTS 12-Bit Parallel Output ADCs PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION LTC1272 250ksps 75mW Single 5V, 7572 Upgrade LTC1273/LTC1275/LTC1276 300ksps 75mW With Clock and Reference LTC1274/LTC1277 100ksps 10mW Low Power ADCs with 1µA Shutdown LTC1278/LTC1279 500/600ksps 75mW 70dB at Nyquist, Low Power, Single 5V LTC1282 140ksps 12mW 3V or ±3V ADC with Clock and Reference LTC1410 1.25Msps 150mW 71dB at Nyquist, Differential Input 12-Bit Serial Output ADCs PART NUMBER VCC SAMPLE RATE POWER DISSIPATION LTC1285/LTC1288 3V 7.5/6.6ksps 0.48mW 3V, One or Two Input, Micropower, SO-8 LTC1286/LTC1298 DESCRIPTION 5V 12.5/11.1ksps 1.25mV One or Two Input, Micropower, SO-8 LTC1290 5/±5V 50ksps 30mW 8 Input, Full-Duplex Serial I/O LTC1296 5/±5V 46.5ksps 30mW 8 Input, Half-Duplex Serial I/O, Power Shutdown Output 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1400f LT/TP 0597 7K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1995