Revised June 2005 74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs General Description Features The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. ■ Input and output interface capability to systems at 5V VCC The LVT162240 and LVTH162240 are designed with equivalent 25: series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These inverting buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162240 and LVTH162240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Outputs include equivalent series resistance of 25: to make external termination resistors unnecessary and reduce overshoot and undershoot ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162240), also available without bushold feature (74LVT162240) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Functionally compatible with the 74 series 162240 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Number Package Description 74LVT162240MEA (Note 1) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162240MTD (Note 1) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 74LVTH162240MEX (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVTH162240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVTH162240MTX (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 2: Use this Order Number to receive devices in Tape and Reel. © 2005 Fairchild Semiconductor Corporation DS012490 www.fairchildsemi.com 74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs June 1999 74LVT162240 • 74LVTH162240 Logic Symbol Pin Descriptions Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 3-STATE Outputs Truth Table Connection Diagram Inputs Outputs OE1 I0–I3 O0–O3 L L H L H L H X Z Inputs Outputs OE2 I4–I7 O4–O7 L L H L H L H X Z Inputs Outputs OE3 I8–I11 O8–O11 L L H L H L H X Z I12–I15 O12–O15 L L H L H L H X Z Inputs OE4 Outputs H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Functional Description 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 4) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage Min Max 2.7 3.6 Units V 0 5.5 V IOH HIGH-Level Output Current 12 mA IOL LOW-Level Output Current 12 mA TA Free Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 40 85 qC 0 10 ns/V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter TA Min 40qC to 85qC Typ Max Units Conditions (Note 5) 1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC0.2 3.0 2.0 2.7 2.7–3.6 2.0 0.8 18 mA V II V VO d 0.1V or V VO t VCC 0.1V V IOH 100 PA IOH 12 mA IOL 100 PA VOL Output LOW Voltage II(HOLD) Bushold Input Minimum Drive 3.0 3.0 (Note 6) Bushold Input Over-Drive Current to Change State II Input Current 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 2.7 0.2 3.0 500 PA 500 Control Pins Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE Current 5 3.6 V PA 75 (Note 6) II(OD) 0.8 75 PA 1 0 r100 PA 0–1.5V r100 PA IOL 12 mA VI 0.8V VI 2.0V (Note 7) (Note 8) 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled 3 www.fairchildsemi.com 74LVT162240 • 74LVTH162240 Absolute Maximum Ratings(Note 3) 74LVT162240 • 74LVTH162240 DC Electrical Characteristics Symbol (Continued) VCC (V) Parameter 40qC to 85qC TA Max Units 3.6 0.19 mA 3.6 0.2 mA Min Typ Conditions (Note 5) ICCZ Power Supply Current 'ICC Increase in Power Supply Current (Note 9) Note 5: All typical values are at VCC 3.3V, TA VCC d VO d 5.5V, Outputs Disabled One Input at V CC 0.6V Other Inputs at V CC or GND 25qC. Note 6: Applies to bushold versions only (74LVTH162240). Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 9: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 10) Parameter (V) 25qC TA VCC Min Typ Conditions Units CL Max 500: 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 11) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 11) Note 10: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 11: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA Symbol 40qC to 85qC, CL 3.3V r 0.3V VCC Parameter Min Typ 500: 50 pF, RL VCC 2.7V Max Min Max 1.0 4.0 1.0 4.8 1.0 4.0 1.0 4.6 1.0 4.8 1.0 5.7 1.0 4.9 1.0 6.1 2.0 4.9 2.0 5.4 2.0 4.5 2.0 4.5 Units (Note 12) Propagation Delay Data to Output tPLH tPHL Output Enable Time tPZH tPZL tPHZ Output Disable Time tPLZ tOSHL Output to Output Skew tOSLH (Note 13) Note 12: All typical values are at VCC 3.3V, TA 1.0 ns ns ns 1.0 ns 25qC. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 14) Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 14: Capacitance is measured at frequency f www.fairchildsemi.com 0V or VCC 0V or VCC 1 MHz, per MIL-STD-883, Method 3012. 4 Typical Units 4 pF 8 pF 74LVT162240 • 74LVTH162240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 5 www.fairchildsemi.com 74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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