Intersil ISL54227 High-speed usb 2.0 (480mbps) dpst switch with overvoltage protection (ovp) and dedicated charger port detection Datasheet

ISL54227
Features
The Intersil ISL54227 is a single supply, dual SPST
(Single Pole/Single Throw) switch that is configured as a
DPST. It can operate from a single 2.7V to 5.25V supply.
The part was designed for switching or isolating a USB
high-speed source or a USB high-speed and full-speed
source in portable battery powered products.
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
The 3.5Ω SPST switches were specifically designed to
pass USB full speed and USB high speed data signals.
They have high bandwidth and low capacitance to pass
USB high speed data signals with minimal distortion.The
device has two logic control input pins (OE and LP) to
control the SPST switches.
The ISL54227 has OVP detection circuitry on the COM
pins to open the SPST switches when the voltage at
these pins exceeds 3.8V or goes negative by -0.45V. It
isolates fault voltages up to +5.25V or down to -5V from
getting passed to the other side of the switch, thereby
protecting the USB down-stream transceiver. It has an
alarm indicator output pin (ALM) to indicate when the
part is in the overvoltage condition.
The part has an interrupt (INT) output pin to indicate a
1 to 1 (high/high) state on the COM lines to inform the
µprocessor when entering a dedicated charging port
mode of operation.
• 1.8V Logic Compatible (2.7V to +3.6V supply)
• Alarm Overvoltage Indicator Output
• Charger Interrupt Indicator Output
• Low Power State
• Power OFF Protection
• COM Pins Overvoltage Detection and Protection for
+5.25V and -5V Fault Voltages
• -3dB Frequency . . . . . . . . . . . . . . . . . . . . 790MHz
• Low ON Capacitance @ 240MHz . . . . . . . . . . . . 2pF
• Low ON-Resistance . . . . . . . . . . . . . . . . . . . . 3.5Ω
• Single Supply Operation (VDD) . . . . . 2.7V to 5.25V
• Available in µTQFN and TDFN Packages
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and
Overvoltage Requirements without Additional
External Components
Applications*(see page 16)
• MP3 and other Personal Media Players
• Cellular/Mobile Phones, PDA’s
The ISL54227 is available in 10 Ld 1.8mmx1.4mm
µTQFN and 10 Ld 3mmx3mm TDFN packages. It
operates over a temperature range of -40 to +85°C.
• Digital Cameras and Camcorders
Typical Application
USB 2.0 HS Eye Pattern with
Switches in the Signal Path
3.3V
• USB Switching
VDD
INT
USB CONNECTOR
ALM
LOGIC
CONTROL
VBUS
D-
LP
OE
D-
COM-
USB
OVP
D+
GND
D+
COM+
ISL54227
µP
HIGH-SPEED
TRANSCEIVER
VOLTAGE SCALE (0.1V/DIV)
500Ω
GND
TIME SCALE (0.2ns/DIV)
July 2, 2010
FN7593.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54227
High-Speed USB 2.0 (480Mbps) DPST Switch with
Overvoltage Protection (OVP) and Dedicated
Charger Port Detection
ISL54227
Pin Configurations
ISL54227
(10 LD 3X3 TDFN)
TOP VIEW
ISL54227
(10 LD 1.8X1.4 µTQFN)
TOP VIEW
D6
ALM
7
PD
INT 1
OE
8
VDD
9
LP 2
5 COM-
LOGIC
OVP
INT 10
4MΩ 4MΩ
4
GND
3
COM+
10 VDD
4MΩ
D+ 3
2
LP
D+
4MΩ
8 ALM
COM+ 4
7 DOVP
GND 5
1
9 OE
LOGIC
6 COM-
NOTE:
1. Switches Shown for OE = “0”.
Pin Descriptions
Truth Table
INPUT
PIN
µTQFN TDFN NAME
DESCRIPTION
OUTPUT
SIGNAL AT
COM PINS
LP
USB Data Port
0V to 3.6V
0
COM+ USB Data Port
0V to 3.6V
D-,
OE D+
INT
ALM
STATE
0
OFF High
High
Normal
0
1
ON
High
High
Normal
0V to 3.6V
1
0
OFF High
High
Low Power
Overvoltage
Range
3.65V to 5.25V
-0.29V to -5V
0
1
OFF High
Low
OVP
COM Pins Tied
Together
0
0
OFF
Low
High
Charger Port
(CP)
Charger Mode Interrupt Output
COM Pins Tied
Together
1
0
OFF
Low
High
Charger Port
(Low Power)
Thermal Pad. Tie to Ground or
Float
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to
3.6V Supply.
1
2
LP
Low Power Input
2
3
D+
3
4
4
5
GND
5
6
COM- USB Data Port
6
7
D-
7
8
ALM
8
9
OE
Switch Enable
9
10
VDD
Power Supply
10
1
INT
-
PD
PD
Ground Connection
USB Data Port
OTV ALARM Interrupt Output
TABLE 1. OVP TRIP POINT VOLTAGE
SYSTEM VOLTAGE CONDITIONS
TRIP POINT
CODEC SUPPLY
SWITCH SUPPLY (VDD)
COMs SHORTED TO
PROTECTED
MIN
MAX
2.7V to 3.3V
2.7V to 5.25V
VBUS
Yes
3.62V
3.95V
2.7V to 3.3V
2.7V to 5.25V
-5V
Yes
-0.6V
-0.29V
2
FN7593.0
July 2, 2010
ISL54227
Ordering Information
PART NUMBER
(Note 5)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
U1
-40 to +85
10 Ld 1.8 x 1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54227IRUZ-T7A (Notes 2, 4) U1
-40 to +85
10 Ld 1.8 x 1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54227IRTZ (Note 3)
4227
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54227IRTZ-T (Notes 2, 3)
4227
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54227IRTZEVAL1Z
Evaluation Board
ISL54227IRUZ-T (Notes 2, 4)
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54227. For more information on MSL please
see techbrief TB363.
3
FN7593.0
July 2, 2010
ISL54227
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
VDD to COMx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V
COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.6V
Input Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V
OE, LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
Continuous Current (COM-/D-, COM+/D+) . . . . . . . ±40mA
Peak Current (COM-/D-, COM+/D+)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114-F). . . . >2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . >150V
Charged Device Model (Tested per JESD22-C101-D) . >2kV
Latch-up (Tested per JEDEC; Class II Level A) . . . . at +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld µTQFN Package (Note 6, 9) .
210
165
10 Ld TDFN Package (Notes 7, 8). .
58
22
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range. . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Normal Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . .
VDD Supply Voltage Range . . . . . . . . . . . .
Logic Control Input Voltage . . . . . . . . . . .
Analog Signal Range, VDD = 2.7V to 5.25V
.
.
.
.
-40°C to +85°C
. 2.7V to 5.25V
. . . 0V to 5.25V
. . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications - 2.7V to 5.25V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND, VOEH = 1.4V,
VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
(High-Speed)
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
VCOM+ or VCOM- = 0V to 400mV
(see Figure 2, Note 15)
rON Matching Between
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
Channels, ΔrON (High-Speed) VCOM+ or VCOM- = Voltage at max rON,
(Notes 14, 15)
25
-
3.5
5
Ω
Full
-
-
7
Ω
25
-
0.2
0.45
Ω
Full
-
-
0.55
Ω
25
-
0.26
1
Ω
Full
-
-
1.2
Ω
rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 2.7V, OE = 1.4V, IDx = 17mA,
VCOM+ or VCOM- = 0V to 400mV,
(Notes 13, 15)
ON-Resistance, rON
VDD = 3.3V, OE = 1.4V, ICOMx = 17mA,
VCOM+ or VCOM- = 3.3V
(see Figure 2, Note 15)
+25
-
6.8
17
Ω
Full
-
-
22
Ω
VDD = 5.25V, OE = 0V, VDx = 0.3V, 3.3V,
VCOMX = 3.3V, 0.3V
25
-20
1
20
nA
Full
-
30
-
nA
25
-9
-
9
µA
Full
-12
-
12
µA
25
-
-
11
µA
Power OFF Logic Current, IOE VDD = 0V, OE = 5.25V
25
-
-
22
µA
Power OFF D+/D- Current,
ID+, ID-
25
-
-
1
µA
OFF Leakage Current,
IDx(OFF)
ON Leakage Current, IDx(ON) VDD = 5.25V, OE = 5.25V, VDx = 0.3V,
3.3V, VCOMX = 0.3V, 3.3V
Power OFF Leakage Current,
ICOM+, ICOM-
VDD = 0V, VCOM+ = 5.25V,
VCOM- = 5.25V, OE = 0V
VDD = 0V, OE = VDD, VD+ = VD- = 5.25V
4
FN7593.0
July 2, 2010
ISL54227
Electrical Specifications - 2.7V to 5.25V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND, VOEH = 1.4V,
VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
Overvoltage Protection Detection
Positive Fault-Protection Trip
Threshold, VPFP
VDD = 2.7V to 5.25V, OE = VDD
(See Table 1 on page 2)
25
3.62
3.8
3.95
V
Negative Fault-Protection Trip VDD = 2.7V to 5.25V, OE = VDD
Threshold, VNFP
(See Table 1 on page 2)
25
-0.6
-0.45
-0.29
V
Negative OVP Response: VDD = 2.7V,
SEL = 0V or VDD, OE/ALM = VDD,
VDx = 0V to -5V, RL = 1.5kΩ
25
-
102
ns
Positive OVP Response: VDD = 2.7V,
SEL = 0V or VDD, OE/ALM = VDD,
VDx = 0V to 5.25V, RL = 1.5kΩ
25
-
2
µs
VDD = 2.7V, OE = VDD, VDx = 0V to 5.25V
or 0V to -5V, RL = 1.5kΩ
25
-
45
µs
OFF Persistance Time
Fault Protection Response
Time
ON Persistance Time
Fault Protection Recovery
Time
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, VINPUT = 3V, RL = 50Ω,
CL = 50pF (see Figure 1)
25
-
160
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, VINPUT = 3V, RL = 50Ω,
CL = 50pF (see Figure 1)
25
-
60
-
ns
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.3V, OE = 3.3V, RL = 45Ω,
CL = 10pF, tR = tF = 500ps at 480Mbps,
(Duty Cycle = 50%) (see Figure 5)
25
-
50
-
ps
Rise/Fall Degradation
(Propagation Delay), tPD
VDD = 3.3V, OE = 3.3V, RL = 45Ω,
CL = 10pF, (see Figure 5)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz
(see Figure 4)
25
-
-39
-
dB
OFF-Isolation
VDD = 3.3V, OE = 0V, RL = 50Ω,
f = 240MHz
25
-
-23
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.86VDC offset,
RL = 50Ω
25
-
790
-
MHz
OFF Capacitance, COFF
f = 1MHz, VDD = 3.3V, LP = 0V, OE = 0V
(see Figure 3)
25
-
2.5
-
pF
COM ON Capacitance, C(ON)
f = 1MHz, VDD = 3.3V, LP = 0V,
OE = 3.3V, (see Figure 3)
25
-
4
-
pF
COM ON Capacitance, C(ON)
f = 240MHz, VDD = 3.3V, LP = 0V,
OE = 3.3V
25
-
2
-
pF
Full
2.7
5.25
V
25
-
45
56
µA
Full
-
-
59
µA
25
-
23
30
µA
Full
-
-
34
µA
25
-
5
6
µA
Full
-
-
10
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
VDD = 5.25V, OE = 5.25V, LP = GND
Positive Supply Current, IDD
VDD = 3.6V, OE = 3.6V, LP = GND
Positive Supply Current, IDD
(Low Power State)
VDD = 3.6V, OE = 0V, LP = VDD
5
FN7593.0
July 2, 2010
ISL54227
Electrical Specifications - 2.7V to 5.25V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VLP = GND, VOEH = 1.4V,
VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
Positive Supply Current, IDD
VDD = 4.3V, OE = 2.6V, LP = GND
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
25
-
35
45
µA
Full
-
-
50
µA
25
-
25
32
µA
Full
-
-
38
µA
Input Voltage Low, VOEL, VLPL VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VOEH,
VLPH
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, VOEL, VLPL VDD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High, VOEH,
VLPH
Full
1.7
-
-
V
Input Voltage Low, VOEL, VLPL VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, VOEH,
VLPH
VDD = 4.3V to 5.25V
Full
2.0
-
-
V
Input Current, IOEL, ILPL
VDD = 5.25V, OE = 0V, LP = 0V
Full
-
-8.2
-
nA
Input Current, IOEH, ILPH
VDD = 5.25V, OE = 5.25V, LP = 5.25V,
4MΩ Pull-down
Full
-
1.4
-
µA
Positive Supply Current, IDD
VDD = 3.6V, OE = 1.4V, LP = GND
DIGITAL INPUT CHARACTERISTICS
VDD = 3.7V to 4.2
NOTES:
10. VLOGIC = Input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value.
15. Limits established by characterization and are not production tested.
6
FN7593.0
July 2, 2010
ISL54227
Test Circuits and Waveforms
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
VDD
50%
0V
VINPUT
tOFF
SWITCH
INPUT VINPUT
SWITCH
INPUT
VOUT
Dx
COMx
OE
VOUT
90%
SWITCH
OUTPUT
C
90%
VIN
CL
50pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VDD
C
rON = V1/17mA
COMx
VHSDX
OE
V1
17mA
VDD
Dx
GND
Repeat test for all switches.
FIGURE 2. rON TEST CIRCUIT
VDD
VDD
C
C
COMx
SIGNAL
GENERATOR
COM+
50Ω
D+
OE
IMPEDANCE
ANALYZER
OE
0V OR
VDD
Dx
VIN
GND
COM-
D-
ANALYZER
NC
GND
RL
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. CAPACITANCE TEST CIRCUIT
7
FIGURE 4. CROSSTALK TEST CIRCUIT
FN7593.0
July 2, 2010
ISL54227
Test Circuits and Waveforms (Continued)
VDD
C
tri
90%
10%
DIN+
50%
VDD
tskew_i
DIN-
90%
OE
15.8Ω
COM-
DIN+
50%
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
D-
45Ω
CL
COM+
OUT-
D+
45Ω
CL
143Ω
90%
10%
OUT+
50%
GND
tskew_o
OUT-
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
50%
90%
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
10%
tf0
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
FIGURE 5. SKEW TEST
Application Block Diagram
3.3V
500Ω
VDD
ALM
INT
3.6V
USB CONNECTOR
VBUS
>1MΩ
LOGIC
CONTROL
4MΩ
D-
COM-
D+
OVP
DET
COM+
µCONTROLLER
LP
OE
4MΩ
D-
D+
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
GND
ISL54227
8
GND
PORTABLE MEDIA DEVICE
FN7593.0
July 2, 2010
ISL54227
Detailed Description
The ISL54227 device is a dual single pole/single throw
(SPST) analog switch configured as a DPST that operates
from a single DC power supply in the range of 2.7V to
5.25V.
It was designed for switching a USB high-speed or
full-speed source in portable battery powered products.
It is offered in small µTQFN and TDFN packages for use
in MP3 players, cameras, PDAs, cellphones, and other
personal media players.
The part consists of two 3.5Ω high-speed SPST switches.
These switches have high bandwidth and low capacitance
to pass USB high-speed (480Mbps) differential data
signals with minimal edge and phase distortion. They can
also swing from 0V to 3.6V to pass USB full speed
(12Mbps) differential data signals with minimal
distortion.
The device has a single logic control pin (OE) to open and
close the two SPST switches. The part has an LP control
pin to put the part in a low power state.
The part contains special over voltage protection (OVP)
circuitry on the COM+ and COM- pins. This circuitry acts
to open the SPST switches when the part senses a
voltage on the COM pins that is >3.8V (typ) or < -0.45V
(typ). It isolates voltages up to 5.25V and down to -5V
from getting through to the other side of the switches
(D-, D+) to protect the USB down-stream transceiver
connected at the D+ and D- pins. It has an alarm (ALM)
interrupt output to indicate when the device has detected
and entered the OTV state. This output can be monitored
by a µController to indicate a fault condition to the
system.
The part has charger port interrupt detection circuitry
(CP) on the COM pins that outputs a Low on the INT pin
to inform the µController or power management circuitry
when entering a dedicated charging port mode of
operation. The charger mode operation is initiated by
driving the OE pin Low and externally connecting the
COM pins together which pulls the COM lines High,
triggering the INT pin to go Low and the SPST switches
to open.
The ISL54227 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that need to switch a high-speed or full-speed
transceiver source. See this functionality in the
“Application Block Diagram” on page 8.
A detailed description of the SPST switches is provided in
the following section.
High-Speed (Dx) SPST Switches
The Dx switches are bi-directional switches that can pass
USB high-speed and USB full-speed signals when VDD is
in the range of 2.7V to 5.25V.
When powered with a 2.7V supply, these switches have a
nominal rON of 3.5Ω over the signal range of 0V to
400mV with a rON flatness of 0.26Ω. The rON matching
9
between the switches over this signal range is only 0.2Ω,
ensuring minimal impact by the switches to USB high
speed signal transitions. As the signal level increases, the
rON switch resistance increases. At signal level of 3.3V,
the switch resistance is nominally 6.8Ω. See Figures 9,
10, 11, 12, 13, 14 in the “Typical Performance Curves”
beginning on page 11.
The Dx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals in the
range of 0V to 400mV. They have low capacitance and
high bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0
high speed signal quality specifications. See Figure 15 in
the “Typical Performance Curves” on page 13 for USB
High-speed Eye Pattern taken with switch in the signal
path.
The Dx switches can also pass USB full-speed signals
(12Mbps) in the range of 0V to 3.6V with minimal
distortion and meet all the USB requirements for USB
2.0 full-speed signaling. See Figure 16 in the “Typical
Performance Curves” on page 14 for USB Full-speed
Eye Pattern taken with switch in the signal path.
The switches are active (turned ON) whenever the OE
voltage is logic “1”(High) and the LP voltage is logic “0”
(Low) and OFF when the OE voltage is logic “0” (Low)
and the LP voltage is logic “0” (Low) or logic “1” (High).
OVERVOLTAGE PROTECTION (OVP)
The maximum normal operating signal range for the Dx
switches is from 0V to 3.6V. For normal operation the
signal voltage should not be allow to exceed these
voltage levels or go below ground by more than -0.3V.
However, in the event that a positive voltage >3.8V (typ)
to 5.25V, such as the USB 5V VBUS voltage, gets shorted
to one or both of the COM+ and COM- pins or a negative
voltage <-0.45V (typ) to -5V gets shorted to one or both
of the COM pins, the ISL54227 has OVP circuitry to
detect the over voltage condition and open the SPST
switches to prevent damage to the USB down-stream
transceiver connected at the signal pins (D-, D+).
The OVP and power-off protection circuitry allows the
COM pins (COM-, COM+) to be driven up to 5.25V while
the VDD supply voltage is in the range of 0V to 5.25V. In
this condition, the part draws <100µA of ICOMx and IDD
current and causes no stress to the IC. In addition the
SPST switches are OFF and the fault voltage is isolated
from the other side of the switch.
The part has an alarm (ALM) interrupt output to indicate
when the device has detected and entered the OTV state.
This output can be monitored by a µController to indicate
a fault condition to the system.
External VDD Series Resistor to Limit IDD Current
during Negative OVP Condition
A 100Ω to 1kΩ resistor in series with the VDD pin (see
Figure 6) is required to limit the IDD current draw from
the system power supply rail during a negative OVP fault
event.
FN7593.0
July 2, 2010
ISL54227
The series resistor also provides improved ESD and
latch-up immunity. During an overvoltage transient event
(such as occurs during system level IEC 61000 ESD
testing), substrate currents can be generated in the IC
that can trigger parasitic SCR structures to turn ON,
creating a low impedance path from the VDD power
supply to ground. This will result in a significant amount
of current flow in the IC, which can potentially create a
latch-up state or permanently damage the IC. The
external VDD resistor limits the current during this
overstress situation and has been found to prevent latchup or destructive damage for many overvoltage transient
events.
Under normal operation, the low microamp IDD current
of the IC produces an insignificant voltage drop across
the series resistor resulting in no impact to switch
operation or performance.
VSUPPLY
C
PROTECTION
RESISTOR
100Ω TO 1kΩ
VDD
COM+
-5V
FAULT
VOLTAGE
OVP
COMOE
IDD
D-
LOW
TO
INDICATE
OVP
ALM
LOGIC
GND
LP
D+
INT
CHARGER PORT DETECTION
POWER
MANAGEMENT
BATTERY CHARGER
CIRCUITRY
VSUPPLY
BATTERY
CHARGER
200Ω
“LOW” TO
INDICATE
CHARGER
CONNECTED
C
VBUS
USB CONNECTOR
With a negative -5V fault voltage at both com pins, the
graph in Figure 7 shows the IDD current draw for
different external resistor values for supply voltages of
2.7V, 3.6V, and 5.25V. Note: With a 500Ω resistor the
current draw is limited to around 5mA. When the
negative fault voltage is removed the IDD current will
return to it’s normal operation current of 25µA to 45µA.
D+ COM+ VDD
CHG DET
D-
COM-
GND
D+
D-
USB
TRANCEIVER
ALM
LOGIC
OE LP GND
INT
OE = “0”
OR
TRI-STATE
µP
FIGURE 8. CHARGER PORT DETECTION
The ISL54227 has special charger port detection circuitry
that monitors the voltage at the com pins to detect when
a battery charger has been connected into the USB port
(see Figure 8).
When the battery charger is connected into the USB
connector, it shorts the COM+ and COM- pins together.
The shorting of the pins is sensed by the ISL54227 IC
and it pulls the COM+ and COM- lines high and as long as
the OE = “0” or is tri-stated by the µP, it will drive its INT
logic output “Low” to tell the power management
circuitry that a battery charger is connected at the port
and not a USB host transceiver. The power management
circuitry will then use the USB connector VBUS line to
charge the battery.
ISL54227 Operation
The following will discuss using the ISL54227 shown in
the “Application Block Diagram” on page 8.
FIGURE 6. VDD SERIES RESISTOR TO LIMIT IDD
CURRENT DURING NEGATIVE OVP AND FOR
ENHANCED ESD AND LATCH-UP IMMUNITY
25
VCOM+ = VCOM- = -5V
IDD (mA)
20
5.25V
5
0
100
3.6V
For lowest power consumption you should use the lowest
VDD supply.
In a typical application, VDD will be in the range of
2.8V to 4.3V and will be connected to the battery or
LDO of the portable media device.
2.7V
200
The power supply connected at the VDD pin provides the
DC bias voltage required by the ISL54227 part for proper
operation. The ISL54227 can be operated with a VDD
voltage in the range of 2.7V to 5.25V.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any
power supply noise from entering the part. The capacitor
should be located as close to the VDD pin as possible.
15
10
POWER
300
400
500 600 700
RESISTOR (Ω)
800
FIGURE 7. NEGATIVE OVP IDD CURRRENT vs
RESISTOR VALUE vs VSUPPLY
10
900 1k
LOGIC CONTROL
The state of the ISL54227 device is determined by the
voltage at the OE pin, LP pin, and the signal voltage at
the COM pins. Refer to “Truth Table” on page 2.
FN7593.0
July 2, 2010
ISL54227
The OE and LP pins are internally pulled low through a
4MΩ resistor to ground and can be tri-stated or left
floating.
draws only 10µA (max) of current across the operating
temperature range.
The ISL54227 is designed to minimize IDD current
consumption when the logic control voltage is lower than
the VDD supply voltage. With VDD = 3.6V and the OE
logic pin is at 1.4V the part typically draws only 25µA.
With VDD = 4.3V and the OE logic pin is at 2.6V the part
typically draws only 35µA. Driving the logic pin to the
VDD supply rail minimizes power consumption.
With a signal level in the range of 0V to 3.6V and with
the LP pin = Logic “0” the switches will be ON when the
OE pin = Logic “1” and will be OFF (high impedance)
when the OE pin = Logic “0”.
The OE and LP pin can be driven with a voltage higher
than the VDD supply voltage. It can be driven up to
5.25V with a VDD supply in the range of 2.7V to 5.25V.
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
VDD SUPPLY
RANGE
LOGIC = “0” (LOW)
LOGIC = “1”
(HIGH)
OE
LP
OE
LP
2.7V to 3.6V
≤ 0.5V
or
floating
≤ 0.5V
or
floating
≥1.4V
≥1.4V
3.7V to 4.2V
≤ 0.7V
or
floating
≤ 0.7V
or
floating
≥1.7V
≥1.7V
4.3V to 5.25V
≤ 0.8V
or
floating
≤ 0.8V
or
floating
≥2.0V
≥2.0V
Low Power Mode
If the OE pin = Logic “0”, and the LP pin = Logic “1” the
switches will turn OFF (high impedance) and the part
will be put in a low power mode. In this mode the part
Typical Performance Curves
Normal Operation Mode
USB 2.0 VBUS Short Requirments
The USB specification in section 7.1.1 states a USB
device must be able to withstand a VBUS short (4.4V to
5.25V) or a -1V short to the D+ or D- signal lines when
the device is either powered off or powered on for at
least 24 hours.
The ISL54227 part has special power-off protection and
OVP detection circuitry to meet these short circuit
requirements. This circuitry allows the ISL54227 to
provide protection to the USB down-stream transceiver
connected at its signal pins (D-, D+) to meet the USB
specification short circuit requirements.
The power-off protection and OVP circuitry allows the
COM pins (COM-, COM+) to be driven up to 5.25V or
down to -5V while the VDD supply voltage is in the range
of 0V to 5.25V. In these overvoltage conditions with a
500Ω external VDD resistor the part draws <55µA of
current into the COM pins and causes no stress/damage
to the IC. In addition all switches are OFF and the
shorted VBUS voltage will be isolated from getting
through to the other side of the switch channels, thereby
protecting the USB transceiver.
TA = +25°C, Unless Otherwise Specified
16
3.4
ICOM = 17mA
12
3.2
10
3.0V
rON (Ω)
rON (Ω)
3.3
3.3V
3.1
0.1
0.2
2
0.3
0.4
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
11
3.0V
4
5.25V
0
2.7V
8
6
3.6V
4.3V
3.0
2.9
ICOM = 17mA
14
2.7V
0
5.25V
0
0.6
1.2
1.8
2.4
3.3V
3.0
3.6
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FN7593.0
July 2, 2010
ISL54227
Typical Performance Curves
4.5
TA = +25°C, Unless Otherwise Specified (Continued)
18
V+ = 2.7V
ICOM = 17mA
V+ = 2.7V
16 ICOM = 17mA
4.0
14
+85°C
12
rON (Ω)
rON (Ω)
3.5
+25°C
3.0
2.5
10
+85°C
8
+25°C
6
-40°C
4
2.0
-40°C
2
1.5
0
0.1
0.2
VCOM (V)
0.3
0
0.4
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
4.0
9
V+ = 3.3V
ICOM = 17mA
8
+85°C
3.5
7
6
3.0
rON (Ω)
rON (Ω)
0
+25°C
+85°C
4
+25°C
2.5
3
-40°C
V+ = 3.3V
ICOM = 17mA
2.0
5
0
0.1
-40°C
2
0.2
VCOM (V)
0.3
0.4
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
12
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.6
VCOM (V)
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN7593.0
July 2, 2010
ISL54227
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 15. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
13
FN7593.0
July 2, 2010
ISL54227
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 16. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
0.0
5.0
4.5
4.0
VDD = 3.3V
IOL CURRENT (mA)
IOH CURRENT (mA)
-0.5
-1.0
-1.5
VDD = 5.25V
-2.0
VDD = 5.25V
3.5
3.0
2.5
2.0
1.5
VDD = 3.3V
1.0
0.5
-2.5
0
1
2
3
4
5
VOH VOLTAGE (V)
FIGURE 17. IOH vs VOH vs VDD for INT and ALM
14
0.0
0
1
2
3
4
5
VOL VOLTAGE (V)
FIGURE 18. IOL vs VOL vs VDD for INT and ALM
FN7593.0
July 2, 2010
ISL54227
TA = +25°C, Unless Otherwise Specified (Continued)
1
-10
0
-20
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
-30
-40
-50
-60
-70
-80
-90
-100
1M
10M
100M
1G
-110
0.001
0.01
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE
10M
100M
500M
Die Characteristics
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL
(POWERED UP):
-30
NORMALIZED GAIN (dB)
1M
FIGURE 20. OFF-ISOLATION
-10
-20
0.1
FREQUENCY (Hz)
GND
-40
TRANSISTOR COUNT:
-50
1297
-60
PROCESS:
-70
Submicron CMOS
-80
-90
-100
-110
0.001
0.01
0.1
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 21. CROSSTALK
15
FN7593.0
July 2, 2010
ISL54227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
7/2/10
FN7593.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL54227
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN7593.0
July 2, 2010
ISL54227
Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
1.80
B
6
PIN #1 ID
A
1
1
1.40
3
10
0.50
6 PIN 1
INDEX AREA
9 X 0.40
2
10X 0.20 4
0.10 M C A B
0.05 M C
0.70
8
5
0.10
7
2X
4X 0.30
6
6X 0.40
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX. 0.55
C
SEATING PLANE
0.08 C
(9 X 0.60)
1
(10X 0.20)
(4X 0.30)
3
10
8
(0.70)
SIDE VIEW
(0.70)
C
5
6
0 .1 27 REF
7
(6X 0.40)
PACKAGE OUTLINE
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
JEDEC reference MO-255.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
17
FN7593.0
July 2, 2010
ISL54227
Package Outline Drawing
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
3.00
A
2.0 REF
6
PIN 1
INDEX AREA
B
8X 0.50 BSC
5
1
6
PIN 1
INDEX AREA
10X 0 . 30
3.00
1.50
0.15
(4X)
10
0.10 M C A B
0.05 M C
5
4 10 X 0.25
TOP VIEW
2.30
( 2.30 )
BOTTOM VIEW
0 .80 MAX
SEE DETAIL "X"
0.10 C
C
(2.90)
SEATING PLANE
0.08 C
(1.50)
SIDE VIEW
(10 X 0.50)
0 . 2 REF
5
C
( 8X 0 .50 )
( 10X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
18
Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).
FN7593.0
July 2, 2010
Similar pages