LINER LT3582-5 I2c programmable boost and single inductor inverting dc/dc converters with otp Datasheet

LT3582/LT3582-5/LT3582-12
I2C Programmable Boost
and Single Inductor Inverting
DC/DC Converters with OTP
DESCRIPTION
FEATURES
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Output Voltages:
3.2V to 12.775V and –1.2V to –13.95V (LT3582)
5V and –5V (LT3582-5)
12V and –12V (LT3582-12)
Digitally Re-Programmable (LT3582) Via I2C for:
Output Voltages
Power Sequencing
Output Voltage Ramp Rates
Power-up Defaults Settable with Non-volatile OTP
(LT3582)
I2C Compatible Interface (Standard Mode*)
All Power Switches Integrated
350mA Current Limit (Boost)
600mA Current Limit (Inverting)
All Feedback Resistors Integrated
Input Voltage Range: 2.55V to 5.5V
Low Quiescent Current
325μA in Active Mode
0.01μA in Shutdown Mode
Integrated Output Disconnect
Tiny 16-pin 3mm × 3mm QFN Package
The LT®3582/LT3582-5/LT3582-12 are dual DC/DC converters featuring positive and negative outputs and integrated
feedback resistors. The LT3582, with its built in One Time
Programming (OTP), has configurable output settings via
the I2C interface, including output voltage settings, power
up sequencing, power down discharge, and output voltage
ramp rates. LT3582 settings can be changed adaptively in
the final product, or set during manufacturing and made
permanent using the built in non-volatile OTP memory.
The positive output voltage can be set between 3.2V and
12.775V in 25mV steps. The negative output voltage can
be set between –1.2V and –13.95V in –50mV steps. The
LT3582-5 and LT3582-12 are pre-configured at the factory
for ±5V and ±12V outputs respectively.
The LT3582 series includes two monolithic converters,
one Boost and one Inverting. The Boost converter has an
integrated power switch and output disconnect switch.
The Inverting converter uses a single inductor topology
and includes an integrated power switch. Both Boost and
Inverting converters use a novel** control scheme resulting in low output voltage ripple while allowing for high
conversion efficiency over a wide load current range. The
LT3582 series is available in a 16-pin 3mm x 3mm QFN.
APPLICATIONS
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AMOLED Power
CCD Power
General Purpose DC/DC Conversion
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
* Input thresholds are reduced to allow communication with low voltage digital ICs.
(See Electrical Characteristics).
**Patent Pending
TYPICAL APPLICATION
±12V Supplies from a Single 5V Input
95
SHDN
SWN
6.8μH
Efficiency and Power Loss
INPUT
4.5V TO 5.5V
VIN
SWN
SWP
EFFICIENCY (%)
1μF
CAPP
VOUTN
I2C
INTERFACE
SDA
OPTIONAL ON
LT3582-5/LT3582-12
)
VPOS
12V
80mA
VOUTP
SCL
CA
(
CAPP
VPP
250
75
200
65
150
55
100
45
50
4.7μF
RAMPP RAMPN
35
0.1
10nF
POWER LOSS (mW)
4.7μF
LT3582
VNEG
–12V
85mA
300
85
6.8μH
GND
10μF
350
VOUTP
VOUTN
10nF
1
10
LOAD CURRENT (mA)
0
100
3582512 TA01b
3582512 TA01a
3582512f
1
LT3582/LT3582-5/LT3582-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
GND
VPP
SCL
SDA
TOP VIEW
VIN Voltage ..................................................................6V
SWP Voltage .............................................................15V
SWN Voltage ........................................................–16.5V
CAPP Voltage ............................................................15V
CAPP-VOUTP Voltage .................................... –0.8V to 8V
ICAPP-VOUTP ........................................................±300mA
VOUTP Voltage ...........................................................15V
VOUTN Voltage ......................................................–16.5V
RAMPP Voltage...........................................................3V
RAMPN Voltage ..........................................................3V
SHDN Voltage .................................................–0.5 to 6V
VPP Voltage ...................................................–0.2 to 16V
SDA, CA, SCL Voltage .....................................–0.5 to 6V
Operating Junction Temperature Range (Notes 3, 5)
LT3582E ............................................. –40°C to 125°C
Storage Temperature Range .............. –65°C to 150°C
16 15 14 13
CA 1
12 SWP
VOUTN 2
11 CAPP
17
GND
SWN 3
10 CAPP
SWN 4
6
7
8
VIN
RAMPN
RAMPP
SHDN
9
5
VOUTP
UD PACKAGE
16-PIN (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W
EXPOSED PAD (PIN #17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3582EUD#PBF
LT3582EUD#TRPBF
LDDB
16-Pin (3mm × 3mm) Plastic QFN
–40°C to 125°C
LT3582EUD-5#PBF
LT3582EUD-5#TRPBF
LDVG
16-Pin (3mm × 3mm) Plastic QFN
–40°C to 125°C
LT3582EUD-12#PBF
LT3582EUD-12#TRPBF
LDVH
16-Pin (3mm × 3mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
VIN_MIN
Minimum Operating Voltage
CONDITIONS
l
2.4
2.475
2.55
V
VIN_MAX
Maximum Operating Voltage
l
5.5
IVIN
VIN Quiescent Current
Ramp Current Configured to 1μA,
SWOFF Bit Active
325
450
μA
IVIN_SHDN
VIN Quiescent Current in Shutdown
VSHDN = 0
0.01
0.5
μA
ICAPP_SHDN
CAPP Quiescent Current in Shutdown VSHDN = 0, VCAPP = 5.0V, VOUTP = 0V
0
0.5
μA
TOFF_MINP
Minimum Switch Off Time
Boost Switch
100
ns
TOFF_MINN
Minimum Switch Off Time
Inverting Switch
125
ns
TON_MAX
Maximum Switch On Time
Inverting and Boost Switches
10
μs
ILIMIT_P
Boost Switch Current Limit
l
285
V
350
430
mA
3582512f
2
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
SYMBOL
PARAMETER
ILIMIT_N
Inverting Switch Current Limit
RON_P
Boost Switch On Resistance
CONDITIONS
l
MIN
TYP
MAX
UNITS
490
600
720
mA
ISWP = 200mA
500
mΩ
RON_N
Inverting Switch On Resistance
ISWN = –400mA
560
IOFF_P
Boost Switch Leakage Current into
SWP pin
VSWP = 5V
0.01
0.5
μA
IOFF_N
Inverting Switch Leakage Current out VIN = 5.0, VSWN = 0.0
of SWN pin
0.01
1
μA
RON_DIS
Output Disconnect Switch On
Resistance
1.4
ILIMIT_DIS
Output Disconnect Current Limit
124
155
186
mA
IVOUTP_PDS
VOUTP Power-Down Discharge
Current
VOUTP = 8V
2.4
4.8
8.8
mA
ICAPP_PDS
CAPP Power-Down Discharge
Current
CAPP = 8V
1.2
2.4
4.4
mA
IVOUTN_PDS
VOUTN Power-Down Discharge
Current
VOUTN = –8V
–1.4
–2.8
–4.2
mA
TSTARTUP
Configuration Startup Delay
VIN> VIN_MIN & SHDN > VSHDN_VIH to I2C
Enabled and Power-up Sequencing Start
64
128
μs
MIN
TYP
MAX
UNITS
4.95
11.88
5
12
5.05
12.1
V
V
VCAPP = 10V, RAMPP > 1.4V
l
l
mΩ
Ω
Programmable Output Characteristics6
SYMBOL
PARAMETER
CONDITIONS
V VOUTP
Positive Output Voltage
LT3582-5
LT3582-12
N_VOUTP
Positive VOUTP Resolution2
V VOUTP_LSB
VOUTP LSB2
l
l
9
Bits
25
mV
V VOUTP_FS
VOUTP
Full Scale Voltage2
Code = BFh, VPLUS = 1
l
12.56
12.775
12.94
V
V VOUTP_MIN
VOUTP Minimum Voltage2
Code = 00h, VPLUS = 0
l
3.152
3.20
3.248
V
V VOUTP_LR
VOUTP Line Regulation
Code = BFh, 2.575 < VIN < 5.5
V VOUTN
Negative Output Voltage
LT3582-5
LT3582-12
N_VOUTN
Negative VOUTN Resolution2
V VOUTN_LSB
VOUTN LSB2
–0.02
l
l
–5.075
–12.1
–5
–12
%/V
–4.925
–11.868
8
V
V
Bits
–50
mV
VOUTN
Full Scale Voltage2
Code = FFh
l
–14.2
–13.95
–13.7
V VOUTN_MIN
VOUTN
Minimum Voltage2
Code = 00h
l
–1.23
–1.205
–1.18
V VOUTN_LR
VOUTN Line Regulation
INL_VOUTP
VOUTP Integral Nonlinearity 2, 4
l
±0.6
LSB
DNL_VOUTP
VOUTP Differential Nonlinearity 2, 4
l
±0.6
LSB
INL_VOUTN
VOUTN
Integral Nonlinearity 2
l
±0.85
LSB
DNL_VOUTN
VOUTN
Differential Nonlinearity 2
±0.85
LSB
IRAMP00
RAMPP/RAMPN Pull Up Current
IRMP Code = 00
VRAMPP = 0.0V
VRAMPN = 0.0V
l
0.7
1.0
1.3
μA
IRAMP01
RAMPP/RAMPN Pull Up Current 2
IRMP Code = 01
VRAMPP = 0.0V
VRAMPN = 0.0V
l
1.4
2.0
2.6
μA
V VOUTN_FS
Code = FFh, 2.575 < VIN < 5.5
–0.01
l
V
V
%/V
3582512f
3
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Programmable Output Characteristics
SYMBOL
PARAMETER
CONDITIONS
IRAMP10
RAMPP/RAMPN Pull Up Current 2
IRMP Code = 10
VRAMPP = 0.0V
VRAMPN = 0.0V
IRAMP11
RAMPP/RAMPN Pull Up Current 2
IRMP Code = 11
VRAMPP = 0.0V
VRAMPN = 0.0V
V VPLUS
VOUTP Voltage Increase When VPLUS
Bit is Set from 0 to 12
MIN
TYP
MAX
l
2.8
4.0
5.2
μA
l
5.6
8.0
10.4
μA
25
UNITS
mV
Input/Output Pin Characteristics
SYMBOL
PARAMETER
VSHDN_VIH
SHDN Input Voltage High
CONDITIONS
l
MIN
VSHDN_VIL
SHDN Input Voltage Low
l
VHYST_SHDN
SHDN Input Hysteresis
I SHDN_BIAS
SHDN Pin Bias Current
VCA_VIH
CA Input Voltage High
l
VCA_VIL
CA Input Voltage Low
l
VSDA_VIH
SDA Input Voltage High
l
TYP
MAX
1.1
V
0.3
50
VSHDN = 1V
2.5
UNITS
4.5
V
mV
6.5
0.7 × VIN
μA
V
0.3 × VIN
1.25
V
V
VSDA_VIL
SDA Input Voltage Low
l
VSCL_VIH
SCL Input Voltage High
l
VSCL_VIL
SCL Input Voltage Low
l
VHYST
Input Hysteresis
SDA, SCL Pins
ILEAK_CA
CA Input Leakage Current
CA = 0V & 5.5V
l
±1
μA
ILEAK_SCL
SCL Input Leakage Current
SCL = 0V & 5.5V
l
±1
μA
ILEAK_SDA
SDA Input Leakage Current
SDA = 0V & 5.5V
l
±1
μA
CIN
Input Capacitance
SDA, SCL Pins
3mA into SDA Pin
VSDA_OL
SDA Output Low Voltage
VPP_RANGE
VPP Voltage Range for OTP Write2
VPPUVLO
Under-voltage Lockout for VPP Pin2
0.85
1.25
V
0.85
80
l
13
V
mV
3
l
V
pF
0.4
V
15
V
12.05
12.45
12.85
V
MIN
TYP
MAX
UNITS
100
kHz
I2C Timing Characteristics
SYMBOL
PARAMETER
CONDITIONS
fSCL
Serial Clock Frequency
l
4.7
μs
4.0
μs
tLOW
Serial Clock Low Period
l
tHIGH
Serial Clock High Period
l
tBUF
Bus Free Time Between Stop and Start
l
4.7
μs
tHD,STA
Start Condition Hold Time
l
4.0
μs
tSU,STA
Start Condition Setup Time
l
4.7
μs
tSU,STO
Stop Condition Setup Time
l
4.0
μs
tHD,DATXMIT
Data Hold Time Transmitting
l
300
ns
LT3582 Sending Data to Host
3582512f
4
LT3582/LT3582-5/LT3582-12
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
I2C Timing Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
tHD,DATRCV
Data Hold Time Receiving
LT3582 Receiving Data from Host
tSU,DAT
Data Setup Time
tF
SDA Fall Time
400pF load, VIN ≥ 2.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: LT3582 only.
Note 3: The LT3582E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlations with statistical process controls.
Note 4: These specifications apply to the VP trim bits in REG0 using
a 50mV LSB and do not include the additional VPLUS trim bit. See
Registers and OTP in the Applications Information section.
TYP
MAX
UNITS
l
0
ns
l
250
ns
l
250
ns
Note 5: This IC includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when over-temperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair
device reliability.
Note 6: Output voltage is measured under non-switching test conditions
approximating a moderate load current from the output.
3582512f
5
LT3582/LT3582-5/LT3582-12
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequencies (Figure 13)
TA = 25°C unless otherwise noted.
Load Regulation (Figure 13)
Output Voltage (Figure 13)
1.00
10000
0.45
0.75
0.30
0.50
ΔVOUT/VOUT (%)
1000
VOUTN
100
ΔVOUT/VOUT (%)
FREQUENCY (kHz)
VOUTP
0.25
VOUTP
0
–0.25
VOUTN
0.15
VOUTN
0
VOUTP
–0.15
–0.50
–0.30
–0.75
10
–1.00
20
40
60
80
LOAD CURRENT (mA)
0
100
20
40
60
80
LOAD CURRENT (mA)
3582512 G01
370
0.6
310
290
270
2.5
125
Switch Current Limit
700
VOUTN
0.5
VOUTP
0.4
0.3
0.2
3
3.5
4
4.5
5
SWN
600
500
400
SWP
300
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
3582512 G04
PMOS CURRENT LIMIT (mA)
VP CODE
SET TO 12V
VP CODE
SET TO 5V
0
VN CODE
SET TO –5V
–20
VN CODE
SET TO –12V
–40
–60
CURRENT OUT
OF VOUTN PIN
–80
0
2.5
5
7.5
10
|VOUT| (V)
12.5
15
3582512 G07
–25
0
25
50
75
TEMPERATURE (°C)
100
Output Disconnect PMOS
On-Resistance
200
2.5
180
2
160
140
120
100
–50
125
3582512 G06
ON-RESISTANCE (Ω)
CURRENT INTO
VOUTP PIN
20
5.5
Output Disconnect PMOS Current
Limit During Normal Operation
80
40
5
3582512 G05
VOUTP and VOUTN Pin Current
During Normal Operation
60
200
–50
0
5.5
VIN (V)
PIN CURRENT (μA)
100
0.1
250
–100
0
25
50
75
TEMPERATURE (°C)
3582512 G03
Switch Resistance
O.7
SWITCH RESISTANCE (Ω)
QUIESCENT CURRENT (μA)
Quiescent Current – Not Switching
330
–25
3582512 G02
390
350
–0.45
–50
100
SWITCH CURRENT LIMIT (mA)
0
1.5
1
0.5
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3582512 G08
0
2
4
6
8
VCAPP (V)
10
12
3582512 G09
3582512f
6
LT3582/LT3582-5/LT3582-12
TYPICAL PERFORMANCE CHARACTERISTICS
Note: All waveforms on this page apply
to Figure 13.
Switching Waveform at 1mA
Load (Boost)
Switching Waveform at 100mA
Load (Boost)
Switching Waveform at 10mA
Load (Boost)
VSWP
5V/DIV
VSWP
5V/DIV
VSWP
5V/DIV
VVOUTP
10mV/DIV
AC COUPLED
VVOUTP
10mV/DIV
AC COUPLED
VVOUTP
10mV/DIV
AC COUPLED
IL2
0.2A/DIV
IL2
0.2A/DIV
IL2
0.2A/DIV
3582512 G10
5μs/DIV
2μs/DIV
Switching Waveform at 1mA
Load (Inverting)
VSWN
10V/DIV
VVOUTN
0.1V/DIV
AC COUPLED
VVOUTN
50mV/DIV
AC COUPLED
LOAD
CURRENT
–20mA/DIV
IL1
0.2A/DIV
IL1
0.2A/DIV
5μs/DIV
Load Transient, VOUTP, 30mA to
60mA to 30mA Steps
VOUTP
0.2V/DIV
AC COUPLED
IL1
0.2A/DIV
5μs/DIV
3582512 G13
3582512 G14
50μs/DIV
3582512 G15
Power-Down Discharge
Waveforms
(PUSEQ = 11, PDDIS = 1)
Power-Up Sequencing Waveforms
(PUSEQ = 11)
VRAMPN
1V/DIV
VRAMPP
1V/DIV
VRAMPN
1V/DIV
LOAD
CURRENT
20mA/DIV
3582512 G12
Load Transient, VOUTN, 30mA to
60mA to 30mA Steps
Switching Waveform at 10mA
Load (Inverting)
VSWN
10V/DIV
VVOUTN
20mV/DIV
AC COUPLED
200ns/DIV
3582512 G11
VRAMPP
1V/DIV
VVOUTP
5V/DIV
VVOUTP
5V/DIV
IL2
0.2A/DIV
VVOUTN
5V/DIV
50μs/DIV
3582512 G16
VVOUTN
5V/DIV
5ms/DIV
3582512 G17
5ms/DIV
3582512 G18
3582512f
7
LT3582/LT3582-5/LT3582-12
PIN FUNCTIONS
CA (Pin 1): I2C Address Select Pin. Tie this pin to VIN to set
the 7-bit address to 0110 001. Tie to GND for 1000 101.
VOUTN (Pin 2): Negative Output Voltage Pin. When the converter is operating, this pin is regulated to the programmed
negative output voltage. Place a ceramic capacitor from
this pin to GND.
SWN (Pins 3 & 4): Negative switching node for the Inverting converter. This is the drain of the internal PMOS
power switch. Connect one end of the Inverting inductor
to these pins. Keep the trace area on these pins as small
as possible.
VIN (Pin 5): Input supply pin and source of the PMOS
power switch. This pin must be bypassed locally with a
ceramic capacitor. The operating voltage range of this pin
is 2.55V to 5.5V.
RAMPN (Pin 6): Soft start ramp pin for the Inverting
converter. Place a capacitor from this pin to GND. A
programmable current of 1μA - 8μA (LT3582) or 1μA
(LT3582-5/LT3582-12) charges this pin during startup,
limiting the ramp rate of VOUTN. This pin is discharged to
GND during shutdown.
RAMPP (Pin 7): Soft start ramp pin for the Boost converter.
Place a capacitor from this pin to GND. A programmable
current of 1μA - 8μA (LT3582) or 1μA (LT3582-5/LT3582-12)
charges this pin during startup, limiting the ramp rate of
VOUTP . This pin is discharged to GND in shutdown.
SHDN (Pin 8): Shutdown Pin. Drive this pin to 1.1V or
higher to enable the part. Drive to 0.3V or lower to shut
down. Includes an integrated 222k pulldown resistor.
VOUTP (Pin 9): Output of the Boost converter output
disconnect circuit. A ceramic capacitor should be placed
from this node to GND. During shutdown, this pin is
disconnected from the Boost network which allows this
pin to discharge to GND, assuming a load is present to
discharge the capacitance.
CAPP (Pins 10 & 11): Connect the Boost output capacitor
from these pins to GND. During shutdown, the voltage on
these pins will remain close to the input voltage due to
the path through the Boost inductor and Schottky. During
normal operation, CAPP will be boosted slightly higher
than the programmed output voltage.
SWP (Pin 12): Positive switching node for the Boost
converter. This is the drain of the internal NMOS power
switch. Connect one end of the Boost inductor to this pin.
Keep the trace area on this pin as small as possible.
GND (Pin 13): Ground Pin. Tie to a local ground plane.
Proper PCB layout is required to achieve advertised
performance; see Applications Information section for
more information.
VPP (Pin 14): Programming Voltage Pin. Drive this pin
to 13-15V when programming the OTP memory. Float
otherwise. A bypass capacitor should be placed from
this node to GND if VPP is used for programming. If VPP
falls below 13V during OTP programming, an internal
FAULT bit, which can be read through the I2C interface,
can be set high.
SDA (Pin 15): I2C Bidirectional Data Pin. Tie to GND or
VIN if unused.
SCL (Pin 16): I2C Clock Pin. Tie to GND or VIN if
unused.
Exposed Pad (Pin 17): Ground Pin. Tie to a local ground
plane. Proper PCB layout is required to achieve advertised
performance; see Applications Information section for
more information.
3582512f
8
LT3582/LT3582-5/LT3582-12
BLOCK DIAGRAM
SWP
VIN
Q
S
Q
R
VARIABLE DELAY
VARIABLE DELAY
S
Q
R
Q
CAPP CAPP
VOUTP
DISCONNECT
CONTROL
–
+
SWN
–
+
SWN
IPEAK TOFF
CONTROL
–
IPEAK TOFF
CONTROL
+
VOUTN
VCN
FBN
OTP
+
+
–
2V
VCP
GND
–
–
+
+
–
OTP
+
+
FBP
0.80V
SHDN
CHIP ENABLE
222k
VIN
VPP
0.80V
SCL
OTP ADJUST
VIN
CAPP
VOUTP
SERIAL INTERFACE,
LOGIC AND OTP
SDA
RAMPN
OUTPUT SEQUENCING
BY OTP
2V
+
–
0.75V
+
–
FBN
CA
FBP
VOUTN
3582512 BD
50mV
OUTPUT SEQUENCING
OTP ADJUST
RAMPP
3582512f
9
LT3582/LT3582-5/LT3582-12
OPERATION
The LT3582 series are dual DC/DC converters, each containing both a Boost and an Inverting converter. Operation
can be best understood by referring to the Block Diagram.
The Boost and Inverting converters each use a novel control
technique, which simultaneously varies both peak inductor
current and switch off time. This results in high efficiency
over a large load range and low output voltage ripple. In
addition, this technique further minimizes output ripple
when the switching frequency is in the audio band.
Boost Converter: The Boost converter uses a grounded
source NMOS power transistor as the main switching element. The current in the NMOS is constantly monitored and
controlled, along with the off time of the switch to achieve
regulation of VOUTP . The VOUTP voltage is divided by the
internal programmable (LT3582 only) resistor divider to
create FBP. The voltage on FBP is compared to an internal
reference and amplified, creating an error signal on the
VCP node which commands the appropriate peak inductor
current and off time for the subsequent switching cycle.
Inverting Converter: The Inverting converter uses a power
PMOS transistor with the source connected to VIN. This
topology requires only one external inductor, instead of
the normally required two inductors plus flying capacitor.
Regulation is achieved in a similar manner as the Boost.
Output Power-up Sequencing: After an initial startup delay
(TSTARTUP = 64μS typical), the outputs VOUTP and VOUTN
rise (in magnitude) simultaneously with the LT3582-5/
LT3582-12 or in one of four selectable sequences with
the LT3582. Using the I2C interface, the LT3582 outputs
can be configured such that (1) they both rise simultaneously, (2) VOUTP rises to regulation before VOUTN rises, (3)
VOUTN rises to regulation before VOUTP rises, or (4) neither
output rises. The outputs of the LT3582-5 and LT3582-12
are pre-configured to rise simultaneously.
The ramp rates of the outputs are proportional to the ramp
rates of their respective RAMP pins. A capacitor is placed
between each RAMP pin and ground. The RAMP pins are
discharged during shutdown. Once enabled, configurable
(LT3582) or pre-configured (LT3582-5/LT3582-12) currents charge each RAMP pin in the desired sequence
causing the outputs to rise.
Output Power-Down Discharge: The power-down discharge feature is permanently enabled on the LT3582-5
and LT3582-12 and can be enabled or disabled through
I2C on the LT3582. Upon SHDN falling, and when powerdown discharge is enabled, internal transistors will activate to assist in discharging the outputs toward ground.
When power-down discharge is disabled, the chip powers
down immediately after SHDN falls and the outputs will
discharge on their own depending on their external load
capacitances and currents.
OTP Memory (LT3582 Only): The LT3582 includes 22 bits
of user programmable output settings and 1 programming
lockout bit. Parameters such as positive & negative output
voltages and power sequencing settings can be changed
in real time with the integrated I2C interface. Settings can
then be made permanent by programming to the on-chip
non-volatile OTP (One Time Programmable) memory.
3582512f
10
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
I2C Interface
recent byte of data was received. The transmitter always
releases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it pulls down the SDA line
so that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge by
leaving SDA high, then the master may abort the transmission by generating a STOP condition. When the master
is receiving data from the slave, the master pulls down
the SDA line during the clock pulse to indicate receipt of
the data. After the last byte has been received the master
leaves the SDA line HIGH (not acknowledge) and issues a
stop condition to terminate the transmission.
The LT3582 series contains an I2C compatible interface
with reduced input threshold voltages to allow for direct
communication with low voltage digital ICs (see Electrical Characteristics). I2C communication is disabled when
SHDN is low. After SHDN rises, I2C communication is
re-enabled after a delay of 64μs (typical). The chip is a
read-write slave device which allows the user to read the
current settings and, for the LT3582, write new ones. Most
settings can be made permanent via the One-Time-Programmable memory. The chip will always enable using the
data stored in OTP and the LT3582 can be reconfigured
after power-up.
Device Addressing
START and STOP Conditions
The LT3582 series supports two 7-bit chip addresses
depending on the logic state of the CA pin. The addresses
are 0110 001 (CA=1) and 1000 101 (CA=0). Also, there
are seven internal data byte locations as shown in Table
1. OTP0-OTP2 are the OTP memory bytes. REG0-REG2
are the corresponding volatile registers used for storing
alternate settings. Finally, the Command Register (CMDR)
is used for additional control of the chip.
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high, as shown in Figure 1. When the master
has finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
All data bytes can be read from their assigned register
addresses. Since they share the same register addresses,
reads of the OTP and REG data bytes are differentiated
by their corresponding RSEL (Register Select) bits in the
ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between transmitter and receiver to indicate that the most
SDA
A6 - A0
SCL
1-7
B7 - B0
8
9
1-7
B7 - B0
8
9
1-7
8
9
S
START
CONDITION
P
CHIP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
3582512 F01
Figure 1. Data Transfer over I2C Bus
3582512f
11
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CMDR register. All data written to register addresses 0-2
is stored in REGO-REG2. Regardless of the RSEL bits, OTP
bytes cannot be written directly. See the OTP Programming section for more information.
Data Transfer Protocol
The LT3582 series supports 8-bit data transfers in the
transaction formats shown in Figures 2 and 3 below.
Multiple data bytes can only be transferred by issuing
multiple transactions.
Figure 2 shows the required format for writing a byte of
data to the LT3582 series. Again, the chip address depends
on the CA pin logic state.
S
CHIP ADDR
W
A
REG ADDR
A
DATA
A
0110 001 OR
1000 101
0
0
00000b2:b0
0
b7:b0
0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
A byte of data is read from the LT3582 series using the
format shown in Figure 3. This transaction requires four
I2C bytes to read one byte of chip data and must be
repeated for each subsequent byte of data that is read.
CHIP ADDR
W
A
REG ADDR
A
0110 001 OR
1000 101
0
0
00000b2:b0
0
S
During shutdown the RSEL bits are reset low. As a result,
the initial configuration comes from the OTP data bytes.
After power-up, the configuration can be changed by writing new settings to the appropriate REG data byte(s) then
setting the corresponding RSEL bit(s).
Finally, data in the REG bytes can be permanently programmed to OTP by applying voltage to the VPP pin and
setting the WOTP bit in the Command Register. See the
OTP Programming section for more information.
LT3582-5/LT3582-12 Chip Configuration
The LT3582-5/LT3582-12 are shipped from the factory
with the OTP memory pre-programmed and LOCKed which
prohibits subsequent changes to the configuration. The
configuration can still be read through the I2C bus and
the RST & SWOFF bits of the CMDR register (described
later) are functional. The following sections describe the
various configurable features of the LT3582. The LT3582-5
and LT3582-12 are pre-configured as follows: VP and VN
are programmed for ±5V or ±12V respectively, LOCK = 1,
IRMP = 00, PDDIS = 1, PUSEQ = 11 and VPLUS may be 1
or 0. Since LOCK = 1, subsequent configuration changes
are prohibited. See Configuration Lockout (LOCK Bit) for
more information.
Registers and OTP
CHIP ADDR
R
A
DATA
A
0110 001 OR
1000 101
1
0
b7:b0
1
Figure 3: I2C Byte Read Transaction
Settings such as output voltages and sequencing are
digitally programmable. The chip uses settings from either
the REG or OTP bytes, depending on the states of the corresponding RSEL bits (0 for OTP and 1 for REG).
P
Figure 2: I2C Byte Write Transaction
S
LT3582 Chip Configuration
P
The registers and OTP bytes for the LT3582 series are
organized as shown in Table 1. The CMDR is reset to 00h
upon power up, during shutdown and during under-voltage and thermal lockouts. REG0-REG2 are never reset
and must always be loaded with valid data before use.
The LT3582’s OTP memory is shipped with all 0’s, and
as a result, the PUSEQ bits are configured to disable the
outputs. The PUSEQ bits must be reconfigured to enable
the outputs.
3582512f
12
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CMDR: The Command Register is used to control various
functions of the chip. During shutdown and power-up the
CMDR is initialized to 00h.
The RSEL (Register Select) bits are functional only for
the LT3582. The LT3582-5 and LT3582-12 function as if
the RSEL bits are always “0”. These bits perform three
functions:
• Each RSEL bit instructs the chip whether to use the
configuration data from the corresponding OTP byte
(RSELx=0) or the REG byte (RSELx=1). Changing an
RSELx bit immediately updates the chip configuration.
Table 1: LT3582 Series Register Map
REGISTER
ADDRESS
REGISTER
NAME
BIT
00h
REG0/
OTP0
7:0
VP
VOUTP Output Voltage (00h=3.2V,
BFh = 12.75V)
01h
REG1/
OTP1
7:0
VN
VOUTN Output Voltage (00h=1.2V,
FFh = 13.95V)
7
-
6
LOCK
Lockout Bit: See “OTP Programming Lockout” Section.
5
VPLUS
VOUTP Output Voltage Bit: Increase VOUTP by ~25mV
4:3
IRMP
RAMPP & RAMPN Pullup Current: IRAMP = (2) IRMP μA
02h
REG2/
OTP2
• Each RSEL bit determines if I2C reads return data from
the corresponding OTP byte (RSELx=0) or the REG byte
(RSELx=1).
• OTP programming only programs data to the bytes with
corresponding RSEL bits set high.
Setting the SWOFF bit immediately disables the Boost and
Inverting power switches and opens the output disconnect
PMOS switch. It is recommended to set this bit before
writing new configuration data. This can prevent unexpected chip behavior while modifying the configuration
and also forces a soft-start after SWOFF is cleared (see
Soft-Start and Power-up Sequencing). Writing “1” to the
RST bit resets the internal I2C logic and the CMDR register.
Reading bit 6 of the CMDR returns the FAULT bit indicating
if an OTP programming attempt may have failed. FAULT
is cleared during reset, power-up, or by writing a “1” to
the CF (Clear Fault) bit. Conditions that set the FAULT bit
are (1) OTP programming in which the VPP voltage is too
low or (2) attempted OTP programming when the LOCK
bit is set. OTP write attempts that set the FAULT bit due
to low VPP voltage should be considered failures and the
device should be discarded. Attempts to re-program the
OTP memory after the FAULT bit has been set are not
recommended. Finally, setting the WOTP bit starts the
OTP programming.
PDDIS Power-Down Discharge Enable.
PUSEQ Must be 11 if Set.
1:0
PUSEQ Power-Up Sequencing: 00 =
Outputs Disabled, 01 = VOUTN
Ramp 1st, 10 = VOUTP Ramp 1st,
11 = Both Ramp Together
7
WOTP Write OTP Memory
6
CF/
Clear Fault/OTP Programming
FAULT Fault
4
CMDR
Reserved, Write to 0
2
5
04h
BIT
DESCRIPTION
NAME
3
RST
Reset
SWOFF Switches-Off
-
Reserved, Write to 0
2
RSEL2 Register Select 2 (0=OTP2,
1=REG2)
1
RSEL1 Register Select 1 (0=OTP1,
1=REG1)
0
RSEL0 Register Select 0 (0=OTP0,
1=REG0)
OTP0/REG0 & OTP1/REG1: Data in addresses 00h &
01h is used to set the output voltages of the Boost and
Inverting converters respectively. See Setting the Output
Voltages for more information.
3582512f
13
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
OTP2/REG2: Data in address 02h configures the output
voltage sequencing, sets a fine voltage adjust for VOUTP ,
and determines if further OTP programming is permitted or
not. Proper uses of the bits in address 02h are discussed
in the following sections.
Setting the Output Voltages (VP , VPLUS and VN bits)
The LT3582 series contains two resistor dividers
which are programmable in the LT3582, to set the
output voltages. The positive output voltage VOUTP
is adjustable in 25mV steps by setting the VP bits in
REG0/OTP0 in addition to the VPLUS bit in REG2/OTP2.
VOUTP = 3.2V + (VP • 50mV) + (VPLUS • 25mV)
where:
VP = an integer value from 0 to 191
VPLUS = 0 or 1
The VOUTN voltage is adjustable in –50mV steps by setting
the VN bits in REG1/OTP1.
VOUTN = –1.2V – (VN • 50mV)
where:
VN = an integer value from 0 to 255
Dynamically Changing the Output Voltage (LT3582 Only):
After output regulation has been reached, it’s possible to
change the output voltages by writing new values to the
VN or VP bits. When reducing the magnitude of an output voltage, it will decay at a rate dependent on the load
current and capacitance. Configuring a large increase in
magnitude of an output voltage can cause a large increase
in switch current to charge the output capacitor. Before
reconfiguring the outputs, consider forcing a soft-start
by asserting the SWOFF bit before writing the new VP or
VN codes. Subsequently clearing SWOFF initiates the new
soft-start sequence.
Soft-Start/Output Voltage Ramping (IRMP bits)
The LT3582 series contains soft-start circuitry to control
the output voltage ramp rates, therefore limiting peak
switch currents during start-up. High switch currents are
inherent in switching regulators during startup since the
feedback loop is saturated due to VOUT being far from its
final value. The regulator tries to charge the output capacitor
as quickly as possible which results in large currents.
Capacitors must be connected from RAMPP & RAMPN
to ground for soft-start. During shutdown or when the
SWOFF bit is set, the RAMP capacitors are discharged
to ground. After SHDN rises or SWOFF is cleared, the
capacitors are charged by programmable (LT3582 only)
currents, thus creating linear voltage ramps. The VOUT
voltages ramp in proportion to their respective RAMP
voltages according to:
V I
VOUT _RAMP _RATE = OUT • RAMP Volts / Sec
0.8V CRAMP Proportionality Constant
RAMP pin ramp rate (V/Sec)
where:
IRAMP = RAMP pin charging current set by IRMP
bits (1μA, 2μA, 4μA or 8μA for LT3582,
1μA for LT3582-5/LT3582-12)
CRAMP = External RAMP pin capacitor (Farads)
VOUT = Output voltage during regulation
For example, selecting IRAMP = 1μA, CRAMP = 10nF and
VOUTP = 12V results in a power-up ramp rate of 1.5Volt/ms
(see Figure 6).
Ramp rates less than 1-10V/ms generally result in good
startup characteristics. The outputs should linearly follow
the RAMPx voltages with no distortions. Figure 7 shows
an excessive startup ramp rate of ~120V/ms in which several startup issues have occurred: A) the expected VOUTP
ramp up path is not followed B) inductor current ringing
occurs C) the VOUTP ramp rate is limited due to the output
3582512f
14
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
disconnect current limit being reached D) additional ringing occurs when the CAPP pin starts charging E) output
voltage overshoot occurs because the inductor currents
are maximized during the output ramp up.
In some cases it may be desirable to use only one RAMP
pin capacitor. In cases where PUSEQ = 11 (see Power-Up
Sequencing section) the RAMPP & RAMPN pins can be
connected together and to a single capacitor. In this case
the capacitor will charge with twice the current configured
by the IRMP bits.
Ramping VOUTP from Ground: The LT3582 series has
the unique ability to generate a smooth VOUTP voltage
ramp starting from ground and continuing all the way up
to regulation (see Figure 6). This ability is not possible
with typical Boost converters in which the output is taken
from the cathode of the Schottky diode (CAPP node in
Figure 5).
The LT3582 series incorporates an output disconnect
PMOS allowing VOUTP to be grounded during shutdown.
L1
SWP
D1
CAPP
LT3582
SERIES
VOUTP
C1
C3
C2
DISCONNECT
CONTROL
VIN
Once enabled, the Disconnect Control circuit actively
drives the PMOS gate allowing VOUTP to ramp up linearly
as shown in Figure 6. Once VOUTP reaches regulation,
the PMOS is fully turned “on” to reduce resistance and
improve efficiency.
Power-Up Sequencing (PUSEQ bits)
Once enabled, the part requires a delay of TSTARTUP (64μs
typ) to properly configure itself. Once configured, the order
in which VOUTP and VOUTN ramp to regulation is controlled
by the PUSEQ bits. The combinations available for the
LT3582 are shown in Table 2. The LT3582-5/LT3582-12
are pre-configured with the 11 combination.
Table 2. Power-Up Sequences
PUSEQ[1:0] Power-Up Sequence
00
Outputs are disabled, neither output ramps up
01
VOUTN ramps up 1st, followed by VOUTP
10
VOUTP ramps up 1st, followed by VOUTN
11
Both VOUTP & VOUTN ramp up starting at the
same time.
Selecting the 01 or 10 combinations cause one of the outputs to start ramping shortly after SHDN rises. The ramp
rate of VOUT is controlled by the RAMP pin as discussed in
the Soft-Start section. After VOUT nears its target regulation voltage, the remaining output is activated and ramps
LOAD
A
3582512 F05
E
VRAMPP
0.5V/DIV
Figure 5: Boost Converter Topology
CAPP
3V/DIV
B
D
VOUTP
3V/DIV
C
IL2
0.2A/DIV
CAPP
2V/DIV
VOUTP
2V/DIV
VRAMPP
0.2V/DIV
IL2
0.2A/DIV
50μs/DIV
3582512 F07
Figure 7: VOUTP Soft-Start with Excessive Ramp Rate
5μs/DIV
3582512 F06
Figure 6: VOUTP Soft-Start Ramping from Ground
3582512f
15
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
under control of its respective RAMP pin (see Figure 8
below). The power-up sequencing concludes when both
outputs have reached regulation.
Evaluating PUSEQ Settings (LT3582 Only): After SHDN
rises, the LT3582 uses the PUSEQ configuration found
in OTP. The effects of differing PUSEQ settings can be
observed without writing to OTP by taking the following
actions:
PDDIS = 0 disables the power-down discharge causing
the chip to shut down immediately after SHDN falls. The
PDDIS bit must only be set in conjunction with PUSEQ being
set to 11. Driving SHDN low, with power-down discharge
enabled (PDDIS = 1) causes the chip to power-down after
first discharging the output voltages. Specifically, driving
SHDN low causes the following sequence of events to
happen:
1. Both converters are turned off.
1. Write the SWOFF bit high, stopping both converters
and discharging the RAMP pins.
2. Discharge currents are enabled to discharge the
output capacitors
2. Write the desired settings to the PUSEQ bits in
REG2.
• See Electrical Charateristics for IVOUTP-PDS and
ICAPP-PDS which help discharge VOUTP and CAPP
3. Set the RSEL2 bit high which selects the REG2
configuration settings.
• See Electrical Charateristics for IVOUTN-PDS which
helps discharge VOUTN
4. Write SWOFF low which restarts both converters.
This will initiate the desired power-up sequence that can
be observed with an oscilloscope.
3. The chip waits until the output voltages have
discharged to within ~0.5V to ~1.5V of ground.
Power-Down Discharge (PDDIS bit)
4. Discharge currents are disabled and the LT3582
powers down.
The PDDIS bit is used to enable power down discharge.
This bit is pre-configured to a “1” for the LT3582-5 and
LT3582-12, thus enabling power-down discharge.Setting
RAMPP
VRAMPP
0.5V/DIV
VRAMPN
0.5V/DIV
RAMPN
VVOUTP
5V/DIV
VVOUTN
5V/DIV
5ms/DIV
3582512 F08
Figure 8: Power-up Sequencing (PUSEQ=10)
3582512f
16
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Since the LT3582 series won’t power-down until both
outputs are discharged (when power-down sequencing
is enabled), make sure VOUTP & VOUTN can be grounded.
This is not a problem in most topologies. However, read
the section Output Disconnect Operating Limits for additional information.
Configuration Lockout (LOCK bit)
After a desired configuration is programmed into OTP, the
LOCK bit can be set to prohibit subsequent changes to the
configuration. The LT3582-5 and LT3582-12 are preconfigured with the LOCK bit set to a logic “1” which:
• Forces the chip to use the OTP configuration
only.
• Forces all I2C reads from addresses 0-2 to return
OTP data.
• Prohibits any further programming of the OTP
memory. Any further attempts to program OTP leaves
the OTP memory unchanged and sets the FAULT bit
in the CMDR.
The LOCK OTP bit is set by programming a logic “1” into
bit 6 of OTP2. Regardless of the RSEL2 setting, I2C reads
of the LOCK bit always indicate the LOCKed or unlocked
state of the OTP memory.
OTP Programming (LT3582 only)
The LT3582 contains One Time Programmable non-volatile memory to permanently store the chip configuration.
Before programming, it’s recommended to set the SWOFF
bit to disable switching activity and prevent unexpected
chip behavior while the configuration is being changed.
Programming involves the transfer of information from
the REG bytes to the OTP bytes. Therefore, valid data
must first be written to the desired REG bytes. After the
REG bytes are written, they are selected by setting the
corresponding RSEL bits in the CMDR. This forces the chip
into the desired configuration and selects those bytes for
programming to OTP. After 15V has been applied to VPP,
the WOTP bit is set in the CMDR to start the programming.
Finally, the WOTP bit is cleared to finish the programming.
An example programming algorithm is given below.
OTP programming draws about 3-6mA per bit from the
VPP pin. It is possible to program all 23 bits simultaneously (up to ~138mA), but it is recommended that one byte
is programmed at a time to reduce noise on VPP caused
by the sudden change in current. A 1-10μF VPP bypass
capacitor is also recommended to prevent voltage droop
after programming begins. Also, avoid hot-plugging VPP
which results in very fast voltage ramp rates and can lead
to excessive voltage on the VPP pin.
Example OTP Programming Algorithm:
1. Apply 15V to the VPP pin. This can be done at any
time before step 5.
2. Write 50h to the CMDR. This disables the power
switches during programming by setting the SWOFF
bit in the CMDR. This also clears the FAULT bit.
3. Write desired data to REG0-REG2.
4. Write 11h to the CMDR. This selects REG0 for programming while keeping the switches off.
5. Write 91h to the CMDR. This programs the REG0
data to OTP0.
6. Write 11h to the CMDR. This command can be sent
immediately after step 5. This stops the programming.
7. Read the CMDR and verify that the FAULT bit is
not set.
8. Repeat steps 4-7 for the remaining bytes that need
programming.
9. Write 10h to the CMDR. This selects the OTP data
for read verification.
3582512f
17
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
10. Read the OTP data and verify the contents.
11. Write 00h to CMDR. This enables the power switches
and the chip will operate from the OTP configuration.
12. Float the VPP pin. This can be done at any time
after step 8.
Choosing Inductors
Several series of inductors that work well with the LT3582
series are listed in Table 3. This table is not complete, and
there are many other manufacturers and parts that can
be used. Consult each manufacturer for more detailed
information and for their entire selection of related parts,
as many different sizes and shapes are available.
Table 3: Inductor Manufacturers
Coilcraft
LPS3008-LPS4018 Series, www.coilcraft.com
XPL2010 Series
Murata
LQH32C, LQH43C Series
Sumida
CDRH26D09, CDRH26D11, www.sumida.com
CDRH3D14 Series
TDK
VLF and VLCF Series
Würth
Elektronik
WE-TPC Series Type T, TH, www.we-online.com
XS and S
www.murata.com
www.tdk.com
Inductances of 2.2μH-10μH typically result in a good
tradeoff between inductor size and system performance.
More inductance typically yields an increase in efficiency
at the expense of increased output ripple. Less inductance
may be used in a given application depending on required
efficiency and output current. For higher efficiency, choose
inductors with high frequency core material, such as ferrite,
to reduce core losses. Also to improve efficiency, choose
inductors with more volume for a given inductance. The
inductor should have low DCR (copper-wire resistance)
to reduce I2R losses, and must be able to handle the peak
inductor current without saturating. To minimize radiated
noise, use a toroidal or shielded inductor (note that the
inductance of shielded types will drop more as current
increases, and will saturate more easily).
Peak Current Rating: Real inductors can experience
a drop in inductance as current and temperature
increase. The inductors should have saturation current ratings higher than the peak inductor currents.
The peak inductor currents can be calculated as:
IPK ≅ ILIMIT +
VLSWON • TOS
mA
L
where:
IPK
ILIMIT
L
VLSWON
TOS
= Peak inductor current
= Typically 350mA for Boost and 600mA for
Inverting
= Inductance in μH
= Maximum inductor voltage when the
power switch is “on”. Typically max VIN
for the Boost and Inverting converters.
= 100 for Boost and 125 for Inverting
Maximum Load Currents: Use one of the following equations to estimate the maximum output load current for the
positive and negative output voltages:
IOUTP =
⎛ VIN(MIN) ⎞ ⎛
TOFF _ MIN • (VOUTP + 0.5 – VIN(MIN) )⎞
⎟• 0.8η
⎜
⎟• ⎜IPK –
2•L
⎝ VOUTP ⎠ ⎝
⎠
or IOUTN =
⎛
⎞ ⎛
VIN(MIN)
• (|VOUTN | +0.5)⎞
T
⎜
⎟ • ⎜IPK – OFF _ MIN
⎟ • 0.8η
⎜V
⎟ ⎝
+
|V
|
2
•
L
⎠
IN(MIN)
OUTN
⎝
⎠
3582512f
18
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Where…
= Regulation voltage
VOUT
VIN(MIN) = Minimum input voltage.
= Peak inductor current. See prior section
IPK
Peak Current Rating. Use minimum ILimit
rating for these calculations.
η
= Power conversion efficiency (about 88%
for Boost or 78% for Inverting)
TOFF_MIN = Minimum switch off time. Typically
100ns for Boost and 125ns for Inverting.
IOUT
= Output load current
For example, if VOUTP = 10V, VOUTN = –10V, VIN = 5V, and
L = 4.7μH then IOUTP = 117mA and IOUTN = 105mA.
Note: The 155mA (Typ) current limit of the output disconnect PMOS (see Electrical Characteristics) may limit
maximum IOUTP unless CAPP is shorted to VOUTP. See
Improving Boost Converter Efficiency.
Maximum Slew Rate: Lower inductance causes higher
current slew rates which can lead to current limit overshoot. Choose an inductance higher than LMIN to limit
the overshoot:
LMIN = VIN(MAX) • 0.2µH
where VIN(MAX) is the maximum input voltage. Using the
previous example VIN = 3V, LMIN = 0.6μH.
Capacitor Selection
The small size and low ESR of ceramic capacitors makes
them suitable for most LT3582 series applications. X5R
and X7R types are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 4.7μF input capacitor and a 2.2μF-10μF output capacitor are sufficient for
most LT3582 series applications. Always use a capacitor
with a sufficient voltage rating. Many capacitors rated at
2.2μF to 10μF, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired output voltage.
Generally a 1206 capacitor will be adequate. A 0.22μF to
1μF capacitor placed on the CAPP node is recommended
to filter the inductor current while the larger 2.2μF to 10μF
placed on the VOUTP & VOUTN nodes will give excellent
transient response and stability. Avoid placing large value
capacitors (generally > 6.8μF) on both CAPP and VOUTP.
This configuration can be less stable since it creates two
poles, one at the CAPP pin and the other at the VOUTP
pin, which can be near each other in frequency. Table 4
shows a list of several capacitor manufacturers. Consult
the manufacturers for more detailed information and for
their entire selection of related parts.
Table 4: Ceramic Capacitor Manufacturers
MANUFACTURER
PHONE
URL
Kemet
408-986-0424
www.kemet.com
Murata
814-237-1431
www.murata.com
Taiyo Yuden
408-573-4150
www.t-yuden.com
TDK
847-803-6100
www.tdk.com
Diode Selection
Schottky diodes, with their low forward voltage drops
and fast switching speeds, are recommended for use with
the LT3582 series. The Diodes Inc. B0540WS is a very
good choice in a small SOD-323 package. This diode is
rated to handle an average forward current of 500mA and
performs well across a wide temperature range. Schottky
diodes with very low forward voltage drops are also available. These diodes may improve efficiency at moderate
and cold temperatures, but will likely reduce efficiency
at higher temperatures due to excessive reverse leakage
currents.
3582512f
19
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Output Disconnect Operating Limits
Improving Boost Converter Efficiency
The LT3582 series has a PMOS output disconnect switch
connected between CAPP and VOUTP . During normal
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that
the output load current doesn’t exceed the PMOS current
limit. Exceeding the current limit causes a significant
rise in PMOS power consumption which may damage
the device.
The efficiency of the Boost converter can be improved by
shorting the CAPP pin to the VOUTP pin (see Figure 11). The
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger VOUTP capacitor
can adequately filter the output voltage.
During shutdown, the PMOS switch is open and CAPP is
isolated from VOUTP up to a voltage difference of 5-5.5V.
In most cases this allows VOUTP to discharge to ground.
However, when the Boost inductor input exceeds 5.5V,
the CAPP-VOUTP voltage may exceed 5V allowing some
current flow through the PMOS switch. In addition, applying CAPP-VOUTP voltages in excess of 5.7V(typical) may
activate internal protection circuitry which turns the PMOS
“on” (see Figure 10). If the current is not limited, this can
lead to a sharp increase in the PMOS power consumption
and may damage the device. If this situation cannot be
avoided, limit PMOS power consumption to less than 1/3
Watt (about 50mA at 7V) to avoid damaging the device.
Refer to the Absolute Maximum Ratings table for maximum
limits on CAPP-VOUTP voltages and currents.
Note that the ripple voltage on VOUTP will typically increase in this configuration since the output disconnect
PMOS, when not shorted, helps to create an RC filter at
the output. Also, if the VOUTP pin is shorted to CAPP,
the power-down discharge should not be enabled. VOUTP
cannot be discharged to ground during shutdown due to
the path from VIN to VOUTP through the external inductor
ICAPP-VOUTP
20μA/DIV
3582512 F11
VCAPP-VOUTP 1V/DIV
180
Figure 10: PMOS Current vs. Voltage During Shutdown
160
PMOS CURRENT (mA)
140
4
120
3
100
80
13
SWN
SWP
SWN
VIN
CAPP
GND
60
LT3582
40
CAPP
VOUTP
20
2
VOUTN
VPP
0
0
100
200
300
CAPP-VOUTP (mV)
400
500
3582512 F10
Figure 9: PMOS Current vs. Voltage During Normal Operation
SDA
SCL
8
SHDN
RAMPP RAMPN
7
6
CA
12
5
11
10
C1
ILOAD
9
14
15
16
1
3582512 F12
Figure 11: Improved Efficiency
3582512f
20
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
and diode. Finally, due to the path from VIN to VOUTP,
current will flow through the integrated feedback resistor
whenever voltage is present on VIN.
Inrush Current
When the Boost inductor input voltage (usually VIN) is
stepped from ground to the operating voltage, a high
level of inrush current may flow through the inductor
and Schottky diode into the CAPP capacitor. Conditions
that increase inrush current include a larger more abrupt
voltage step at the inductor input, larger CAPP capacitors
and inductors with low inductances and/or low saturation
currents. For circuits that use output capacitor values
within the recommended range and have input voltages
of less than 5V, inrush current remains low, posing no
hazard to the devices. In cases where there are large
input voltage steps (more than 5V) and/or a large CAPP
capacitor is used, inrush current should be measured to
ensure safe operation.
Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interference (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have sharp rising and falling edges.
Minimize the length and area of all traces connected to
the SWP/SWN pins and always use a ground plane under
the switching regulator to minimize interplane coupling.
Suggested component placement is shown in Figure 12.
Make sure to include the ground plane cuts as shown in
Figure 12. The switching action of the regulators can cause
large current steps in the ground plane. The cuts reduce
noise by recombining the current steps into a continuous
flow under the chip, thus reducing di/dt related ground
noise in the ground plane.
Thermal Lockout
If the die temperature reaches approximately 147°C, the
part will go into thermal lockout. In this event, the chip
is reset which turns off the power switches and starts to
discharge the RAMP capacitors. The part will be re-enabled
when the die temperature drops by about 3.5°C.
3582512f
21
LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CA
SCL
SDA
VPP
CVPP
(OPT)
16
VOUTN
GND
COUTN
L2
CIN
15
14
13
1
L1
12
17
2
11
3
10
4
9
5
6
7
8
CCAPP
COUTP
VIN
VIAS TO GROUND PLANE UNDER
PIN 17 REQUIRED TO IMPROVE
THERMAL PERFORMANCE
SHDN
VOUTP
GROUND PLANE
3582512 G13
Figure 12: Suggested Component Placement (not to scale)
3582512f
22
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
±5V Outputs from a Single 2.7V to 3.8V Input
D1
L1
6.8μH
SWN
SHDN
SWN
VIN
INPUT
2.7V TO 3.8V
SWP
L2 6.8μH
GND
LT3582
C4 1μF
C2
10μF
VNEG
–5V
100mA (VIN ≥ 2.7V)
125mA (VIN ≥ 3.3V)
CAPP
VOUTN
I2C
INTERFACE
OPTIONAL ON
LT3582-5
CAPP
SDA
VOUTP
SCL
VPP
CA
(
C1
4.7μF
D2
)
C3
10μF
RAMPP RAMPN
C5
22nF
VPOS
5V
100mA (VIN ≥ 2.7V)
124mA (VIN ≥ 3.3V)
C6
22nF
3582512 TA02a
REG0/OTP0 = 24h
REG1/OTP1 = 4Ch
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7μF, 6.3V, X5R, 0805
C2-C3: 10μF, 6.3V, X5R 0805
C4: 1μF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTP to GND
95
Efficiency and Power Loss, Load from VOUTN to GND
100
VIN = 3.3V
95
180
VIN = 3.3V
90
160
85
80
50
65
40
55
30
EFFICIENCY (%)
60
140
100
65
80
55
60
40
20
45
120
75
45
20
10
0.1
1
10
LOAD CURRENT (mA)
0
100
35
1
10
LOAD CURRENT (mA)
0.1
3582512 TA02b
0
100
3582512 TA02c
Efficiency and Power Loss, Load from VOUTP to VOUTN
95
300
VIN = 3.3V
85
250
75
200
65
150
55
100
45
50
35
0.1
1
10
LOAD CURRENT (mA)
POWER LOSS (mW)
EFFICIENCY (%)
35
POWER LOSS (mW)
70
75
POWER LOSS (mW)
EFFICIENCY (%)
85
0
100
3582512 TA02d
3582512f
23
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
±5V Outputs from a Single 2.7V to 3.8V Input (Improved Efficiency)
D1
L1
6.8μH
SWN
SHDN
SWN
VIN
SWP
GND
CAPP
VOUTN
I C
INTERFACE
OPTIONAL ON
LT3582-5
)
CAPP
SDA
VOUTP
SCL
VPP
CA
(
C1
4.7μF
C3 10μF
C2
10μF
2
L2 6.8μH
D2
LT3582
VNEG
–5V
100mA (VIN ≥ 2.7V)
125mA (VIN ≥ 3.3V)
INPUT
2.7V TO 3.8V
VPOS
5V
110mA (VIN ≥ 2.7V)
150mA (VIN ≥ 3.3V)
RAMPP RAMPN
C5
22nF
C6
22nF
3582512 TA03
REG0/OTP0 = 24h
REG1/OTP1 = 4Ch
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7μF, 6.3V, X5R, 0805
C2-C3: 10μF, 6.3V, X5R, 0805
C4: 1μF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTP to GND
95
80
VIN = 3.3V
70
85
50
65
40
30
55
POWER LOSS (mW)
EFFICIENCY (%)
60
75
20
45
10
35
0.1
1
10
LOAD CURRENT (mA)
0
100
3582512 TA03a
3582512f
24
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
12V and –5V Outputs from a Single 2.7V to 5.5V Input
D1
L1
6.8μH
SWN
SHDN
SWN
VIN
INPUT
2.7V TO 5.5V
SWP
L2 6.8μH
GND
LT3582
C4 1μF
C2
10μF
VNEG
–5V
100mA
CAPP
VOUTN
I2C
INTERFACE
C1
4.7μF
D2
CAPP
SDA
VOUTP
SCL
VPP
CA
C3
4.7μF
RAMPP RAMPN
C5
22nF
VPOS
12V
38mA (VIN = 2.7)
58mA (VIN = 3.6)
95mA (VIN = 5.5)
C6
22nF
3582512 TA04a
REG0/OTP0 = B0h
REG1/OTP1 = 4Ch
REG2/OTP2 = 0Bh
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7μF, 6.3V, X5R, 0805
C2: 10μF, 6.3V, X5R, 0805
C3: 4.7μF, 16V, X5R, 0805
C4: 1μF, 16V, X5R, 0603
C5-C6: 22nF, 0603
Efficiency and Power Loss, Load from VOUTN to GND
Efficiency and Power Loss, Load from VOUTP to GND
95
95
100
VIN = 3.6V
180
VIN = 3.6V
90
160
85
80
60
50
65
40
55
30
EFFICIENCY (%)
75
140
100
65
80
55
60
40
20
45
120
75
45
20
10
0
100
35
1
10
LOAD CURRENT (mA)
35
1
10
LOAD CURRENT (mA)
0.1
0
100
3582512 TA04c
3582512 TA04b
Efficiency and Power Loss, Load from VOUTP to VOUTN
95
200
VIN = 3.6V
180
85
160
140
75
120
100
65
80
55
60
POWER LOSS (mW)
EFFICIENCY (%)
0.1
POWER LOSS (mW)
70
POWER LOSS (mW)
EFFICIENCY (%)
85
40
45
20
35
0.1
1
10
LOAD CURRENT (mA)
0
100
3582512 TA04d
3582512f
25
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
D1
L1
6.8μH
SWN
SHDN
SWN
VIN
INPUT
4.5V TO 5.5V
SWP
L2 6.8μH
GND
LT3582
C4 1μF
C2
4.7μF
VNEG
–12V
85mA
CAPP
VOUTN
I2C
INTERFACE
(
)
CAPP
SDA
VOUTP
SCL
VPP
CA
OPTIONAL ON
LT3582-12
C1
4.7μF
D2
VPOS
12V
80mA
C3
RAMPP RAMPN
C5
10nF
C6
10nF
3582512 TA05a
REG0/OTP0 = B0h
REG1/OTP1 = D8h
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT XPL2010-682
C1: 4.7μF, 6.3V, X5R, 0805
C2: 4.7μF, 16V, X5R, 0805
C3: 1× 4.7μF OR 2× 4.7μF OR 10μF
16V, X5R, 0805
C4: 1μF, 16V, X5R, 0603
C5-C6: 10nF, 0603
Figure 13. ±12V Outputs from a Single 5V Input
VOUTP Ripple
VOUTN Ripple and C2 Selection
80
25
4.7μF 16V 0805 X5R
OUTPUT RIPPLE (mV)
OUTPUT RIPPLE (mV)
20
15
10
60
10μF 16V 0805 X5R
40
2× 4.7μF 16V 0805 X5R
20
5
0
0
0
20
40
60
LOAD CURRENT (mA)
80
0
20
40
60
LOAD CURRENT (mA)
3582512 TA05b
80
3582512 TA05c
Also See Typical Characteristics and Front Page for Additional Data
3582512f
26
LT3582/LT3582-5/LT3582-12
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 p0.05
3.50 p 0.05
1.45 p 0.05
2.10 p 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 p 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
15
16
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
1.45 p 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
3582512f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3582/LT3582-5/LT3582-12
TYPICAL APPLICATION
Tiny AMOLED Power Supply is 0.8mm (Max) Thin
SWN
VIN
90
INPUT
2.7V TO 4.2V
SWP
C4 10μF
C2
10μF
VNEG
–5V
90mA
CAPP
VOUTN
2
I C
INTERFACE
C1
10μF
D2
LT3582
CAPP
SDA
CA
VPOS
4.6V
100mA
VOUTP
SCL
VPP
C3
10μF
RAMPP RAMPN
C5
10nF
300
250
L2 1.5μH
GND
350
VIN = 3.3V
80
EFFICIENCY (%)
SHDN
70
200
60
150
50
100
40
50
30
0.1
C6
10nF
POWER LOSS (mW)
L1
1.5μH
D1
SWN
Efficiency and Power Loss, Load from VOUTP to VOUTN
1
10
LOAD CURRENT (mA)
0
100
3582512 TA06b
3582512 TA06a
REG0/OTP0 = 1Ch
REG1/OTP1 = 4Ch
REG2/OTP2 = 07h
D1-D2: PANASONIC M21D3800L LOW VF SCHOTTKY
L1-L2: TDK MLP3216S1R5L
C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805
C5-C6: 0402 X5R
RELATED PARTS
PART
DESCRIPTION
COMMENTS
LT1944/-1(Dual)
Dual Output 350mA ISW, Constant Off-Time, High
Efficiency Step-Up DC/DC Converter
VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20μA, ISD <1μA, MS10
LT1945(Dual)
Dual Output, Pos/Neg, 350mA ISW, Constant OffTime, High Efficiency Step-Up DC/DC Converter
VIN: 1.2V to 15V, VOUT(MAX) = ±34V, IQ = 20μA, ISD <1μA, MS10
LT3463/A
Dual Output, Boost/Inverter, 250mA ISW, Constant VIN: 2.4V to 15V, VOUT(MAX) = ±40V, IQ = 40μA, ISD <1μA, DFN
Off-Time, High Efficiency Step-Up DC/DC
Converter with Integrated Schottkys
LT3471
Dual Output, Boost/Inverter, 1.3A ISW, 1.2MHz,
High Efficiency Boost-Inverting DC/DC Converter
VIN: 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD <1μA, DFN
LT3472
Dual Output, Boost/Inverter, 0.35A ISW, 1.2MHz,
High Efficiency Boost-Inverting DC/DC Converter
VIN: 2.2V to 16V, VOUT(MAX) = ±34V, IQ = 2.8mA, ISD <1μA, DFN
LT3477
42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED
Driver
VIN: 2.5V to 25V, VOUT(MAX) = 40V, IQ = Analog/PWM, ISD <1μA, QFN,
TSSOP-20E
LT3494/A
180/350mA (ISW), Low Noise High Efficiency StepUp DC/DC Converter
VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 65μA, ISD <1μA, 2mm × 3mm DFN
LT3495/ LT3495B/
650/350mA (ISW), Low Noise High Efficiency StepLT3495-1/ LT3495B-1 Up DC/DC Converter
VIN: 2.5V to 16V, VOUT(MAX) = 40V, IQ = 60μA, ISD <1μA, 2mm × 3mm DFN
LT1930/A
1A (ISW ), 1.2/2.2MHz, High Efficiency Step-Up
DC/DC Converter
VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2/5.5mA, ISD <1μA, ThinSOT
LT1931/A
1A (ISW ), 1.2/2.2MHz, High Efficiency Inverting
DC/DC Converter
VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2/5.5mA, ISD <1μA, ThinSOT
LT3467/A
1.1A (ISW ), 1.3/2.1MHz, High Efficiency Step-Up
DC/DC Converter with Soft-Start
VIN: 2.4V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD <1μA, ThinSOT
LT1618
1.5A (ISW ), 1.4MHz, High Efficiency Step-Up
DC/DC Converter
VIN: 1.6V to 18V, VOUT(MAX) = 35V, IQ = 1.8mA, ISD <1μA, MS10, DFN
LT1946/A
1.5A (ISW ), 1.2/2.7MHz, High Efficiency Step-Up
DC/DC Converter
VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD <1μA, MS8E
3582512f
28 Linear Technology Corporation
LT 0509 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
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