Cypress CY62256VNLL-70SNXE 256k (32k x 8) static ram Datasheet

CY62256VN
256K (32K x 8) Static RAM
Functional Description[1]
Features
• Temperature Ranges
The CY62256VN family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tri-state drivers.
These devices have an automatic power-down feature,
reducing the power consumption by over 99% when
deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Speed: 70 ns
• Low voltage range: 2.7V–3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in standard Pb-free and non Pb-free 28-lead
(300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead
Reverse TSOP-I packages
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A13
A14
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06512 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY62256VN
Product Portfolio
Power Dissipation
VCC Range (V)
Product
Range
Min.
Typ.[2]
Max.
Operating, ICC (mA)
Standby, ISB2 (µA)
Typ.[2]
Typ.[2]
Max.
Max.
CY62256VNLL
Com’l
2.7
3.0
3.6
11
30
0.1
5
CY62256VNLL
Ind’l
2.7
3.0
3.6
11
30
0.1
10
CY62256VNLL
Automotive-A
2.7
3.0
3.6
11
30
0.1
10
CY62256VNLL
Automotive-E
2.7
3.0
3.6
11
30
0.1
130
Pin Configurations
Narrow SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
7
6
8
9
5
4
3
2
10
11
12
13
14
15
16
17
18
1
28
27
26
25
24
23
22
TSOP I
Reverse Pinout
Top View
(not to scale)
19
20
21
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26 Input
A0–A14. Address Inputs
11–13, 15–19
Input/Output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
27
Input/Control
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted
20
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins
14
Ground
GND. Ground for the device
28
Power Supply VCC. Power supply for the device
Note:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C, and tAA = 70 ns.
Document #: 001-06512 Rev. *A
Page 2 of 12
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CY62256VN
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................ –65°C to + 150°C
Operating Range
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .......................................... –0.5V to + 4.6V
Device
Range
CY62256VN Commercial
Ambient
Temperature
(TA)[4]
VCC
0°C to +70°C
2.7V to 3.6V
−40°C to +85°C
Industrial
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Automotive-A −40°C to +85°C
DC Input Voltage[3] .................................–0.5V to VCC + 0.5V
Automotive-E −40°C to +125°C
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
-70
Parameter
Description
Test Conditions
Min.
Typ.[2]
Max.
Unit
VOH
Output HIGH Voltage
IOH = −1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.3V
V
VIL
Input Leakage Voltage
–0.5
0.8
V
IIX
Input Leakage Current
Com’l/Ind’l/Auto-A
–1
+1
µA
IOZ
Output Leakage Current GND < VIN < VCC, Output
Disabled
GND < VIN < VCC
2.4
V
Auto-E
–10
+10
µA
Com’l/Ind’l/Auto-A
–1
+1
µA
Auto-E
–10
+10
µA
11
30
mA
ICC
VCC Operating Supply
Current
VCC = 3.6V, IOUT = 0 mA,
f = fMAX = 1/tRC
All Ranges
ISB1
Automatic CE
Power down Current TTL Inputs
VCC = 3.6V, CE > VIH,
All Ranges
VIN > VIH or VIN < VIL, f = fMAX
100
300
µA
ISB2
Automatic CE
Power-down CurrentCMOS Inputs
VCC = 3.6V, CE > VCC – 0.3V Com’l
VIN > VCC – 0.3V or VIN <
Ind’l/Auto-A
0.3V, f = 0
Auto-E
0.1
5
µA
10
130
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature
Document #: 001-06512 Rev. *A
Page 3 of 12
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CY62256VN
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Thermal Resistance[5]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
SOIC
TSOPI
RTSOPI
Unit
68.45
87.62
87.62
°C/W
26.94
23.73
23.73
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC
10%
R2
50 pF
90%
10%
90%
GND
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth
OUTPUT
Vth
Parameter
Value
Units
R1
1100
Ohms
R2
1500
Ohms
RTH
645
Ohms
VTH
1.750
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions[6]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
[6]
tR[5]
Typ.[2]
Min.
Max.
1.4
VCC = 1.4V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V
V
Com’l
0.1
µA
3
Ind’l/Auto-A
6
Auto-E
50
Chip Deselect to Data
Retention Time
Operation Recovery Time
Unit
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
1.8V
VDR > 1.4V
tCDR
1.8V
tR
CE
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed VCC + 0.3V.
Document #: 001-06512 Rev. *A
Page 4 of 12
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CY62256VN
Switching Characteristics Over the Operating Range[7]
CY62256VN-70
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
70
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
ns
70
10
ns
ns
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low-Z[8]
OE HIGH to High-Z
tHZOE
[8]
tLZCE
CE LOW to Low-Z
tHZCE
CE HIGH to High-Z[8, 9]
tPU
CE LOW to Power-up
ns
25
ns
25
ns
10
ns
0
CE HIGH to Power-down
tPD
Write Cycle
5
[8, 9]
ns
70
ns
[10, 11]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[8, 9]
tLZWE
WE HIGH to Low-Z[8]
ns
25
10
ns
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06512 Rev. *A
Page 5 of 12
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CY62256VN
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[13, 14]
t RC
CE
tACE
OE
t HZOE
tHZCE
tDOE
DATA OUT
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
t PD
t PU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tSA
WE
tHA
t PWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAINVALID
t HZOE
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 001-06512 Rev. *A
Page 6 of 12
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CY62256VN
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
t HD
DATAINVALID
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC
ADDRESS
CE
tAW
t HA
tSA
WE
tSD
DATA I/O
NOTE 17
t HZWE
Document #: 001-06512 Rev. *A
t HD
DATA INVALID
tLZWE
Page 7 of 12
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CY62256VN
Typical DC and AC Characteristics
1.4
1.6
1.4
1.2
2.5
1.0
2.0
TA= 25°C
0.4
0.2
0.0
25
125
1.6
2.0
1.4
NORMALIZED tAA
VCC = 3.0V
TA = 25°C
0.0
1.65
1.2
1.0
0.8
0.5
2.1
2.6
3.1
3.6
0.6
−55
25
125
OUTPUT SOURCE CURRENT (mA)
3.
3V
105
OUTPUT SINK CURRENT
14 vs. OUTPUT VOLTAGE
12
10
8
6
4
TA = 25°C
2
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
25
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
2.5
ISB
–0.5
−55
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.0
1.0
0.5
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.5
1.5
0.4
0.0
−55
3.6
3.2
2.8
2.4
2.0
1.8
1.6
0.6
OUTPUT SINK CURRENT (mA)
0.6
0.8
=
0.8
cc
1.0
V
1.2
3.0
VCC = 3.0V
ISB2 µA
NORMALIZED ICC
NORMALIZED ICC
1.8
0.2
NORMALIZED tAA
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
–14
–12
–10
–8
–6
TA = 25°C
–4
0
0.0
0.5
1.0
1.5
2
2.5
OUTPUT VOLTAGE (V)
Document #: 001-06512 Rev. *A
Page 8 of 12
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CY62256VN
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
1.25
NORMALIZED ICC
DELTA tAA (ns)
30.0
25.0 T = 25°C
A
VCC = 3V
20.0
15.0
10.0
VCC = 3.0V
1.00
TA = 25°C
VIN = 0.5V
0.75
5.0
0.0
0
200
400
600
0.50
1
800 1000
10
20
30
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
Truth Table
CE
WE
OE
H
X
X
High-Z
Inputs/Outputs
Deselect/Power-down
Mode
Standby (ISB)
Power
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Deselect, Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
70
Ordering Code
CY62256VNLL-70SNC
Package
Diagram
51-85092 28-lead (300-mil) Narrow SOIC
CY62256VNLL-70SNXC
CY62256VNLL-70ZC
Package Type
Operating
Range
Commercial
28-lead (300-mil) Narrow SOIC (Pb-Free)
51-85071
CY62256VNLL-70ZXC
28-lead TSOP I
28-lead TSOP I (Pb-Free)
CY62256VNLL-70SNXI
51-85092 28-lead (300-mil) Narrow SOIC (Pb-Free)
CY62256VNLL-70ZI
51-85071
28-lead TSOP I
51-85074
28-lead Reverse TSOP I
CY62256VNLL-70ZXA
51-85071
28-lead TSOP I (Pb-Free)
Automotive-A
CY62256VNLL-70SNXE
51-85092
28-lead (300-mil) Narrow SOIC (Pb-Free)
Automotive-E
CY62256VNLL-70ZXE
51-85071
28-lead TSOP I (Pb-Free)
CY62256VNLL-70ZRXE
51-85074
28-lead Reverse TSOP I (Pb-Free)
CY62256VNLL-70ZXI
CY62256VNLL-70ZRI
Industrial
28-lead TSOP I (Pb-Free)
CY62256VNLL-70ZRXI
28-lead Reverse TSOP I (Pb-Free)
Please contact your local Cypress sales representative for availability of other parts
Document #: 001-06512 Rev. *A
Page 9 of 12
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CY62256VN
Package Diagrams
28-lead (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
28-lead TSOP 1 (8 × 13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06512 Rev. *A
Page 10 of 12
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CY62256VN
Package Diagrams (continued)
28-lead Reverse TSOP 1 (8 × 13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06512 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62256VN
Document History Page
Document Title: CY62256VN 256K (32K x 8) Static RAM
Document Number: 001-06512
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
426504
See ECN
NXR
New Data Sheet
*A
488954
See ECN
NXR
Added Automotive product
Updated ordering Information table
Document #: 001-06512 Rev. *A
Page 12 of 12
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