Cypress CY8C5386PVI-057 Programmable system-on-chip (psoc ) Datasheet

PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including
interfaces such as USB, multi-master I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C53
family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3
microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean
primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities
for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware
updates.
Features
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
 Analog peripherals (1.71 V  VDDA  5.5 V)
 1.024 V ± 0.1% internal voltage reference across –40 °C to
+85 °C (14 ppm/°C)
 Successive approximation register (SAR) analog-to-digital
converter (ADC), 12-bit at 1 Msps
 Two 8-bit 8 Msps current digital-to-analog converters (DAC)
(IDACs) or 1 Msps voltage DACs (VDACs)
 Four comparators with 95-ns response time
 Two uncommitted opamps with 25-mA drive capability
 Two configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and sample and hold
 CapSense support

 32-bit ARM Cortex-M3 CPU core
DC to 80 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, multiple security features
 Up to 64 KB SRAM memory
 2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 million cycles, and 20 years retention
 24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
 Low voltage, ultra low power
 Wide operating voltage range: 0.5 V to 5.5 V
 High efficiency boost regulator from 0.5 V input to 1.8 V to
5.0 V output
 2 mA at 6 MHz
 Low power modes including:
• 2-µA sleep mode with real time clock (RTC) and
low-voltage detect (LVD) interrupt
• 300-nA hibernate mode with RAM retention
 Versatile I/O system
[1]
 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs )
 Any GPIO to any digital or analog peripheral routability
 LCD direct drive from any GPIO, up to 46x16 segments
®
[2]
 CapSense support from any GPIO
 1.2 V to 5.5 V I/O interface voltages, up to 4 domains
 Maskable, independent IRQ on any pin or port
 Schmitt-trigger transistor-transistor logic (TTL) inputs
 All GPIOs configurable as open drain high/low,
pull-up/pull-down, High-Z, or strong output
 Configurable GPIO pin state at power-on reset (POR)
 25 mA sink on SIO
 Digital peripherals
 20 to 24 programmable logic device (PLD) based universal
digital blocks (UDBs)
[1]
 Full CAN 2.0b 16 RX, 8 TX buffers
[1]
 Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
 Up to four 16-bit configurable timer, counter, and PWM blocks
 Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog


 Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single-wire
viewer (SWV), and TRACEPORT interfaces
 Cortex-M3 flash patch and breakpoint (FPB) block
 Cortex-M3 Embedded Trace Macrocell™ (ETM™)
generates an instruction trace stream.
 Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
 Cortex-M3 instrumentation trace macrocell (ITM) can be
used for printf-style debugging
 DWT, ETM, and ITM blocks communicate with off-chip debug
and trace systems via the SWV or TRACEPORT
2
 Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
 Precision, programmable clocking
 3- to 74-MHz internal oscillator over full temperature and
voltage range
 4- to 33-MHz crystal oscillator for crystal PPM accuracy
 Internal PLL clock generation up to 80 MHz
 32.768-kHz watch crystal oscillator
 Low power internal oscillator at 1, 33, and 100 kHz
 Temperature and packaging
 –40°C to +85°C degrees industrial temperature
 48-pin SSOP, 68-pin QFN, and 100-pin TQFP package
options

Notes
1. This feature on select devices only. See Ordering Information on page 91 for details.
2. GPIOs with opamp outputs are not recommended for use with CapSense
Cypress Semiconductor Corporation
Document Number: 001-55035 Rev. *G
•
198 Champion Court
•
,
San Jose CA 95134-1709
•
408-943-2600
Revised September 2, 2010
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Contents
1. Architectural Overview ................................................ 3
2. Pinouts .......................................................................... 5
3. Pin Descriptions ........................................................... 9
4. CPU .............................................................................. 10
4.1 ARM Cortex-M3 CPU .......................................... 10
4.2 Cache Controller ................................................. 12
4.3 DMA and PHUB .................................................. 12
4.4 Interrupt Controller .............................................. 14
5. Memory ........................................................................ 16
5.1 Static RAM .......................................................... 16
5.2 Flash Program Memory ....................................... 16
5.3 Flash Security ...................................................... 16
5.4 EEPROM ............................................................. 16
5.5 External Memory Interface .................................. 16
5.6 Memory Map ....................................................... 18
6. System Integration ..................................................... 19
6.1 Clocking System .................................................. 19
6.2 Power System ..................................................... 23
6.3 Reset ................................................................... 26
6.4 I/O System and Routing ...................................... 28
7. Digital Subsystem ...................................................... 34
7.1 Example Peripherals ........................................... 34
7.2 Universal Digital Block ......................................... 38
7.3 UDB Array Description ........................................ 41
7.4 DSI Routing Interface Description ....................... 42
7.5 CAN ..................................................................... 43
7.6 USB ..................................................................... 45
7.7 Timers, Counters, and PWMs ............................. 46
7.8 I2C ....................................................................... 46
8. Analog Subsystem ..................................................... 47
8.1 Analog Routing .................................................... 48
8.2 Successive Approximation ADC .......................... 50
8.3 Comparators ........................................................ 50
8.4 Opamps ............................................................... 52
8.5 Programmable SC/CT Blocks ............................. 52
8.6 LCD Direct Drive ................................................. 53
8.7 CapSense ............................................................ 54
Document Number: 001-55035 Rev. *G
8.8 Temp Sensor ....................................................... 54
8.9 DAC ..................................................................... 54
8.10 Up/Down Mixer .................................................. 55
8.11 Sample and Hold ............................................... 56
9. Programming, Debug Interfaces, Resources ........... 56
9.1 JTAG Interface .................................................... 57
9.2 SWD Interface ..................................................... 57
9.3 Debug Features ................................................... 57
9.4 Trace Features .................................................... 57
9.5 SWV and TRACEPORT Interfaces ..................... 57
9.6 Programming Features ........................................ 57
9.7 Device Security ................................................... 57
10. Development Support .............................................. 58
10.1 Documentation .................................................. 58
10.2 Online ................................................................ 58
10.3 Tools .................................................................. 58
11. Electrical Specifications .......................................... 59
11.1 Absolute Maximum Ratings ............................... 59
11.2 Device Level Specifications ............................... 60
11.3 Power Regulators .............................................. 62
11.4 Inputs and Outputs ............................................ 63
11.5 Analog Peripherals ............................................ 69
11.6 Digital Peripherals ............................................. 78
11.7 Memory ............................................................. 81
11.8 PSoC System Resources .................................. 86
11.9 Clocking ............................................................. 88
12. Ordering Information ................................................ 91
12.1 Part Numbering Conventions ............................ 93
13. Packaging .................................................................. 94
14. Acronyms .................................................................. 96
15. Reference Documents .............................................. 97
16. Document Conventions ........................................... 98
16.1 Units of Measure ............................................... 98
17. Revision History ....................................................... 99
18. Sales, Solutions, and Legal Information .............. 102
Page 2 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
1. Architectural Overview
Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Clock Tree
IMO
Digital System
Quadrature Decoder
UDB
UDB
UDB
UDB
I 2C Slave
Sequencer
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
16- Bit
PWM
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
I2C
CAN
2.0
16- Bit PRS
Master/
Slave
UDB
22 
UDB
8- Bit
Timer
Logic
UDB
FS USB
2.0
4x
Timer
Counter
PWM
Logic
UDB
UDB
UART
UDB
UDB
USB
PHY
GPIOs
32.768 KHz
( Optional)
GPIOs
Xtal
Osc
SIO
System Wide
Resources
Usage Example for UDB
4 to 33 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
WDT
and
Wake
EEPROM
CPU System
SRAM
8051 or
Cortex M3 CPU
Interrupt
Controller
FLASH
Cache
Controller
PHUB
DMA
Program &
Debug
GPIOs
System Bus
Memory System
Program
GPIOs
Debug &
Trace
EMIF
ILO
Boundary
Scan
Analog System
LCD Direct
Drive
ADC
POR and
LVD
1.71 to
5.5 V
Sleep
Power
1.8 V LDO
SMP
GPIOs
Power Management
System
2 x SC/ CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
CapSense
SAR
ADC
+
2x
Opamp
-
+
2 x DAC
4x
CMP
-
3 per
Opamp
GPIOs
SIOs
Clocking System
0. 5 to 5.5V
( Optional)
Document Number: 001-55035 Rev. *G
Page 3 of 102
[+] Feedback
PRELIMINARY
Figure 1-1 illustrates the major components of the CY8C53
family. They are:
 ARM Cortex-M3 CPU subsystem
 Nonvolatile subsystem
 Programming, debug, and test subsystem
 Inputs and outputs
 Clocking
 Power
 Digital subsystem
 Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of pre-built
and tested standard digital peripherals (UART, SPI, LIN, PRS,
CRC, timer, counter, PWM, AND, OR, and so on) that are
mapped to the UDB array. The designer can also easily create a
digital circuit using boolean primitives by means of graphical
design entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C53 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multimaster;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the “Example
Peripherals” section on page 34 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 34 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
 Analog muxes
 Comparators
 Analog mixers
 Voltage references
 Analog-to-Digital Converters (ADC)
 Digital-to-Analog Converters (DACs)
Document Number: 001-55035 Rev. *G
PSoC® 5: CY8C53 Family Datasheet
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C53 family also offers a SAR ADC. Featuring 12-bit
conversions at up to 1 M samples per second, it also offers low
nonlinearity and offset errors and SNR better than 70 dB. It is
well suited for a variety of higher speed analog applications.
Two high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
 Comparators
 Uncommitted opamps
 Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
 Transimpedance amplifiers
 Programmable gain amplifiers
 Mixers
 Other similar analog components
See the “Analog Subsystem” section on page 47 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. The designer can enable
an error correcting code (ECC) for high reliability applications. A
powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Two KB of byte-writable EEPROM
is available on-chip to store application data. Additionally,
selected configuration options such as boot speed and pin drive
mode are stored in nonvolatile memory. This allows settings to
activate immediately after POR.
Page 4 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow VOH
to be set independently of VDDIO when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the “I/O System and Routing” section on page 28 of this
datasheet.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in real time clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
2. Pinouts
The CY8C53 family supports a wide supply operating range from
1.71 to 5.5 V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a
3.3 V supply for LCD glass drive. The boost’s output is available
Document Number: 001-55035 Rev. *G
PSoC supports a wide range of low-power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
The details of the PSoC power modes are covered in the “Power
System” section on page 23 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include FPB,
DWT, ETM, and ITM. These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 56 of this datasheet.
The VDDIO pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-2 and
Figure 2-3. Using the VDDIO pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each VDDIO may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of VDDIO associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
Page 5 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 2-1. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(OpAmp0+, GPIO) P0[2]
(OpAmp0-/Extref0, GPIO) P0[3]
Vddio0
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
Vccd
Vssd
Vddd
(TRACECLK, GPIO) P2[3]
(TRACEDATA[0], GPIO) P2[4]
Vddio2
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
Vssb
Ind
Vboost
Vbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Lines show
Vddio to I/O
supply
association
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
[3]
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
[3]
P15[7] (USBIO, D-, SWDCK)
[3]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P0[5] (GPIO, OpAmp2-)
P0[4] (GPIO, OpAmp2+)
Vddio0
53
52
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
55
54
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
Vddd
Vssd
Vccd
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
64
63
62
61
60
59
Vddio2
P2[4] (GPIO, TRACEDATA[0])
P2[3] (GPIO, TRACECLK)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show Vddio
to IO supply
association
QFN
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
Vddio3
(GPIO) P3[5]
28
29
30
31
32
33
34
(MHz XTAL: Xi, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(Extref1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
24
25
26
27
Vddd
Vssd
Vccd
(MHz XTAL: Xo, GPIO) P15[0]
20
21
22
23
(GPIO) P1[6]
18
19
(Top View)
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[3](USBIO, D+, SWDIO) P15[6]
[3](USBIO, D-, SWDCK) P15[7]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
Vddio1
66
65
68
67
P2[5] (GPIO, TRACEDATA[1])
Figure 2-2. 68-pin QFN Part Pinout[4]
Notes
3. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
Document Number: 001-55035 Rev. *G
Page 6 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
P0[6] ( GPIO, IDA C0)
P0[5] ( GPIO, OpA mp 2-)
P0[4] ( GPIO, OpA mp 2+)
77
76
P4[5] ( GPIO)
P4[4] ( GPIO)
P4[3] ( GPIO)
P4[2] ( GPIO)
P0[7] ( GPIO, IDA C2)
82
81
80
79
78
Vccd
P4[7] ( GPIO)
P4[6] ( GPIO)
85
84
83
Vdd d
Vssd
87
86
90
89
88
P15[4] ( GPIO)
P6[3] ( GPIO)
P6[2] ( GPIO)
P6[1] ( GPIO)
P6[0] ( GPIO)
P2[1] ( GPIO)
P2[0] ( GPIO)
P15[5] ( GPIO)
95
94
93
92
91
P2[4] ( GPIO, TRA CE DA TA[0])
P2[3] ( GPIO, TRA CE CL K])
P2[2] ( GPIO)
98
97
96
54
53
52
51
P0[0] (GPIO , OpAmp2 out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] ( GPIO, kHz XTAL: Xi)
P15[2] ( GPIO, kHz XTAL: Xo)
P12[1] (SIO , I2C1 : SDA)
P12[0] (SIO , I2C1 : SCL)
P3[7] (GPIO)
P3[6] (GPIO)
( GPIO) P 3[5]
Vd di o3
47
48
49
50
43
44
45
46
( GPIO) P 3[0]
( GPIO) P 3[1]
( Extref1, GPIO) P 3[2]
( GPIO) P 3[3]
( GPIO) P 3[4]
32
33
34
35
59
58
57
56
55
( GPIO) P 5[5]
( GPIO) P 5[6]
( GPIO) P 5[7]
[5] (USBIO, D+, SWDIO) P1 5[6]
[5] ( US BIO, D-, SWDCK) P1 5[7]
24
25
P0[2] (GPIO , OpAmp0 +)
P0[1] (GPIO , OpAmp0 out)
62
61
60
26
27
28
29
30
31
( TDI, GPIO) P1[4]
( nTRST, GPIO) P1[5]
TQFP
Vd di o1
( TCK, SWDCK, GPIO) P1[1]
( configurable XRES, GPIO) P1[2]
( TDO, SWV , GPIO) P1[3]
17
18
19
20
21
22
23
( GPIO) P5[2]
( GPIO) P5[3]
( TMS, SWDIO, GPIO) P1[0]
73
72
71
64
63
(MHz XTAL: Xo, GPIO) P1 5[0]
( MHz XTAL: Xi, GPIO) P1 5[1]
Vssd
XRES
( GPIO) P5[0]
( GPIO) P5[1]
Vddio0
P0[3] (GPIO , OpAmp0-/ Extref0)
68
67
66
65
NC
NC
Vssb
Ind
Vboost
Vbat
75
74
70
69
36
37
38
39
40
41
42
( GPIO) P6[5]
( GPIO) P6[6]
( GPIO) P6[7]
5
6
7
8
9
10
11
12
13
14
15
16
Lines show Vddio
to I/O supply
association
V ddd
Vssd
Vccd
(I2C0 : SCL, SIO ) P 12[4]
(I2C0 : SDA , SIO ) P 12[5]
( GPIO) P6[4]
1
2
3
4
( GPIO) P 1[6]
( GPIO) P 1[7]
(SIO) P1 2[6]
(SIO) P1 2[7]
( GPIO) P 5[4]
( TRACEDATA[1] , GPIO) P2[5]
( TRACEDATA[2] , GPIO) P2[6]
( TRACEDATA[3] , GPIO) P2[7]
100
99
Vddio2
Figure 2-3. 100-pin TQFP Part Pinout
Note
5. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
Document Number: 001-55035 Rev. *G
Page 7 of 102
[+] Feedback
PRELIMINARY
Figure 2-4 and Figure 2-5 show an example schematic and an
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
PSoC® 5: CY8C53 Family Datasheet
on page 23. The trace between the two VCCD pins should be
as short as possible.
 The two pins labeled VSSD must be connected together.
 The two pins labeled VDDD must be connected together.
 The two pins labeled VCCD must be connected together, with
capacitance added, as shown in Figure 2-4 and Power System
Figure 2-4. Example Schematic for 100-pin TQFP Part with Power Connections
Vddd
Vddd
C1
1 uF
Vddd
C2
0.1 uF
U2
CY8C55xx
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vssd
Vssd
Vddd
C12
0.1 uF
Vccd
Vddd
C15
1 uF
C16
0.1 uF
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C8
0.1 uF
C17
1 uF
Vssd
Vssd
Vssd
Vdda
Vssa
Vcca
Vssa
Vdda
C9
1 uF
C10
0.1 uF
Vssa
Vddd
C11
0.1 uF
C13
10 uF, 6.3 V
Vssa
Vdda
Vddd
Vddio0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0out, P0[1]
OA2out, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
kHzXin, P15[3]
kHzXout, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3out, P3[7]
OA1out, P3[6]
Vddio1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
Vddd
Vssd
Vccd
NC
NC
P15[0], MHzXout
P15[1], MHzXin
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
Vddio3
Vssd
Vssd
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P32 47
48
49
50
Vssd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vssd
Vddio2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
Vddd
Vssd
Vccd
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
Vssd
Vddd
100
99
98
97
96
95
94
93
92
91
90
89
Vddd
88
Vssd
87
86
85
84
83
82
81
80
79
78
77
76
Vccd
C6
0.1 uF
C14
0.1 uF Vssd
Vssa
Vssd
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-5.
Document Number: 001-55035 Rev. *G
Page 8 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 2-5. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
Vssa
Vddd
Vdda
Vssa
Plane
Vssd
Plane
3. Pin Descriptions
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
IDAC0, IDAC2. Low resistance output pin for high current DACs
(IDAC).
OpAmp0out, OpAmp2out. High current output of uncommitted
opamp[6].
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp.
OpAmp0+, OpAmp2+. Noninverting
opamp.
Vssd
input
to
uncommitted
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense[6].
I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3
TRACEDATA pins.
TRACEPORT
connection,
I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
TRACEDATA[3:0]. Cortex-M3
output data.
Ind. Inductor connection to boost pump.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are No Connect (NC) on devices without
USB.[3]
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
TRACEPORT
clocks
connections,
SWV. Single Wire Viewer output.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are No Connect (NC) on devices without
USB.[3]
VBOOST. Power sense connection to boost pump.
VBAT. Battery supply to boost pump.
Note
6. GPIOs with opamp outputs are not recommended for use with CapSense
Document Number: 001-55035 Rev. *G
Page 9 of 102
[+] Feedback
PRELIMINARY
VCCA. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to VSSA. Regulator output not for
external use.
PSoC® 5: CY8C53 Family Datasheet
VSSD. Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each
VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),
and must be less than or equal to VDDA. If the I/O pins associated
with Vddio0, Vddio2 or Vddio3 are not used then that VDDIO
should be tied to ground (VSSD or VSSA).
VCCD. Output of digital core regulator and input to digital core.
The two VCCD pins must be shorted together, with the trace
between them as short as possible, and a 1 µF capacitor to VSSD;
see Power System on page 23. Regulator output not for external
use.
XRES (and configurable XRES). External reset pin. Active low
with internal pullup. In 48-pin SSOP parts, P1[2] is configured as
XRES. In all other parts the pin is configured as a GPIO.
VDDA. Supply for all analog peripherals and analog core
regulator. VDDA must be the highest voltage present on the
device. All other supply pins must be less than or equal to
VDDA.
4. CPU
VDDD. Supply for all digital peripherals and digital core regulator.
VDDD must be less than or equal to VDDA.
4.1 ARM Cortex-M3 CPU
The CY8C53 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
VSSA. Ground for all analog peripherals.
VSSB. Ground connection for boost pump.
Figure 4-1. ARM Cortex-M3 Block Diagram
Interrupt Inputs
Nested
Vectored
Interrupt
Controller
(NVIC)
I- Bus
JTAG/SWD
D-Bus
Embedded
Trace Module
(ETM)
Instrumentation
Trace Module
(ITM)
S-Bus
Trace Pins:
Debug Block
(Serial and
JTAG)
Flash Patch
and Breakpoint
(FPB)
Trace Port
5 for TRACEPORT or
Interface Unit 1 for SWV mode
(TPIU)
Cortex M3 Wrapper
C-Bus
AHB
32 KB
SRAM
Data
Watchpoint and
Trace (DWT)
Cortex M3 CPU Core
AHB
Bus
Matrix
Bus
Matrix
Cache
256 KB
ECC
Flash
AHB
32 KB
SRAM
Bus
Matrix
AHB Bridge & Bus Matrix
DMA
PHUB
AHB Spokes
GPIO &
EMIF
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
Document Number: 001-55035 Rev. *G
Page 10 of 102
[+] Feedback
PRELIMINARY
The Cortex-M3 CPU subsystem includes these features:
 ARM Cortex-M3 CPU
 Programmable NVIC, tightly integrated with the CPU core
 Full-featured debug and trace modules, tightly integrated with
the CPU core
 Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB
of SRAM
PSoC® 5: CY8C53 Family Datasheet
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
 Cache controller
 Peripheral HUB (PHUB)
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
 DMA controller
Table 4-2. Cortex M3 CPU Registers
Register
 External memory interface (EMIF)
R0-R12
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
 4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
 Low Registers: Registers R0-R7 are acces-
sible by all instructions that specify a general
purpose register.
 The Thumb®-2 instruction set, which offers ARM-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
 Bit-field control
 Hardware multiply and divide
 Saturation
 If-Then
 Wait for events and interrupts
 Exclusive access and barrier
 Special register access
The Cortex-M3 does not support ARM instructions.
Description
 High Registers: Registers R8-R12 are acces-
sible by all 32-bit instructions that specify a
general purpose register; they are not accessible by all 16-bit instructions.
R13
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
R14
R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
R15
R15 is the Program Counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
xPSR
 Extensive interrupt and system exception support.
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
4.1.2 Cortex-M3 Operating Modes
 Application Program Status Register (APSR)
 Bit-band support. Atomic bit-level write and read operations.
 Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
 Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
Table 4-1. Operational Level
Condition
Privileged
 Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
 Execution Program Status Register (EPSR)
User
Running an exception Handler mode
Not used
Running main program Thread mode
Thread mode
Document Number: 001-55035 Rev. *G
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
Page 11 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 4-2. Cortex M3 CPU Registers (continued)
Register
PRIMASK
Description
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
BASEPRI
CONTROL
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode, 
1 = user level in thread mode.
Bit 1: 0 = default stack (MSP) is used, 
1 = alternate stack is used. If in thread mode or
user level then the alternate stack is the PSP.
There is no alternate stack for handler mode; the
bit must be 0 while in handler mode.
4.2 Cache Controller
The CY8C53 family has a 1 KB instruction cache between the
CPU and the flash memory. This improves instruction execution
rate and reduces system power consumption by requiring less
frequent flash access.
Table 4-3. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, CAN, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
4.3.2 DMA Features
 24 DMA channels
 Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
 TDs can be dynamically updated
 Eight levels of priority per channel
 Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
 Each channel can generate up to two interrupts per transfer
4.3 DMA and PHUB
 Transactions can be stalled or canceled
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
 Supports transaction size of infinite or 1 to 64k bytes
 A central hub that includes the DMA controller, arbiter, and
 TDs may be nested and/or chained for complex transactions
router
 Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.3.1 PHUB Features
 CPU and DMA controller are both bus masters to the PHUB
 Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
 Simultaneous CPU and DMA access to peripherals located on
different spokes
 Simultaneous DMA source and destination burst transactions
on different spokes
 Supports 8-, 16-, 24-, and 32-bit addressing and data
Document Number: 001-55035 Rev. *G
 Large transactions may be broken into smaller bursts of 1 to
127 bytes
4.3.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in Table 4-4 after the CPU and DMA priority levels 0 and 1 have
satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
Page 12 of 102
[+] Feedback
PRELIMINARY
Table 4-4. Priority Levels
PSoC® 5: CY8C53 Family Datasheet
4.3.4.6 Scatter Gather DMA
Priority Level
0
1
% Bus Bandwidth
100.0
100.0
2
3
4
5
6
7
50.0
25.0
12.5
6.2
3.1
1.5
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.3.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location).
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I2C slave where an address is received by the external
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
Document Number: 001-55035 Rev. *G
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Page 13 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Exception
Number
1
2
3
Reset
NMI
Hard fault
–3 (highest)
–2
–1
Exception Table
Address Offset
0x00
0x04
0x08
0x0C
4
MemManage
Programmable
0x10
5
Bus fault
Programmable
0x14
6
Usage fault
Programmable
0x18
7 – 10
11
12
13
14
15
16 – 47
–
SVC
Debug monitor
–
PendSV
SYSTICK
IRQ
–
Programmable
Programmable
–
Programmable
Programmable
Programmable
0x1C – 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40 – 0x3FC
Exception Type
Priority
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 42.
The NVIC handles interrupts from the peripherals, and passes
the interrupt vectors to the CPU. It is closely integrated with the
CPU for low latency interrupt handling. Features include:
 32 interrupts. Multiple sources for each interrupt.
 Configurable number of priority levels: from 3 to 8.
 Dynamic reprioritization of interrupts.
 Priority grouping. This allows selection of preempting and non
preempting interrupt levels.
Document Number: 001-55035 Rev. *G
Function
Starting value of R13 / MSP
Reset
Non maskable interrupt
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
Memory management fault, for example, instruction
fetch from a nonexecutable region
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
Typically caused by invalid instructions or trying to
switch to ARM mode
Reserved
System service call via SVC instruction
Debug monitor
Reserved
Deferred request for system service
System tick timer
Peripheral interrupt request #0 - #31
 Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
 Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Page 14 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 4-6. Interrupt Vector Table
Interrupt #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Cortex-M3 Exception #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Document Number: 001-55035 Rev. *G
Fixed Function
Low voltage detect (LVD)
Cache/ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I2C
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
USB Bus Int
USB Endpoint[0]
USB Endpoint Data
Reserved
Reserved
Reserved
Decimator Int
phub_err_int
eeprom_fault_int
DMA
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
Page 15 of 102
[+] Feedback
PRELIMINARY
5. Memory
5.1 Static RAM
CY8C53 static RAM (SRAM) is used for temporary data storage.
Code can be executed at full speed from the portion of SRAM
that is located in the code space. This process is slower from
SRAM above 0x20000000. The device provides up to 64 KB of
SRAM. The CPU or the DMA controller can access all of SRAM.
The SRAM can be accessed simultaneously by the Cortex-M3
CPU and the DMA controller if accessing different 32-KB blocks.
PSoC® 5: CY8C53 Family Datasheet
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
External read
5.2 Flash Program Memory
Field Upgrade Internal read and write
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
256 KB of user program space.
External read and
write
Full Protection Internal read
External read and
write + internal write
Up to an additional 32 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected. The flash output is 9 bytes wide with 8 bytes of data
and 1 byte of ECC data.
The CPU or DMA controller read both user code and bulk data
located in flash through the cache controller. This provides
higher CPU performance. If ECC is enabled, the cache controller
also performs error checking and correction. Flash programming
is performed through a special interface and preempts code
execution out of flash. Code execution out of cache may
continue during flash programming as long as that code is
contained inside the cache.
The flash programming interface performs flash erasing,
programming and setting code protection levels. Flash In
System Serial Programming (ISSP), typically used for production
programming, is possible through both the SWD and JTAG
interfaces. In-system programming, typically used for
bootloaders, is also possible using serial interfaces such as I2C,
USB, UART, and SPI, or any communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security” section on page 57). For more information on
Document Number: 001-55035 Rev. *G
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C53 has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into two sections, each containing 64 rows
of 16 bytes each.
The CPU can not execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
5.5 External Memory Interface
CY8C53 provides an EMIF for connecting to external memory
devices. The connection allows read and write accesses to
external memories. The EMIF operates in conjunction with
UDBs, I/O ports, and other hardware to generate external
memory address and control signals. At 33 MHz, each memory
access cycle takes four bus clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C53 only
supports one type of external memory device at a time.
Page 16 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
External memory is located in the Cortex-M3 external RAM space; it can use up to 24 address bits. See Memory Map on page 18.
The memory can be 8 or 16 bits wide. Cortex-M3 instructions can be fetched/executed from external memory, although at a slower
rate than from flash.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Document Number: 001-55035 Rev. *G
Page 17 of 102
[+] Feedback
PRELIMINARY
5.6 Memory Map
Table 5-3. Peripheral Data Address Map (continued)
The Cortex-M3 has a fixed address map, which allows
peripherals to be accessed by simple memory access
instructions.
5.6.1 Address Map
The 4-GB address space is divided into the ranges shown in
Table 5-2:
Table 5-2. Address Map
Address Range
0x00000000 –
0x1FFFFFFF
0x20000000 –
0x3FFFFFFF
PSoC® 5: CY8C53 Family Datasheet
Size
Use
0.5 GB
Program code. This includes
the exception vector table at
power up, which starts at
address 0.
0.5 GB
Static RAM. This includes a 1
MByte bit-band region
starting at 0x20000000 and a
32 Mbyte bit-band alias
region starting at
0x22000000.
0x40000000 –
0x5FFFFFFF
0.5 GB
Peripherals. This includes a 1
MByte bit-band region
starting at 0x40000000 and a
32 Mbyte bit-band alias
region starting at
0x42000000.
0x60000000 –
0x9FFFFFFF
1 GB
External RAM.
0xA0000000 –
0xDFFFFFFF
1 GB
External peripherals.
0xE0000000 –
0xFFFFFFFF
0.5 GB
Internal peripherals, including
the NVIC and debug and
trace modules.
Table 5-3. Peripheral Data Address Map
Address Range
Purpose
0x00000000 – 0x0003FFFF 256K Flash
0x1FFF8000 – 0x1FFFFFFF 32K SRAM in Code region
0x20000000 – 0x20007FFF 32K SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF Flash programming interface
0x40004800 – 0x400048FF Cache controller
Document Number: 001-55035 Rev. *G
Address Range
0x40004900 – 0x400049FF
Purpose
I 2C
controller
0x40004E00 – 0x40004EFF Decimator
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
0x40005000 – 0x400051FF I/O ports control
0x40005400 – 0x400054FF External Memory Interface
(EMIF) control registers
0x40005800 – 0x40005FFF Analog Subsystem Interface
0x40006000 – 0x400060FF USB Controller
0x40006400 – 0x40006FFF UDB Configuration
0x40007000 – 0x40007FFF PHUB Configuration
0x40008000 – 0x400087FF EEPROM
0x4000A000 – 0x4000A400 CAN
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
0x48000000 – 0x48007FFF Flash ECC Bytes
0x60000000 – 0x60FFFFFF External Memory Interface
(EMIF)
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
including NVIC, debug, and trace
The bit-band feature allows individual bits in words in the
bit-band region to be read or written as atomic operations. This
is done by reading or writing bit 0 of corresponding words in the
bit-band alias region. For example, to set bit 3 in the word at
address 0x20000000, write a 1 to address 0x2200000C. To test
the value of that bit, read address 0x2200000C and the result is
either 0 or 1 depending on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.6.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0 - 0x1FFFFFFF.
The system bus is used for data accesses and debug accesses
within the ranges 0x20000000 – 0xDFFFFFFF and 0xE0100000
– 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 – 0x3FFFFFFF, although these can be
slower than instruction fetches via the ICode bus.
The private peripheral bus (PPB) is used within the Cortex-M3 to
access system control registers and debug and trace module
registers.
Page 18 of 102
[+] Feedback
PRELIMINARY
6. System Integration
PSoC® 5: CY8C53 Family Datasheet
Key features of the clocking system include:
 Seven general purpose clock sources
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 80-MHz clock, accurate to ±1% over voltage
and temperature. Additional internal and external clock sources
allow each design to optimize accuracy, power, and cost. All of
the system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
the user wants, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent PSoC.
3- to 74-MHz IMO, ±1% at 3 MHz
4- to 33-MHz external crystal oscillator (MHzECO)
 Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 22
 DSI signal from an external I/O pin or other logic
 24- to 80-MHz fractional PLL sourced from IMO, MHzECO,
or DSI
 Clock doubler
 1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
 32.768-kHz external crystal oscillator (kHzECO) for RTC


 IMO has a USB mode that auto locks to USB bus clock requiring
no external crystal for USB. (USB equipped parts only)
 Independently sourced clock dividers in all clocks
 Eight 16-bit clock dividers for the digital system
 Four 16-bit clock dividers for the analog system
 Dedicated 16-bit divider for the CPU bus and CPU clock
 Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
Fmin
Tolerance at Fmin
Fmax
Tolerance at Fmax
Startup Time
IMO
3 MHz
±1% over voltage and temperature
74 MHz
±7%
10 µs max
MHzECO
4 MHz
Crystal dependent
33 MHz
Crystal dependent
5 ms typ, max is
crystal dependent
DSI
0 MHz
Input dependent
66 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
80 MHz
Input dependent
250 µs max
Doubler
12 MHz
Input dependent
48 MHz
Input dependent
1 µs max
ILO
1 kHz
–50%, +100%
100 kHz
-55%, +100%
15 ms max in lowest
power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
500 ms typ, max is
crystal dependent
Document Number: 001-55035 Rev. *G
Page 19 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 6-1. Clocking Subsystem
3-74 MHz
IMO
4-33 MHz
ECO
External IO
or DSI
0-66 MHz
32 kHz ECO
1,33,100 kHz
ILO
12-48 MHz
Doubler
CPU
Clock
24-80 MHz
PLL
System
Clock Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked Loop)
The IMO provides clock outputs at 3-, 6-, 12-, 24-, 48-, and
74-MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
Document Number: 001-55035 Rev. *G
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 80 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1-kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
Page 20 of 102
[+] Feedback
PRELIMINARY
The central timewheel is a 1-kHz, free-running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a low
power mode. Firmware can reset the central timewheel.
The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use the RTC capability instead of the central timewheel.
The 100-kHz clock (CLK100K) works as a low-power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel.
PSoC® 5: CY8C53 Family Datasheet
6.1.2.2 32.768 kHz ECO
The 32.768-kHz external crystal oscillator (32kHzECO) provides
precision timing with minimal power consumption using an
external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Figure 6-3. 32kHzECO Block Diagram
The fast timewheel is a 100 kHz, 5-bit counter clocked by the ILO
that can also be used to wake the system. The fast timewheel
settings are programmable, and the counter automatically resets
when the terminal count is reached. This enables flexible,
periodic wakeups of the CPU at a higher rate than is allowed
using the central timewheel. The fast timewheel can generate an
optional interrupt each time the terminal count is reached.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 33 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
Phase-Locked Loop on page 20). The GPIO pins connecting to
the external crystal and capacitors are fixed. MHzECO accuracy
depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 33 MHz
Crystal Osc
Xi
(Pin P15[1])
External
Components
XCLK_MHZ
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
Xo
(Pin P15[0])
4 – 33 MHz
crystal
Capacitors
Document Number: 001-55035 Rev. *G
Page 21 of 102
[+] Feedback
PRELIMINARY
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
 The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
 Bus clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
 Eight fully programmable 16-bit clock dividers generate digital
PSoC® 5: CY8C53 Family Datasheet
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the UDBs and fixed function timer/counter/PWMs can
also generate clocks.
 Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as the ADC. The
analog clock dividers include skew control to ensure that critical
analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Document Number: 001-55035 Rev. *G
Page 22 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and Vddiox, respectively. It also
includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output
pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD
pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system
also contains a sleep regulator, an I2C regulator, and a hibernate regulator.
Figure 6-4. PSoC Power System
Vddd
1 µF
Vddio2
Vddd
I/O Supply
Vssd
Vccd
Vddio2
Vddio0
0.1 µF
0.1 µF
I/O Supply
Vddio0
0.1 µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
Vdda
Vdda
Digital
Regulators
Vssd
Vcca
Analog
Regulator
0.1 µF
1 µF
.
Vssa
Analog
Domain
0.1µF
I/O Supply
Vddio3
Vddd
Vssd
I/O Supply
Vccd
Vddio1
Hibernate
Regulator
0.1 µF
0.1 µF
Vddio1
Vddd
Vddio3
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-5.
6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
 Active
 Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-5 illustrates the allowable transitions
between power modes.
 Sleep
 Hibernate
Document Number: 001-55035 Rev. *G
Page 23 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 6-2. Power Modes
Power Modes
Description
Entry Condition
Wakeup
Source
Any interrupt
Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset,
peripherals available
manual register
(programmable)
entry
Any (programmable) All regulators available.
Digital and analog
regulators can be
disabled if external
regulation used.
Alternate
Active
Similar to Active mode, and is Manual register
typically configured to have
entry
fewer peripherals active to
reduce power. One possible
configuration is to turn off the
CPU and flash, and run
peripherals at full speed
Any interrupt
Sleep
All subsystems automatically
disabled 
Manual register
entry
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed. 
Digital and analog
regulators can be
disabled if external
regulation used.
Hibernate
All subsystems automatically
disabled 
Lowest power consuming
mode with all peripherals and
internal regulators disabled,
except hibernate regulator is
enabled
Configuration and memory
contents retained
Manual register
entry
PICU
Only hibernate regulator
active.
Any (programmable) All regulators available.
Digital and analog
regulators can be
disabled if external
regulation used.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(Typ)
Code
Digital
Execution Resources
Analog
Resources
Clock Sources Available
Active
–
2 mA[7]
Yes
All
All
All
–
All
Alternate
Active
–
TBD
User
defined
All
All
All
–
All
No
I 2C
Comparator ILO/kHzECO
Comparator, PICU,
XRES, LVD,
I2C, RTC, CTW, LVD WDR
No
None
None
PICU
Sleep
<15 µs
Hibernate <100 µs
2 µA
300 nA
Document Number: 001-55035 Rev. *G
None
Wakeup Sources
Reset Sources
XRES
Page 24 of 102
[+] Feedback
PRELIMINARY
Figure 6-5. Power Mode Transitions
6.2.1.5 Wakeup Events
Active
Manual
Sleep
PSoC® 5: CY8C53 Family Datasheet
Hibernate
Buzz
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Interrupt sources include internally generated interrupts,
power supervisor, central timewheel, and I/O interrupts. Internal
interrupt sources can come from a variety of peripherals, such
as analog comparators and UDBs. The central timewheel
provides periodic interrupts to allow the system to wake up, poll
peripherals, or perform real-time functions. Reset event sources
include the external reset I/O pin (XRES), WDT, and Precision
Reset (PRES).
6.2.2 Boost Converter
Alternate
Active
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
Applications that use a supply voltage of less than 1.71 V, such
as solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
0.5 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage from 0.5 V to 5.5 V
(VBAT), and can start up with VBAT as low as 0.5 V. The converter
provides a user configurable output voltage of 1.8 to 5.0 V
(VBOOST). VBAT is typically less than VBOOST; if VBAT is greater
than or equal to VBOOST, then VBOOST will be the same as VBAT.
The block can deliver up to 50 mA (IBOOST) depending on
configuration.
Four pins are associated with the boost converter: VBAT, VSSB,
VBOOST, and Ind. The boosted output voltage is sensed at the
VBOOST pin and must be connected directly to the chip’s supply
inputs. An inductor is connected between the VBAT and Ind pins.
The designer can optimize the inductor value to increase the
boost converter efficiency based on input voltage, output
voltage, current and switching frequency. The External Schottky
diode shown in Figure 6-6 is required only in cases when
VBOOST>3.6 V.
Figure 6-6. Application for Boost Converter
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
Vboost Vdda Vddd
Optional Schottky
Diode. Only
required when Vdd
>3.6 V.
IND
22
µF
PSoC
0.1
µF
10 µH
22
µF
Vbat
Vssb
Vssa
Vssd
Note
7. IMO 6 MHz, CPU 6 MHz, all peripherals disabled
Document Number: 001-55035 Rev. *G
Page 25 of 102
[+] Feedback
PRELIMINARY
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low power, low current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption. Table 6-4 lists the boost power modes
available in different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Chip -Active mode
Chip -Sleep mode
Chip-Hibernate mode
Boost Power Modes
Boost can be operated in either active or
standby mode.
Boost can be operated in either active or
standby mode. However, it is recommended to operate boost in standby
mode for low power consumption
Boost can only be operated in active
mode. However, it is recommended not to
use boost in chip hibernate mode due to
high current consumption in boost active
mode
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,
or 32 kHz to optimize efficiency and component cost. The
100 kHz, 400 kHz, and 2 MHz switching frequencies are
generated using oscillators internal to the boost converter block.
When the 32 kHz switching frequency is selected, the clock is
derived from a 32 kHz external crystal oscillator. The 32 kHz
external clock is primarily intended for boost standby mode.
If the boost converter is not used in a given application, tie the
VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin
unconnected.
6.3 Reset
CY8C53 has multiple internal and external reset sources
available. The reset sources are:
 Power source monitoring - The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
 External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to Vddio1. VDDD, VDDA, and Vddio1 must all
have voltage applied before the part comes out of reset.
 Watchdog timer - A watchdog timer monitors the execution of
PSoC® 5: CY8C53 Family Datasheet
Figure 6-7. Resets
Vddd Vdda
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
 IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages VDDD
and VDDA, both directly at the pins and at the outputs of the
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the
voltage is high enough for PRES to release, the IMO starts.
 PRES - Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
 Software - The device can be reset under program control.
Document Number: 001-55035 Rev. *G
Page 26 of 102
[+] Feedback
PRELIMINARY
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
services and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
 ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when VDDA and VDDD
go outside a voltage range. For AHVI, VDDA is compared to a
fixed trip level. For ALVI and DLVI, VDDA and VDDD are
compared to trip levels that are programmable, as listed in
Table 6-5. ALVI and DLVI can also be configured to generate
a device reset instead of an interrupt.
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Interrupt Supply
Normal
Voltage
Range
Available Trip Accuracy
Settings
DLVI
VDDD
1.71 V-5.5 V 1.70 V-5.45 V in
250 mV
increments
±2%
ALVI
VDDA
1.71 V-5.5 V 1.70 V-5.45 V in
250 mV
increments
±2%
AHVI
VDDA
1.71 V-5.5 V 5.75 V
±2%
6.3.1.2 Other Reset Sources
 XRES - External Reset
CY8C53 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
The external reset is active low. It includes an internal pull-up
resistor. XRES is active during sleep and hibernate modes.
 SRES - Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
 DRES - Digital Logic Reset
A logic signal can be routed from the UDBs or other digital
peripheral source through the DSI to the Configurable XRES
pin, P1[2], to generate a hardware-controlled reset. The pin
must be placed in XRES mode. The response to a DRES is the
same as after an IPOR reset.
 WRES - Watchdog Timer Reset
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be
serviced.
Document Number: 001-55035 Rev. *G
PSoC® 5: CY8C53 Family Datasheet
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power on reset event.
Page 27 of 102
[+] Feedback
PRELIMINARY
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both General Purpose I/O (GPIO) and
Special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense[6], and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
 Features supported by both GPIO and SIO:
User programmable port reset state
 Separate I/O supplies and voltages for up to four groups of I/O
 Digital peripherals use DSI to connect the pins
 Input or output or both for CPU and DMA
 Eight drive modes
 Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
 Dedicated port interrupt vector for each port
 Slew rate controlled digital output drive mode

Document Number: 001-55035 Rev. *G
PSoC® 5: CY8C53 Family Datasheet
Access port control and configuration registers on either port
basis or pin basis
 Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
 Special functionality on a pin by pin basis

 Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices
CapSense on CapSense equipped devices[6]
 Analog input and output capability
 Continuous 100 µA clamp current capability
 Standard drive strength down to 1.71 V


 Additional features only provided on SIO pins:
Higher drive strength than GPIO
Hot swap capability (5 V tolerance at any operating VDD)
 Programmable and regulated high input and output drive
levels down to 1.2 V
 No analog input or LCD capability
 Over voltage tolerance up to 5.5 V
 SIO can act as a general purpose analog comparator


 USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
 Input, output, or both for CPU and DMA
 Input, output, or both for digital peripherals
 Digital output (CMOS) drive mode
 Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges


Page 28 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 6-8. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
Digital System Output
In
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
Capsense Global Control
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-55035 Rev. *G
5
Page 29 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
Driver
Vhigh
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SYNC_OUT
D+ pin only
USBIO_CR1[7]
USB or I/O
USB SIE Control for USB Mode
USBIO_CR1[4,5]
Digital System Output
PRT[x]BYP
Vddd
0
1
In
Drive
Logic
Vddd
5k
Vddd Vddd
1.5 k
PIN
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
Document Number: 001-55035 Rev. *G
D+ 1.5 k
D+D- 5 k
Open Drain
Page 30 of 102
[+] Feedback
PRELIMINARY
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-11 depicts a simplified pin view based on
each of the eight drive modes. Table 6-6 shows the I/O pin’s drive
state based on the port data register value or digital array signal
PSoC® 5: CY8C53 Family Datasheet
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
Pin
1. High Impedance
Digital
DR
PS
Pin
2. Resistive
Pull-Up
Vddio
DR
PS
Pin
4. Open Drain,
Drives Low
DR
PS
Vddio
DR
PS
3. Resistive
Pull-Down
Vddio
Pin
5. Open Drain,
Drives High
DR
PS
Vddio
Pin
6. Strong Drive
Pin
DR
PS
Pin
7. Resistive
Pull-Up and Pull-Down
Table 6-6. Drive Modes
Diagram
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedence analog
Drive Mode
0
0
0
High-Z
High-Z
1
High Impedance digital
0
0
1
High-Z
High-Z
2
Resistive pull-up[8]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[8]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High-Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High-Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[8]
1
1
1
Res High (5K)
Res Low (5K)
 High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
 High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Note
8. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-55035 Rev. *G
Page 31 of 102
[+] Feedback
PRELIMINARY
 Resistive pull-up or resistive pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull-up and pull-down
are not available with SIO in regulated output mode.
 Open drain, drives high and open drain, drives low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
 Strong drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
 Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pull-up and pull-down are not
available with SIO in regulated output mode.
PSoC® 5: CY8C53 Family Datasheet
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.2 Pin Registers
6.4.7 I/O Power Supplies
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature allows
users to provide different I/O voltage levels for different pins on
the device. Refer to the specific device package pinout to
determine VDDIO capability for a given port and pin.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
6.4.3 Bidirectional Mode
High speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRTxDM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRTxSLW registers.
Document Number: 001-55035 Rev. *G
The SIO port pins support an additional regulated high output
capability, as described in Adjustable Output Level.
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DACs or uncommitted
opamps.
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders[6]. See the
“CapSense” section on page 54 for more information.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 53 for details.
Page 32 of 102
[+] Feedback
PRELIMINARY
6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to output
either the standard VDDIO level or the regulated output, which is
based on an internally generated reference. Typically a voltage
DAC (VDAC) is used to generate the reference. The “DAC”
section on page 54 has more details on VDAC use and reference
routing to the SIO pins. Resistive pull-up and pull-down drive
modes are not available with SIO in regulated output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO. The
reference sets the pins voltage threshold for a high logic level.
Available input thresholds are:
 0.5 ×VDDIO
 0.4 ×VDDIO
 0.5 ×VREF
 VREF
Typically a voltage DAC (VDAC) generates the VREF reference.
“DAC” section on page 54 has more details on VDAC use and
reference routing to the SIO pins.
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in Figure 6-9 on page 30 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (VDDIO < VIN < VDDA)
tolerance feature at any operating VDD.
 There are no current limitations for the SIO pins as they present
PSoC® 5: CY8C53 Family Datasheet
 The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply.
 In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8 V, and
an external device could run from 5 V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated VDDIO supply
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull-down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull-down or pull-up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
6.4.17 Low Power Functionality
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in “Pinouts” on page 5. The special
features are:
 Digital
4- to 33-MHz crystal oscillator
32.768-kHz crystal oscillator
2
 Wake from sleep on I C address match. Any pin can be used
2
for I C if wake from sleep is not required.
 JTAG interface pins
 SWD interface pins
 SWV interface pins
 External reset


 Analog
Opamp inputs and outputs
High current IDAC outputs
 External reference inputs


6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
pins for board level test.
a high impedance load to the external circuit.
Document Number: 001-55035 Rev. *G
Page 33 of 102
[+] Feedback
PRELIMINARY
 Universal Digital Block Array - UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
 Digital System Interconnect (DSI) - Digital signals from UDBs,
fixed function peripherals, I/O pins, interrupts, DMA, and other
system core signals are attached to the Digital System
Interconnect to implement full featured device connectivity. The
DSI allows any digital function to any pin or other feature
routability when used with the Universal Digital Block Array.
IO Port
 Universal Digital Blocks (UDB) - These form the core
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
IO Port
DSI Routing Interface
IO Port
The main components of the digital programmable system are:
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
DSI Routing Interface
UDB Array
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture.
Designers do not need to interact directly with the programmable
digital system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
Digital Core System
and Fixed Function Peripherals
UDB Array
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
Figure 7-1. CY8C53 Digital Programmable Architecture
IO Port
7. Digital Subsystem
PSoC® 5: CY8C53 Family Datasheet
Digital Core System
and Fixed Function Peripherals
7.1 Example Peripherals
The flexibility of the CY8C53 family’s UDBs and analog blocks
allow the user to create a wide range of components
(peripherals). The most common peripherals were built and
characterized by Cypress and are shown in the PSoC Creator
component catalog, however, users may also create their own
custom components using PSoC Creator. Using PSoC Creator,
users may also create their own components for reuse within
their organization, for example sensor interfaces, proprietary
algorithms, and display interfaces.
The number of components available through PSoC Creator is
too numerous to list in the datasheet, and the list is always
growing. An example of a component available for use in
CY8C53 family, but, not explicitly called out in this datasheet is
the UART component.
Document Number: 001-55035 Rev. *G
Page 34 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
7.1.1 Example Digital Components
7.1.3 Example System Function Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C53 family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
The following is a sample of the system function components
available in PSoC Creator for the CY8C53 family. The exact
amount of hardware resources (UDBs, SC/CT blocks, routing,
RAM, flash) used by a component varies with the features
selected in PSoC Creator for the component.
 Communications
 CapSense
I2C (1 to 3 UDBs)
 UART (1 to 3 UDBs)

 Functions

EMIF (External Memory Interface, 1 UDB)
 Logic (x CPLD product terms per logic function)
NOT
 OR
 XOR
 AND

7.1.2 Example Analog Components
The following is a sample of the analog components available in
PSoC Creator for the CY8C53 family. The exact amount of
hardware resources (SC/CT blocks, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
 Amplifiers
TIA
PGA
 opamp


 ADC

Successive Approximation (SAR)
 DACs
 LCD Drive
 LCD Control
 Filters
7.1.4 Designing with PSoC Creator
7.1.4.1 More Than a Typical IDE
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
Current
Voltage
 PWM


 Comparators
 Mixers
Document Number: 001-55035 Rev. *G
Page 35 of 102
[+] Feedback
PRELIMINARY
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
PSoC® 5: CY8C53 Family Datasheet
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
Figure 7-2. PSoC Creator Framework
Document Number: 001-55035 Rev. *G
Page 36 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
7.1.4.2 Component Catalog
7.1.4.4 Software Development
Figure 7-3. Component Catalog
Figure 7-4. Code Editor
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADC, DACs, and filters, and
communication protocols, such as I2C, USB and CAN. See
“Example Peripherals” section on page 34 for more details about
available peripherals. All content is fully characterized and
carefully documented in datasheets with code examples, AC/DC
specifications, and user code ready APIs.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
7.1.4.5 Nonintrusive Debugging
Figure 7-5. PSoC Creator Debugger
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion.
Breakpoints and code execution commands are all readily
available from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and
peripherals—make for an unparalleled level of visibility into the
system.
Document Number: 001-55035 Rev. *G
Page 37 of 102
[+] Feedback
PRELIMINARY
 Clock and Reset Module - This block provides the UDB clocks
and reset selection and control.
7.2.1 PLD Module
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, look up tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
PT4
PT5
PT6
PT7
Figure 7-7. PLD 12C4 Structure
PT3
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
provide a way for CPU firmware to interact and synchronize
with UDB operation.
PT2
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
 Status and Control Module - The primary role of this block is to
PT1
7.2 Universal Digital Block
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
PT0
PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
PSoC® 5: CY8C53 Family Datasheet
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
Figure 7-6. UDB Block Diagram
PLD
Chaining
Clock
and Reset
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Status and
Control
Datapath
Datapath
Chaining
SELIN
(carry in)
OUT0
MC0
T
T
T
T
T
T
T
T
OUT1
MC1
T
T
T
T
T
T
T
T
OUT2
MC2
T
T
T
T
T
T
T
T
OUT3
MC3
T
T
T
T
T
T
T
T
SELOUT
(carry out)
Routing Channel
The main component blocks of the UDB are:
 PLD blocks - There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
 Datapath Module - This 8-bit wide datapath contains structured
AND
Array
OR
Array
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V 10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
logic to implement a dynamically configurable ALU, a variety
Document Number: 001-55035 Rev. *G
Page 38 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
Figure 7-8. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
6
F0
A0
A1
D0
D1
D1
Data Registers
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
Input
Muxes
Datapath Control
Input from
Programmable
Routing
Control Store RAM
8 Word X 16 Bit
FIFOs
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.6 Working Registers
7.2.2.7 Dynamic Datapath Configuration RAM
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
x 16-bit configuration RAM, which stores eight unique 16-bit wide
configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumulators or ALU. Each FIFO is four
bytes deep.
Document Number: 001-55035 Rev. *G
ALU
The ALU performs eight general purpose functions. They are:
 Increment
 Decrement
 Add
 Subtract
 Logical AND
Page 39 of 102
[+] Feedback
PRELIMINARY
 Logical OR
 Logical XOR
 Pass, used to pass a value through the ALU to the shift register,
PSoC® 5: CY8C53 Family Datasheet
Figure 7-9. Example FIFO Configurations
System Bus
System Bus
mask, or another UDB register
Independent of the ALU operation, these functions are available:
F0
F0
F1
D0
A0
D1
A1
 Shift left
 Shift right
 Nibble swap
 Bitwise OR mask
D0/D1
A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
F1
F0
F1
7.2.2.8 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.9 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.10 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic
Redundancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
7.2.2.11 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Document Number: 001-55035 Rev. *G
System Bus
System Bus
TX/RX
Dual Capture
Dual Buffer
7.2.2.12 Chaining
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
7.2.2.13 Time Multiplexing
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.14 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Page 40 of 102
[+] Feedback
PRELIMINARY
Figure 7-10. Status and Control Registers
System Bus
PSoC® 5: CY8C53 Family Datasheet
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Figure 7-11. Digital System Interface Structure 
8-bit Status Register
(Read Only)
8-bit Control Register
(Write/Read)
System Connections
HV
B
Routing Channel
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
HV
A
UDB
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
HV
B
HV
A
HV
B
HV
A
7.2.3.15 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
UDB
UDB
HV
A
UDB
HV
B
UDB
HV
A
HV
B
System Connections
7.2.3.16 Clock Generation
7.3.1 UDB Array Programmable Resources
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
Figure 7-12 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
7.3 UDB Array Description
Figure 7-11 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
Document Number: 001-55035 Rev. *G
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Page 41 of 102
[+] Feedback
PRELIMINARY
Figure 7-12. Function Mapping Example in a Bank of UDBs
8-Bit
Timer
UDB
Sequencer
Quadrature Decoder
UDB
HV
A
16-Bit
PWM
HV
B
Figure 7-13. Digital System Interconnect
Timer
Counters
16-Bit PYRS
UDB
PSoC® 5: CY8C53 Family Datasheet
CAN
Interrupt
Controller
I2C
DMA
Controller
IO Port
Pins
IO Port
Pins
UDB
HV
A
HV
B
Digital System Routing I/F
UDB
UDB
UDB
8-Bit
Timer Logic
UDB
8-Bit SPI
I2C Slave
12-Bit SPI
UDB
UDB
HV
B
UDB ARRAY
UDB
HV
A
UDB
HV
B
Digital System Routing I/F
HV
A
Logic
UDB
UDB
UART
UDB
UDB
12-Bit PWM
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Global
Clocks
Global
Clocks
SC
Blocks
DACS
Figure 7-14. Interrupt and DMA Processing in the IDMUX 
Interrupt and DMA Processing in IDMUX
Fixed Function IRQs
0
 DMA requests from all digital peripherals in the system.
1
IRQs
 Digital peripheral data signals that need flexible routing to I/Os.
UDB Array
 Digital peripheral data signals that need connections to UDBs.
 Connections to the interrupt and DMA controllers.
2
Edge
Detect
3
DMA termout (IRQs)
0
Fixed Function DRQs
1
Edge
Detect
Document Number: 001-55035 Rev. *G
Interrupt
Controller
DRQs
 Connection to I/O pins.
 Connection to analog system digital signals.
Comparators
Interrupt and DMA routing is very flexible in the CY8C53
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-14 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
Signals in this category include:
 Interrupt requests from all digital peripherals in the system.
SAR
ADC
EMIF
DMA
Controller
2
Page 42 of 102
[+] Feedback
PRELIMINARY
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
PSoC® 5: CY8C53 Family Datasheet
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
UDB Array Digital System Interface
Figure 7-15. I/O Pin Synchronization Routing
DO
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
DI
Port i
Figure 7-16. I/O Pin Output Connectivity 
7.5 CAN
8 IO Data Output Connections from the
UDB Array Digital System Interface
DO
PIN 0
DO
PIN1
DO
PIN2
DO
PIN3
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B
specifications as defined in the Bosch specification and
conforms to the ISO-11898-1 standard. The CAN protocol was
originally designed for automotive applications with a focus on a
high level of fault detection. This ensures high communication
reliability at a low cost. Because of its success in automotive
applications, CAN is used as a standard communication protocol
for motion oriented machine control networks (CANOpen) and
factory automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
Port i
Document Number: 001-55035 Rev. *G
Page 43 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 7-18. CAN Bus System Implementation
CAN Node 1
CAN Node 2
CAN Node n
PSoC
CAN
Drivers
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H
CAN_L
CAN_H
CAN_L
CAN_H
CAN_L
CAN Bus
7.5.1 CAN Features
 CAN2.0A/B protocol implementation - ISO 11898 compliant
Standard and extended frames with up to 8 bytes of data per
frame
 Message filter capabilities
 Remote Transmission Request (RTR) support
 Programmable bit rate up to 1 Mbps

 Listen Only mode
 SW readable error counter and indicator
 Sleep mode: Wake the device from sleep with activity on the
Rx pin
 Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
 Enhanced interrupt controller
CAN receive and transmit buffers status
 CAN controller error status including BusOff

 Receive path
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that
covers the ID, IDE and RTR
 DeviceNet addressing support
 Multiple receive buffers linkable to build a larger receive
message array
 Automatic transmission request (RTR) response handler
 Lost received message notification


 Transmit path
Eight transmit buffers
Programmable transmit priority
• Round robin
• Fixed priority
 Message transmissions abort capability


7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
 CAN Configuration walkthrough with bit timing analyzer
 Receive filter setup
Document Number: 001-55035 Rev. *G
Page 44 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 7-19. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
Tx Buffer
Status
TxReq
Pending
TxMessage1
TxReq
TxAbort
Bit Timing
Priority
Arbiter
TxMessage6
TxReq
TxAbort
TxInterrupt
Request
(if enabled)
TxMessage7
TxReq
TxAbort
RxInterrupt
Request
(if enabled)
RxMessage0
Acceptance Code 0
Acceptance Mask 0
RxMessage1
Acceptance Code 1
Acceptance Mask 1
RxMessage
Handler
RxMessage14
Acceptance Code 14
Acceptance Mask 14
RxMessage15
Acceptance Code 15
Acceptance Mask 15
ErrInterrupt
Request
(if enabled)
7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. The maximum data payload
size is 64 bytes for control, interrupt, and bulk endpoints and
1023 bytes for isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
Routing” section on page 28.
 Three memory modes
Manual Memory Management with No DMA Access
 Manual Memory Management with Manual DMA Access
 Automatic Memory Management with Automatic DMA
Access

CRC Check
WakeUp
Request
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
 Interrupts on bus and each endpoint event, with device wakeup
 USB Reset, Suspend, and Resume operations
 Bus powered and self powered modes
Figure 7-20. USB
Arbiter
System Bus
 Dedicated 8-byte buffer for EP0
Rx
requiring no external crystal for USB (USB equipped parts only)
 Eight unidirectional data endpoints
 Shared 512-byte buffer for the eight data endpoints
Rx
CAN
Framer
 Internal 48 MHz oscillator that auto locks to USB bus clock,
USB includes the following features:
 One bidirectional control endpoint 0 (EP0)
Tx
CRC
Generator
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RTR RxMessages
0-15
Rx Buffer
Status
RxMessage
Available
Tx
CAN
Framer
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
Interrupts
External 22 
Resistors
USB
I/O
D–
48 MHz
IMO
 Internal 3.3 V regulator for transceiver
Document Number: 001-55035 Rev. *G
Page 45 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
7.7 Timers, Counters, and PWMs
7.8 I2C
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows designers to choose the timer, counter, and
PWM features that they require. The tool set utilizes the most
optimal resources available.
The I2C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I2C serial
communication bus. The bus is compliant with Philips ‘The I2C
Specification’ version 2.1. Additional I2C interfaces can be
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
 16-bit Timer/Counter/PWM (down count only)
I2C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from low
power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to the
two special sets of SIO pins.
 Selectable clock source
I2C features include:
 PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
 Slave and Master, Transmitter, and Receiver operation
 Period reload on start, reset, and terminal count
 Byte processing for low CPU overhead
 Interrupt on terminal count, compare true, or capture
 Interrupt or polling CPU interface
 Dynamic counter reads
 Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
 Timer capture mode
 7 or 10-bit addressing (10-bit addressing requires firmware
Timer/Counter/PWM features include:
 Count while enable signal is asserted mode
support)
 SMBus operation (through firmware support - SMBus
 Free run mode
supported in hardware in UDBs)
 One Shot mode (stop at end of period)
 Complementary PWM outputs with deadband
 PWM output kill
 7-bit hardware address compare
 Wake from low power modes on address match
Figure 7-21. Timer/Counter/PWM
Clock
Reset
Enable
Capture
Kill
Timer / Counter /
PWM 16-bit
Document Number: 001-55035 Rev. *G
IRQ
TC / Compare!
Compare
Page 46 of 102
[+] Feedback
PRELIMINARY
8. Analog Subsystem
PSoC® 5: CY8C53 Family Datasheet
 Four comparators with optional connection to configurable LUT
outputs
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
 Two configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
 Two opamps for internal use and connection to GPIO that can
be used as high current output buffers
 Flexible, configurable analog routing architecture provided by
 CapSense subsystem to enable capacitive touch sensing
analog globals, analog mux bus, and analog local buses
 Precision reference for generating an accurate analog voltage
 Successive approximation (SAR) ADC
for internal analog blocks
 Two 8-bit DACs that provide either voltage or current output
Figure 8-1. Analog Subsystem Block Diagram
SAR
ADC
DAC
R
O
U
T
I
N
G
S C /C T B lo c k
S C /C T B lo c k
R
O
U
T
I
N
G
Op
Amp
G P IO
P o rt
A
N
A
L
O
G
P re cisio n
R e fe re n ce
DAC
Op
Amp
A
N
A
L
O
G
C o m p a ra to rs
CMP
CMP
CMP
G P IO
P o rt
CMP
C a p S e n s e S u b s y s te m
A n a lo g
In te rfa c e
DSI
A rra y
The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and also connections from one
analog resource to another. PSoC Creator also provides
component libraries that allow you to configure the various
Document Number: 001-55035 Rev. *G
C lo c k
D istrib u tio n
C o n fig &
S ta tu s
R e g iste rs
PHUB
CPU
D e cim a to r
analog blocks to perform application specific functions (PGA,
transimpedance amplifier, voltage DAC, current DAC, and so
on). The tool also generates API interface libraries that allow you
to write firmware that allows the communication between the
analog peripheral and CPU/Memory.
Page 47 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
8.1 Analog Routing
8.1.2 Functional Description
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
8.1.1 Features
 Flexible, configurable analog routing architecture
 16 Analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
 Each GPIO is connected to one analog global and one analog
mux bus
 8 Analog local buses (abus) to route signals between the
different analog blocks
 Multiplexers and switches for input and output selection of the
analog blocks
Document Number: 001-55035 Rev. *G
Page 48 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 8-2. CY8C53 Analog Interconnect
*
*
*
*
swfol
*
GPIO
P3[5]
GPIO
P3[4]
GPIO
P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
*P15[1]
GPXT
*P15[0]
3210 76543210
swinn
*
in0
swout
abuf_vref_int
(1.024V)
i2
refbufl_
cmp
cmp0_vref
(1.024V)
+
- comp2
CAPSENSE
out
ref
in refbufl
refsel[1:0]
sc0
Vin
Vref
out
vssa
sc0_bgref
(1.024V)
refbufr
out
ref
in
i1
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
sc1
Vin
Vref
out
SC/CT
Vssa
sc1_bgref
(1.024V)
v2
DAC2
i2
USB IO
* P15[6]
36
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
*P1[7]
GPIO
*P1[6]
dac_vref (0.256V)
CY8C55 only
Vp (+)
Vn (-) SAR0
Vrefhi_out
refs
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
SAR ADC
ExVrefL1
refmux[2:0]
ExVrefL2
refmux[2:0]
CY8C55 only
CY8C55 only
01 23456 7 0123
3210 76543210
*
13
*
Vbat
XRES
Vssb
Vssd
Ind
Vboost
*
Document Number: 001-55035 Rev. *G
*
Large ( ~200 Ohms)
*
Switch Resistance
Small ( ~870 Ohms )
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
*
Notes:
* Denotes pins on all packages
LCD signals are not shown.
AGR[0]
AMUXBUSR
AGR[3]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
AGL[3]
AGL[2]
AGL[1]
AGL[0]
AMUXBUSL
Vddio1
AGR[3]
AGR[2]
AGR[1]
LPF
*
*
Connection
VBE
Vss ref
*
*
Mux Group
Switch Group
TS
ADC
*
AGL[1]
AGL[2]
AGL[3]
:
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
*
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
*
AMUXBUSL
Vdda
Vdda/2
en_resvda
*
en_resvda
Vddd
* P15[7]
VIDAC
Vdda
Vdda/2
Vssd
USB IO
v0
DAC0
i0
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
Vccd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
ABUSL0
ABUSL1
ABUSL2
ABUSL3
*
*
Vddio2
+
-
*
*
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
comp3
90
i3
cmp0_vref
(1.024V)
AGR[4]
AMUXBUSR
bg_vda_swabusl0
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
Vssd
ExVrefR
comp1 +
-
cmp1_vref
Vdda
Vdda/2
Vccd
swout
swin
COMPARATOR
cmp_muxvn[1:0]
vref_cmp1
(0.256V)
bg_vda_res_en
out1
AGR[7]
AGR[6]
AGR[5]
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
in1
5
comp0
+
cmp1_vref
*
LPF
out0
swin
refbufr_
cmp
i0
cmp1_vref
*
*
01 2 3 4 56 7 0123
swfol
*
*
AGL[6]
AGL[7]
44
*
*
*
*
AGL[4]
AGL[5]
*
*
ExVrefL2
opamp2
*
*
AGR[6]
AGR[7]
AGL[7]
opamp0
*
AGR[4]
AGR[5]
AGL[4]
AGL[5]
AGL[6]
ExVrefL
ExVrefL1
*
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
AMUXBUSL
Vssd
AMUXBUSR
AMUXBUSL
swinp
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
Vcca
Vssa
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinp
swinn
Rev #51
2-April-2010
Page 49 of 102
[+] Feedback
PRELIMINARY
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C38,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
8.2 Successive Approximation ADC
The CY8C53 family of devices has a Successive Approximation
(SAR) ADC. This ADC is 12-bit at up to 1 Msps, with
single-ended or differential inputs, making it useful for a wide
variety of sampling and control applications.
8.2.1 Functional Description
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure 8-3.
Figure 8-3. SAR ADC Block Diagram
PSoC® 5: CY8C53 Family Datasheet
8.2.2 Conversion Signals
Writing a start bit or assertion of a Start of Frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
When the conversion is complete, a status bit is set and the
output signal End of Frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.2.3 Operational Modes
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
8.3 Comparators
The CY8C53 family of devices contains four comparators.
Comparators have these features:
 Input offset factory trimmed to less than 5 mV
 Rail-to-rail common mode input range (VSSA to VCCA)
vrefp
vrefn
S/H
DAC
array
D0:D11
vin
comparator
SAR
digital
D0:D11
power
filtering
modes: fast, slow, or ultra low power
 Comparator outputs can be routed to look up tables to perform
autozero
reset
clock
clock
POWER
GROUND
 Speed and power can be traded off by using one of three
vrefp
vrefn
simple logic functions and then can also be routed to digital
blocks
 The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
 Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
8.3.1 Input and Output Interface
The input is connected to the analog globals and muxes. The
frequency of the clock is 16 times the sample rate; the maximum
clock rate is 16 MHz.
Document Number: 001-55035 Rev. *G
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Page 50 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 8-4. Analog Comparator
From
Analog
Routing
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
_
+
_
comp3
+
_
From
Analog
Routing
From
Analog
Routing
comp2
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
4
LUT3
UDBs
8.3.2 LUT
The CY8C53 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-1.
Document Number: 001-55035 Rev. *G
Table 8-1. LUT Function vs. Program Word and Inputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
A OR B
A NOR B
A XNOR B
NOT B
A OR (NOT B)
1100b
1101b
1110b
1111b
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
Page 51 of 102
[+] Feedback
PRELIMINARY
8.4 Opamps
The CY8C53 family of devices contain two general purpose
opamps.
Figure 8-5. Opamp
GPIO
PSoC® 5: CY8C53 Family Datasheet
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.5 Programmable SC/CT Blocks
Analog
Global Bus
Opamp
Analog
Global Bus
VREF
Analog
Internal Bus
GPIO
=
GPIO
Analog Switch
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
See Figure 8-6. In any configuration, the input and output signals
can all be connected to the internal global signals and monitored
with an ADC, or comparator. The configurations are
implemented with switches between the signals and GPIO pins.
The CY8C53 family of devices contains two switched
capacitor/continuous time (SC/CT) blocks in a device. Each
switched capacitor/continuous time block is built around a single
rail-to-rail high bandwidth opamp.
Switched capacitor is a circuit design technique that uses
capacitors plus switches instead of resistors to create analog
functions. These circuits work by moving charge between
capacitors by opening and closing different switches.
Nonoverlapping in phase clock signals control the switches, so
that not all switches are ON simultaneously.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, VREF connection, and so on.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
Figure 8-6. Opamp Configurations
a) Voltage Follower
The opamp and resistor array is programmable to perform
various analog functions including
 Naked Operational Amplifier - Continuous Mode
Opamp
Vout to Pin
Vin
 Unity-Gain Buffer - Continuous Mode
 Programmable Gain Amplifier (PGA) - Continuous Mode
 Transimpedance Amplifier (TIA) - Continuous Mode
 Up/Down Mixer - Continuous Mode
b) External Uncommitted
Opamp
 Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
 First Order Analog to Digital Modulator - Switched Cap Mode
Opamp
Vout to GPIO
Vp to GPIO
Vn to GPIO
8.5.1 Naked Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
8.5.2 Unity Gain
c) Internal Uncommitted
Opamp
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
Vn
To Internal Signals
8.5.3 PGA
Opamp
Vout to Pin
Vp
GPIO Pin
Document Number: 001-55035 Rev. *G
The PGA amplifies an external or internal signal. The PGA can
be configured to operate in inverting mode or noninverting mode.
The PGA function may be configured for both positive and
negative gains as high as 50 and 49 respectively. The gain is
adjusted by changing the values of R1 and R2 as illustrated in
Figure 8-7. The schematic in Figure 8-7 shows the configuration
Page 52 of 102
[+] Feedback
PRELIMINARY
and possible resistor settings for the PGA. The gain is switched
from inverting and non inverting by changing the shared select
value of the both the input muxes. The bandwidth for each gain
case is listed in Table 8-2.
PSoC® 5: CY8C53 Family Datasheet
Figure 8-8. Continuous Time TIA Schematic
R fb
Table 8-2. Bandwidth
Gain
Bandwidth
1
6.0 MHz
24
340 kHz
48
220 kHz
50
215 kHz
I in
V out
V ref
Figure 8-7. PGA Resistor Settings
Vin
0
Vref
1
R1
20 k or 40 k
R2
20 k to 980 k
S
The TIA configuration is used for applications where an external
sensor's output is current as a function of some type of stimulus
such as temperature, light, magnetic flux etc. In a common
application, the voltage DAC output can be connected to the
VREF TIA input to allow calibration of the external sensor bias
current by adjusting the voltage DAC output voltage.
8.6 LCD Direct Drive
Vref
0
Vin
1
The PGA is used in applications where the input signal may not
be large enough to achieve the desired resolution in the ADC, or
dynamic range of another SC/CT block such as a mixer. The gain
is adjustable at runtime, including changing the gain of the PGA
prior to each ADC sample.
8.5.4 TIA
The Transimpedance Amplifier (TIA) converts an internal or
external current to an output voltage. The TIA uses an internal
feedback resistor in a continuous time configuration to convert
input current to output voltage. For an input current Iin, the output
voltage is Iin x Rfb +VREF, where VREF is the value placed on the
non inverting input. The feedback resistor Rfb is programmable
between 20 K and 1 M through a configuration register.
Table 8-3 shows the possible values of Rfb and associated
configuration settings.
Table 8-3. Feedback Resistor Settings
Configuration Word
Nominal Rfb (K)
000b
20
001b
30
010b
40
011b
60
100b
120
101b
250
110b
500
111b
1000
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C53 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
Key features of the PSoC LCD segment system are:
 LCD panel direct driving
 Type A (standard) and Type B (low power) waveform support
 Wide operating voltage range support (2 V to 5 V) for LCD
panels
 Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
 Internal bias voltage generation through internal resistor ladder
 Up to 62 total common and segment outputs
 Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
 Up to 62 front plane/segment outputs for direct drive
 Drives up to 736 total segments (16 backplane x 46 front plane)
 Up to 64 levels of software controlled contrast
 Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
 Adjustable LCD refresh rate from 10 Hz to 150 Hz
Document Number: 001-55035 Rev. *G
Page 53 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
 Ability to invert LCD display for negative image
8.6.4 LCD DAC
 Three LCD driver drive modes, allowing power optimization
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
 LCD driver configurable to be active when PSoC is in limited
active mode
Figure 8-9. LCD System
Global
Clock
UDB
LCD Driver
Block
DMA
8.7 CapSense
LCD
DAC
PIN
Display
RAM
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in the CapSense component in PSoC
Creator.
A capacitive sensing method using a Delta-Sigma Modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
8.8 Temp Sensor
PHUB
8.6.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.6.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
8.9 DAC
The CY8C53 parts contain two Digital to Analog Convertors
(DACs). Each DAC is 8-bit and can be configured for either
voltage or current output. The DACs support CapSense, power
supply regulation, and waveform generation. Each DAC has the
following features.
 Adjustable voltage or current output in 255 steps
 Programmable step size (range selection)
 Eight bits of calibration to correct ± 25% of gain error
 Source and sink option for current output
 8 Msps conversion rate for current output
 1 Msps conversion rate for voltage output
 Monotonic in nature
8.6.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
Document Number: 001-55035 Rev. *G
Page 54 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 8-10. DAC Block Diagram
I source Range
1x , 8x , 64x
Reference
Source
Vout
Scaler
Iout
R
3R
I sink Range
1x , 8x , 64x
8.9.1 Current DAC
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be
configured to source or sink current.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
8.9.2 Voltage DAC
Figure 8-11. Mixer Configuration
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
C2 = 1.7 pF
C1 = 850 fF
Rmix 0 20 k or 40 k
8.10 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local
Document Number: 001-55035 Rev. *G
sc_clk
Rmix 0 20 k or 40 k
Vin
0
Vref
Vout
1
sc_clk
Page 55 of 102
[+] Feedback
PRELIMINARY
8.11 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I).
Vi
C1
C2
1
n
1
2
9. Programming, Debug Interfaces,
Resources
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
 JTAG or SWD access
Figure 8-12. Sample and Hold Topology 
(1 and 2 are opposite phases of a clock)
1
PSoC® 5: CY8C53 Family Datasheet
 Flash Patch and Breakpoint (FPB) block for implementing
breakpoints and code patches
 Data Watchpoint and Trigger (DWT) block for implementing
V ref
V out
2
2
watchpoints, trigger resources, and system profiling
 Embedded Trace Macrocell (ETM) for instruction trace
 Instrumentation Trace Macrocell (ITM) for support of printf-style
debugging
1
2
1
1
V ref
2
C3
C4
2
Vref
8.11.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
8.11.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors.
The main application for this modulator is for a low frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement
Document Number: 001-55035 Rev. *G
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Four interfaces are available: JTAG, SWD, SWV, and
TRACEPORT. JTAG and SWD support all programming and
debug features of the device. JTAG also supports standard JTAG
scan chains for board level test and chaining multiple JTAG
devices for programming or testing. The SWV and TRACEPORT
provide trace output from the DWT, ETM, and ITM.
TRACEPORT is faster but uses more pins. SWV is slower but
uses only one pin.
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Page 56 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
9.1 JTAG Interface
9.4 Trace Features
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit
transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,
whichever is least. By default, the JTAG pins are enabled on new
devices but the JTAG interface can be disabled, allowing these
pins to be used as General Purpose I/O (GPIO) instead. The
JTAG interface is used for programming the flash memory,
debugging, I/O scan chains, and JTAG device chaining.
The following trace features are supported:
9.2 SWD Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
 Instruction trace
 Data watchpoint on access to data address, address range, or
data value
 Trace trigger on data watchpoint
 Debug exception trigger
 Code profiling
 Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
 Interrupt events trace
 Software event monitoring, “printf-style” debugging
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D- pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
9.5 SWV and TRACEPORT Interfaces
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Table 9-1. Debug Configurations
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in Table 9-1.
Debug and Trace Configuration
All debug and trace disabled
GPIO Pins Used
0
JTAG
4 or 5
SWD
2
9.3 Debug Features
SWV
1
The CY8C53 supports the following debug features:
TRACEPORT
 Halt and single-step the CPU
JTAG + TRACEPORT
 View and change CPU and peripheral registers, and RAM
SWD + SWV
3
SWD + TRACEPORT
7
addresses
5
9 or 10
 Six program address breakpoints and two literal access
breakpoints
 Data watchpoint events to CPU
 Patch and remap instruction from flash to SRAM
 Debugging at the full speed of the CPU
 Debug operations are possible while the device is reset, or in
low power modes
 Compatible with PSoC Creator and MiniProg3 programmer and
debugger
 Standard JTAG programming and debugging interfaces make
CY8C53 compatible with other popular third-party tools (for
example, ARM / Keil)
Document Number: 001-55035 Rev. *G
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL).
Page 57 of 102
[+] Feedback
PRELIMINARY
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0x50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security”
section on page 16). However, after setting the values in the
WOL, a user still has access to the part until it is reset. Therefore,
a user can write the key into the WOL, program the flash
protection data, and then reset the part to lock it.
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out via Serial Wire Debug
(SWD) port to electrically identify protected parts. The user can
write the key in WOL to lock out external access only if no flash
protection is set. For more information on how to take full
advantage of the security features in PSoC see the PSoC 5
TRM.
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Document Number: 001-55035 Rev. *G
PSoC® 5: CY8C53 Family Datasheet
10. Development Support
The CY8C53 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
10.1 Documentation
A suite of documentation, to ensure that you can find answers to
your questions quickly, supports the CY8C53 family. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: PSoC Creator makes designing
with PSoC as easy as dragging a peripheral onto a schematic,
but, when low level details of the PSoC device are required, use
the technical reference manual (TRM) as your guide.
Note Visit www.arm.com for detailed documentation about the
Cortex-M3 CPU.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C53 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Page 58 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11. Electrical Specifications
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC
Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example
Peripherals” section on page 34 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Higher storage temperatures
reduce NVL data retention time.
Recommended storage temperature is +25 °C ±25 °C. Extended
duration storage temperatures
above 85 °C degrade reliability.
–55
25
100
°C
Analog supply voltage relative to
VSSA
–0.5
–
6
V
VDDD
Digital supply voltage relative to
VSSD
–0.5
–
6
V
VDDIO
I/O supply voltage relative to VSSD
–0.5
–
6
V
VCCA
Direct analog core voltage input
–0.5
–
1.95
V
VCCD
Direct digital core voltage input
–0.5
–
1.95
V
VSSA
Analog ground voltage
VSSD – 0.5
–
VSSD +
0.5
V
VGPIO[9]
DC input voltage on GPIO
Includes signals sourced by VDDA
and routed internal to the pin.
VSSD – 0.5
–
VDDIO +
0.5
V
VSIO
DC input voltage on SIO
Output disabled
VSSD – 0.5
–
7
V
Output enabled
VSSD – 0.5
–
6
V
0.5
–
5.5
V
VSSD – 0.5
–
5.5
V
TSTG
Storage temperature
VDDA
VIND
Voltage at boost converter input
VBAT
Boost converter supply
Ivddio
Current per VDDIO supply pin
–
–
100
mA
ESDHBM
Electrostatic discharge voltage
Human body model
2200
–
–
V
ESDCDM
ESD voltage
Charge device model
500
–
–
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Note
9. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO  VDDA.
Document Number: 001-55035 Rev. *G
Page 59 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.2 Device Level Specifications
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
Description
VDDA
Analog supply voltage and input to
analog core regulator
VDDA
Analog supply voltage, analog
regulator bypassed
VDDD
Digital supply voltage relative to
VSSD
Digital supply voltage, digital
VDDD
regulator bypassed
VDDIO[10]
VCCA
VCCD
VBAT
IDD[11]
Conditions
Analog core regulator enabled
Min
1.8
Typ
–
Max
5.5
Units
V
Analog core regulator disabled
1.71
1.8
1.89
V
Digital core regulator enabled
1.8
–
VDDA
V
Digital core regulator disabled
1.71
1.8
1.89
V
I/O supply voltage relative to VSSIO
Direct analog core voltage input
Analog core regulator disabled
(Analog regulator bypass)
1.71
1.71
–
1.8
VDDA
1.89
V
V
Direct digital core voltage input
Digital core regulator disabled
(Digital regulator bypass)
Voltage supplied to boost converter
Active Mode, VDD = 1.71 V – 5.5 V
T = –40 °C
Execute from Flash cache, see
Cache Controller on page 12 and
T = 25 °C
Flash Program Memory on page 16
T = 85 °C
[12]
Sleep Mode
VDD = VDDIO = 4.5–5.5 V T = –40 °C
CPU = OFF
RTC = ON (= ECO32K ON, in low
T = 25 °C
power mode)
T = 85 °C
Sleep timer = ON (= ILO ON at
1 kHz)[13]
VDD = VDDIO = 2.7–3.6 V T = –40 °C
WDT = OFF
T = 25 °C
I2C Wake = OFF
T = 85 °C
Comparator = OFF
POR = ON
VDD = VDDIO = 1.71–1.95 V T = –40 °C
Boost = OFF
T = 25 °C
SIO pins in single ended input,
T = 85 °C
unregulated output mode
1.71
1.8
1.89
V
0.5
–
5.5
V
–
–
–
–
2
–
–
–
–
mA
mA
mA
–
–
–
–
–
–
–
–
–
–
–
–
–
2
–
–
–
–
–
–
–
–
–
–
–
–
–
µA
µA
µA
µA
µA
µA
µA
µA
µA
–
–
–
µA
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7–3.6V
T = 25 °C
Notes
10. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO  VDDA.
11. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets
12. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
13. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Document Number: 001-55035 Rev. *G
Page 60 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-2. DC Specifications (continued)
Parameter
Description
I2C Wake = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
Conditions
VDD = VDDIO = 2.7–3.6V
T = 25 °C
Min
–
Typ
–
Max
–
Units
µA
T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
–
–
–
–
–
nA
nA
nA
T = –40 °C
T = 25 °C
T = 85 °C
VDD = VDDIO = 1.71–1.95 V T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
–
–
–
300
–
–
–
–
–
–
–
–
–
–
nA
nA
nA
nA
nA
nA
Hibernate Mode[14]
VDD = VDDIO = 4.5–5.5 V
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7–3.6 V
Table 11-3. AC Specifications[15]
Min
Typ
Max
Units
FCPU
Parameter
CPU frequency
Description
1.71 V  VDDD  5.5 V
Conditions
DC
–
80
MHz
FBUSCLK
Bus frequency
1.71 V  VDDD  5.5 V
DC
–
80
MHz
Svdd
VDD ramp rate
–
–
1
V/ns
TIO_INIT
Time from VDDD/VDDA/VCCD/VCCA
IPOR to I/O ports set to their reset
states
–
–
10
µs
TSTARTUP
Time from VDDD/VDDA/VCCD/VCCA VCCA/VDDA = regulated from
 PRES to CPU executing code at VDDA/VDDD, no PLL used, fast IMO
reset vector
boot mode (48 MHz typ.)
–
–
33
µs
–
–
66
µs
Wakeup from limited active mode – 
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
–
–
12
µs
Wakeup from sleep mode – Occurrence of LVD interrupt to beginning
of execution of next CPU instruction
–
–
15
µs
THIBERNATE Wakeup form hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
–
–
100
µs
VCCA/VCCD = regulated from
VDDA/VDDD, no PLL used, slow IMO
boot mode (12 MHz typ.)
TSLEEP
Notes
14. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
15. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 61 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.3 Power Regulators
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDD
VCCD
Output voltage
Regulator output capacitor
Conditions
±10%, X5R ceramic or better. The two VCCD
pins must be shorted together, with as short
a trace as possible, see Power System on
page 23
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Min
0.5
–
Typ
–
–
Max
5.5
50
Units
V
mA
–
–
75
mA
–
–
30
mA
–
–
20
mA
–
–
15
mA
4.7
10
1
10
22
–
47
47
–
µH
µF
A
20
–
–
V
–
–
–
–
200
12
700
–
–
mA
µA
µA
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDA
VCCA
Output voltage
Regulator output capacitor
Conditions
±10%, X5R ceramic or better
11.3.3 Inductive Boost Regulator
Table 11-6. Inductive Boost Regulator DC Specifications
Parameter
Description
Input voltage
VBAT
IBOOST
LBOOST
CBOOST
IF
VR
ILPK
Load current[16, 17]
Boost inductor
Filter capacitor[18]
External Schottky diode average
forward current
External Schottky diode peak
reverse voltage
Inductor peak current
Quiescent current
Conditions
Includes startup
VIN=1.6–5.5 V, VOUT =1.6–5.0 V, external
diode
VIN=1.6–3.6 V, VOUT =1.6–3.6 V, internal
diode
VIN=0.8–1.6 V, VOUT =1.6–3.6 V, internal
diode
VIN=0.8–1.6 V, VOUT =3.6–5.0 V, external
diode
VIN=0.5–0.8 V, VOUT =1.6–3.6 V, internal
diode
10 µH specified
22 µF || 0.1 µF specified
External Schottky diode is required for
VBOOST > 3.6 V
External Schottky diode is required for
VBOOST > 3.6 V
Boost active mode
Boost standby mode, 32 khz external crystal
oscillator, IBOOST < 1 µA
Notes
16. For output voltages above 3.6 V, an external diode is required.
17. Maximum output current applies for output voltages  4x input voltage.
18. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 62 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-6. Inductive Boost Regulator DC Specifications (continued)
Parameter
VBOOST
Description
Boost output voltage range[19]
1.8 V
1.9 V
2.0 V
2.4 V
2.7 V
3.0 V
3.3 V
3.6 V
5.0 V
Load regulation
Line regulation
Efficiency
Conditions
External diode required
VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 10 mA,
Fsw = 400 kHz
Min
Typ
Max
Units
1.71
1.81
1.90
2.28
2.57
2.85
3.14
3.42
4.75
–
–
90
1.80
1.90
2.00
2.40
2.70
3.00
3.30
3.60
5.00
–
–
–
1.89
2.00
2.10
2.52
2.84
3.15
3.47
3.8
5.25
TBD
TBD
–
V
V
V
V
V
V
V
V
V
%
%
%
Min
–
–
Typ
–
0.1, 0.4,
or 2
Max
100
–
Units
mV
MHz
20
–
80
%
Table 11-7. Inductive Boost Regulator AC Specifications
Parameter
Description
VRIPPLE
Ripple voltage (peak-to-peak)
FSW
Switching frequency
Conditions
VOUT = 1.8 V, FSW = 400 kHz, IOUT = 10 mA
Duty cycle
11.4 Inputs and Outputs
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.4.1 GPIO
Table 11-8. GPIO DC Specifications
Parameter
VIH
VIL
Description
Input voltage high threshold
Input voltage low threshold
Conditions
CMOS Input, PRT[x]CTL = 0
CMOS Input, PRT[x]CTL = 0
VIH
Input voltage high threshold
VIH
Input voltage high threshold
VIL
Input voltage low threshold
VIL
Input voltage low threshold
VOH
Output voltage high
LVTTL Input, PRT[x]CTL = 1,VDDIO 0.7 x VDDIO
< 2.7 V
LVTTL Input, PRT[x]CTL = 1,
2.0
VDDIO  2.7 V
LVTTL Input, PRT[x]CTL = 1,VDDIO
–
< 2.7 V
–
LVTTL Input, PRT[x]CTL = 1,
VDDIO  2.7 V
IOH = 4 mA at 3.3 VDDIO
VDDIO – 0.6
VOL
Output voltage low
Rpullup
Pull-up resistor
IOH = 1 mA at 1.8 VDDIO
IOL = 8 mA at 3.3 VDDIO
IOL = 4 mA at 1.8 VDDIO
Min
0.7  VDDIO
–
VDDIO – 0.5
–
–
4
Typ
–
–
Max
–
0.3 
VDDIO
Units
V
V
–
–
V
–
–
V
–
V
–
0.3 x
VDDIO
0.8
V
–
–
V
–
–
–
5.6
–
0.6
0.6
8
V
V
V
k
Note
19. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 63 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-8. GPIO DC Specifications (continued)
Parameter
Rpulldown
IIL
Description
Pull-down resistor
Conditions
Min
4
Typ
5.6
Max
8
Units
k
Input leakage current (absolute
value)[20]
25°C, VDDIO = 3.0 V
–
–
2
nA
CIN
Input capacitance[20]
GPIOs without opamp outputs
GPIOs with opamp outputs
VH
–
–
40
7
18
–
pF
pF
mV
–
–
100
µA
Rglobal
Input voltage hysteresis
(Schmitt-Trigger)[20]
Current through protection diode to
VDDIO and VSSIO
Resistance pin to analog global bus 25 °C, VDDIO = 3.0 V
–
–
–
Rmux
Resistance pin to analog mux bus 25 °C, VDDIO = 3.0 V
–
–
320
220
–
–


Min
2
2
10
10
Typ
–
–
–
–
Max
12
12
60
60
Units
ns
ns
ns
ns
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
20
MHz
3.3 V < VDDIO < 5.5 V, slow strong 90/10% VDDIO into 25 pF
drive mode
–
–
7
MHz
1.71 V < VDDIO < 3.3 V, slow strong 90/10% VDDIO into 25 pF
drive mode
GPIO input operating frequency
1.71 V < VDDIO < 5.5 V
90/10% VDDIO
–
–
3.5
MHz
–
–
66
MHz
Idiode
Table 11-9. GPIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Fgpioout
Fgpioin
Description
Rise time in Fast Strong Mode[20]
Fall time in Fast Strong Mode[20]
Rise time in Slow Strong Mode[20]
Fall time in Slow Strong Mode[20]
GPIO output operating frequency
3.3 V < VDDIO < 5.5 V, fast strong
drive mode
1.71 V < VDDIO < 3.3 V, fast strong
drive mode
Conditions
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
11.4.2 SIO
Table 11-10. SIO DC Specifications
Parameter
Vinref
Voutref
Description
Conditions
Input voltage reference (Differential
input mode)
Output voltage reference (Regulated output mode)
VDDIO > 3.7
VDDIO < 3.7
Min
0.5
Typ
Max
Units
–
0.52 VDDIO
V
1
1
–
–
VDDIO – 1
VDDIO – 0.5
V
V
VIH
Input voltage high threshold
GPIO mode
Differential input mode
CMOS input
Hysteresis disabled
0.7  VDDIO
Vinref + 0.1
–
–
–
–
V
V
VIL
Input voltage low threshold
GPIO mode
Differential input mode
CMOS input
Hysteresis disabled
–
–
–
–
0.3 VDDIO
Vinref – 0.1
V
V
Note
20. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 64 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-10. SIO DC Specifications (continued)
Parameter
VOH
Description
Output voltage high
Unregulated mode
Regulated mode
Regulated mode
Output voltage low
VOL
Rpullup
Rpulldown
IIL
CIN
VH
Idiode
Pull-up resistor
Pull-down resistor
Input leakage current (absolute
value)[21]
VIH < Vddsio
VIH > Vddsio
Input Capacitance[21]
Input voltage hysteresis
(Schmitt-Trigger)[21]
Conditions
IOH = 4 mA, VDDIO = 3.3 V
Min
Typ
Max
Units
VDDIO – 0.4
–
–
V
Voutref – 0.6
Voutref – 0.25
–
–
Voutref+0.2
Voutref+0.2
V
V
VDDIO = 3.30 V, IOL = 25 mA
VDDIO = 1.80 V, IOL = 4 mA
–
–
4
4
–
–
5.6
5.6
0.8
0.4
8
8
V
V
k
k
25 °C, Vddsio = 3.0 V, VIH = 3.0 V
25 °C, Vddsio = 0 V, VIH = 3.0 V
–
–
–
–
–
–
–
–
–
40
50
–
14
10
7
–
–
100
nA
µA
pF
mV
mV
µA
IOH = 1 mA
IOH = 0.1 mA
Single ended mode (GPIO mode)
Differential mode
Current through protection diode to
VSSIO
Table 11-11. SIO AC Specifications
Parameter
TriseF
Description
Rise time in Fast Strong Mode
(90/10%)[21]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
1
Typ
–
Max
12
Units
ns
TfallF
Fall time in Fast Strong Mode
(90/10%)[21]
Cload = 25 pF, VDDIO = 3.3 V
1
–
12
ns
TriseS
Rise time in Slow Strong Mode
(90/10%)[21]
Fall time in Slow Strong Mode
(90/10%)[21]
Cload = 25 pF, VDDIO = 3.0 V
10
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
10
–
60
ns
TfallS
Note
21. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 65 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-11. SIO AC Specifications (continued)
Parameter
Fsioout
Fsioin
Description
Conditions
SIO output operating frequency
3.3 V < VDDIO < 5.5 V, Unregulated 90/10% VDDIO into 25 pF
output (GPIO) mode, fast strong
drive mode
Min
Typ
Max
Units
–
–
33
MHz
1.71 V < VDDIO < 3.3 V, Unregu90/10% VDDIO into 25 pF
lated output (GPIO) mode, fast
strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated 90/10% VDDIO into 25 pF
output (GPIO) mode, slow strong
drive mode
–
–
16
MHz
–
–
5
MHz
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
–
–
4
MHz
3.3 V < VDDIO < 5.5 V, Regulated Output continuously switching
output mode, fast strong drive mode into 25 pF
–
–
20
MHz
1.71 V < VDDIO < 3.3 V, Regulated
output mode, fast strong drive mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
Output continuously switching
into 25 pF
Output continuously switching
into 25 pF
–
–
10
MHz
–
–
2.5
MHz
90/10% VDDIO
–
–
66
MHz
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Document Number: 001-55035 Rev. *G
90/10% VDDIO into 25 pF
Page 66 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.4.3 USBIO
For operation in USB mode, VDDD range condition is 3.15 V  VDDD  3.45 V (USB regulator bypassed) or 4.35 V  VDDD  5.25 V
(USB regulator in use). For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 60.
Table 11-12. USBIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Rusbi
USB D+ pull-up resistance
With idle bus
0.900
–
1.575
k
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
k
Vohusb
Static output high
15 k ±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 k ±5% to Vss, internal pull-up
enabled
–
–
0.3
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD  3 V
2.4
–
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD  3 V
–
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
Vcm
Differential input common mode range
Vse
Single ended receiver threshold
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
Rext
External USB series resistor
In series with each USB pin
Zo
USB driver output impedance
Including Rext
CIN
IIL
–
–
0.2
V
0.8
–
2.5
V
0.8
–
2
V
3
–
7
k
21.78
(–1%)
22
22.22
(+1%)

28
–
44

USB transceiver input capacitance
–
–
20
pF
Input leakage current (absolute value) 25 °C, VDDD = 3.0 V
–
–
2
nA
Min
12 – 0.25%
Typ
12
Max
12 +
0.25%
Units
MHz
Table 11-13. USBIO AC Specifications
Parameter
Description
Tdrate
Full-speed data rate average bit rate
Conditions
Tjr1
Receiver data jitter tolerance to next
transition
–8
–
8
ns
Tjr2
Receiver data jitter tolerance to pair
transition
Driver differential jitter to next transition
Driver differential jitter to pair transition
Source jitter for differential transition to
SE0 transition
–5
–
5
ns
–3.5
–4
–2
–
–
–
3.5
4
5
ns
ns
ns
160
82
–
–
–
–
175
–
14
ns
ns
ns
–
–
1
4
1
4
–
–
–
–
–
–
20
6
12
40
12
40
MHz
MHz
ns
ns
ns
ns
Tdj1
Tdj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential
transition
Fgpio_out
GPIO mode output operating frequency 3 V  VDDD  5.5 V
VDDD = 1.71 V
Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Tr_gpio
Tf_gpio
Document Number: 001-55035 Rev. *G
Page 67 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-14. USB Driver AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Tr
Transition rise time
4
–
20
ns
Tf
Transition fall time
4
–
20
ns
TR
Rise/fall time matching
90%
–
111%
Vcrs
Output signal crossover voltage
1.3
–
2
V
Min
Typ
Max
Units
11.4.4 XRES
Table 11-15. XRES DC Specifications
Parameter
Description
Conditions
VIH
Input voltage high threshold
CMOS Input, PRT[x]CTL = 0
0.7  VDDIO
–
–
V
VIL
Input voltage low threshold
CMOS Input, PRT[x]CTL = 0
–
–
0.3 
VDDIO
V
Rpullup
Pull-up resistor
4
5.6
8
k
capacitance[22]
CIN
Input
–
3
–
pF
VH
Input voltage hysteresis
(Schmitt-Trigger)[22]
–
100
–
mV
Idiode
Current through protection diode to
VDDIO and VSSIO
–
–
100
µA
Min
Typ
Max
Units
1
–
–
µs
Table 11-16. XRES AC Specifications
Parameter
TRESET
Description
Reset pulse width
Conditions
Note
22. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 68 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5 Analog Peripherals
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 Opamp
Table 11-17. Opamp DC Specifications
Parameter
VIOFF
VIOFF
TCVos
Ge1
VI
VO
IOUT
IOUT
CMRR
Description
Conditions
Input offset voltage
Input offset voltage
T = 25 °C
Input offset voltage drift with temperature
Gain error, unity gain buffer mode
Rload = 1 k
Quiescent current
Input voltage range
Output voltage range
Output load = 1 mA
Output current
Output current
Common mode rejection ratio[23]
Output voltage is between VSSA
+500 mV and VDDA – 500 mV, and
VDDA > 2.7 V
Output voltage is between VSSA
+500 mV and VDDA – 500 mV, and
VDDA > 1.7 V and VDDA < 2.7 V
Min
–
–
–
–
–
VSSA
VSSA + 50
25
Typ
–
0.5
12
–
900
–
–
–
Max
Units
2
mV
–
mV
–
µv/°C
0.1
%
–
µA
VDDA
mV
VDDA – 50 mV
–
mA
16
–
–
mA
70
–
–
dB
Min
3
Typ
–
Max
–
Units
MHz
3
–
–
38
–
–
V/µs
nv/sqrtHz
Table 11-18. Opamp AC Specifications
Parameter
Description
GBW
Gain BW[23]
Tslew
Slew rate[23]
Input noise density[23]
Conditions
100 mV pk-pk, load capacitance
200 pF
Load capacitance 200 pF
11.5.2 Voltage Reference
Table 11-19. Voltage Reference Specifications
Parameter
VREF
Description
Precision reference voltage
Conditions
Initial trimming
Min
Typ
Max
Units
1.023
(–0.1%)
1.024
1.025
(+0.1%)
V
15
ppm/°C
Temperature drift[23]
Long term drift
Thermal cycling drift (stability)[23]
Total
variation[23]
50
ppm/Khr
100
ppm
±1
%
Note
23. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 69 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.3 SAR ADC
Table 11-20. SAR ADC DC Specifications
Parameter
Description
Conditions
Typ
Max
Units
bits
Resolution
–
–
12
Number of channels – single ended
–
–
No of
GPIO
–
–
No of
GPIO/2
Yes
–
–
Number of channels – differential
Differential pair is formed using a
pair of neighboring GPIO.
Monotonicity[24]
Gain error
–
–
±0.1
%
Input offset voltage
–
–
±0.2
mV
Current consumption
–
–
500
µA
Input voltage range – single
ended[24]
VSSA
–
VDDA
V
Input voltage range – differential[24]
VSSA
–
VDDA
V
–
–
2
K
7
8
9
pF
Min
Typ
Max
Units
Input
CIN
Min
resistance[24]
Input capacitance[24]
Table 11-21. SAR ADC AC Specifications
Parameter
Description
Sample & hold
Conditions
droop[24]
–
–
1
µV/µs
PSRR
Power supply rejection ratio[24]
80
–
–
dB
CMRR
Common mode rejection ratio
80
–
–
dB
Sample rate[24]
–
–
1
Msps
Signal-to-noise ratio (SNR)[24]
70
–
–
dB
Input bandwidth[24]
–
500
–
KHz
SNR
INL
Integral non linearity[24]
Internal reference
–
–
±1
LSB
DNL
Differential non linearity[24]
Internal reference
–
–
±1
LSB
–
–
0.005
%
Min
Typ
Max
Units
THD
Total harmonic
distortion[24]
11.5.4 Analog Globals
Table 11-22. Analog Globals AC Specifications
Parameter
Description
Conditions
Rppag
Resistance pin-to-pin through
analog global[25]
VDDA = 3.0 V
–
939
1461

Rppmuxbus
Resistance pin-to-pin through
analog mux bus[25]
VDDA = 3.0 V
–
721
1135

BWag
3 dB bandwidth of analog globals
VDDA = 3.0 V
–
–
2
MHz
CMRRag
Common mode rejection for
differential signals
VDDA = 3.0 V
85
91
–
dB
Notes
24. Based on device characterization (Not production tested).
25. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended.
Document Number: 001-55035 Rev. *G
Page 70 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.5 Comparator
Table 11-23. Comparator DC Specifications
Parameter
VIOFF
Description
Conditions
Min
Typ
Max
Units
Input offset voltage in fast mode
Factory trim
–
–
±2
mV
Input offset voltage in slow mode
Factory trim
–
–
±2
mV
Custom trim
–
–
±2
mV
Input offset voltage in slow mode[26] Custom trim
–
–
±1
mV
VIOFF
Input offset voltage in ultra low
power mode
–
±12
–
mV
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
Fast mode
0
–
VDDA– 0.1
V
0
–
VDDA
V
CMRR
Common mode rejection ratio
50
–
–
dB
ICMP
High current mode/fast mode[27]
–
–
400
µA
Low current mode/slow mode[27]
–
–
100
µA
–
6
–
µA
Min
Typ
Max
Units
VIOFF
Input offset voltage in fast
mode[26]
Slow mode
Ultra low power
mode[27]
Table 11-24. Comparator AC Specifications
Parameter
TRESP
Description
Conditions
Response time, high current
mode[27]
50 mV overdrive, measured
pin-to-pin
–
95
TBD
ns
Response time, low current
mode[27]
50 mV overdrive, measured
pin-to-pin
–
155
TBD
ns
Response time, ultra low power
mode[27]
50 mV overdrive, measured
pin-to-pin
–
55
–
µs
Notes
26. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM.
27. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 71 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.6 IDAC
Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
–
8
–
Code = 255, VDDA  2.7 V, RL
600 
–
2.040
–
mA
Code = 255, VDDA  2.7 V, RL
300 
–
2.040
–
mA
Medium[28]
Code = 255, RL 600 
–
255
–
µA
Low[28]
Code = 255, RL 600 
–
31.875
–
µA
Resolution
IOUT
Units
Output current
High[28]
INL
Integral non linearity
RL 600 , CL=15 pF
–
–
±1
LSB
DNL
Differential non linearity
RL 600 , CL=15 pF
–
–
±0.5
LSB
–
0
±1
LSB
Uncompensated
–
–
3.5
%
Ezs
Zero scale error
Eg
Gain error
Temperature compensated
–
–
TBD
%
IDAC_ICC
DAC current low speed mode[28]
Code = 0
–
–
100
µA
IDAC_ICC
DAC current high speed mode[28]
Code = 0
–
–
500
µA
Min
–
Typ
–
Max
8
Units
Msps
–
–
100
ns
–
–
1000
ns
Table 11-26. IDAC (Current Digital-to-Analog Converter) AC Specifications
Parameter
FDAC
TSETTLE
Description
Update rate
Settling time to 0.5LSB
Fast mode
Slow mode
Conditions
Full scale transition, 600  load, 
CL = 15 pF
Independent of IDAC range setting
(IOUT)
Independent of IDAC range setting
(IOUT)
Note
28. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 72 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.7 VDAC
Table 11-27. VDAC (Voltage Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
–
8
–
Units
Output resistance[29]
ROUT
High
VOUT = 4 V
–
16
–
k
Low
VOUT = 1 V
–
4
–
k
Code = 255, VDDA > 5 V
–
4
–
V
Output voltage range[29]
VOUT
High
Code = 255
–
1
–
V
INL
Integral non linearity
Low
CL=15 pF
–
–
±1
LSB
DNL
Differential non linearity
CL=15 pF
–
–
±1
LSB
Ezs
Zero scale error
–
–
±1
LSB
Eg
Gain error
mode[29]
VDAC_ICC
DAC current low speed
VDAC_ICC
DAC current high speed mode[29]
Uncompensated
–
–
3
%
Temperature compensated
–
–
TBD
%
Code = 0
–
–
100
µA
Code = 0
–
–
500
µA
Min
Typ
Max
Units
Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications
Parameter
FDAC
Description
1 V mode
–
–
1
Msps
Update rate[29]
4 V mode
–
–
250
Ksps
Update
Settling time to
TSETTLE
Conditions
rate[29]
0.5LSB[29]
Full scale transition, CL = 15 pF
High[29]
VOUT = 4 V
–
–
4000
ns
Low[29]
VOUT = 1 V
–
–
1000
ns
11.5.8 Discrete Time Mixer
The discrete time mixer is used for modulating (shifting signals in frequency down) where the output frequency of the mixer is equal
to the difference of the input frequency and the local oscillator frequency. The discrete time mixer is created using a SC/CT analog
block; see the Mixer component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code.
Table 11-29. Discrete Time Mixer DC Specifications
Parameter
Description
Conditions
Analog input noise injection (RMS) 1 MHz clock rate
4 MHz clock rate
Input voltage[30]
Min
Typ.
Max
Units
–
10
–
µV
–
30
–
µV
VSSA
–
VDDA
V
Input offset voltage
–
–
10
mV
Quiescent current
–
0.9
2
mA
Table 11-30. Discrete Time Mixer AC Specifications
Parameter
LO
Min
Typ
Max
Units
Local oscillator frequency[29]
Description
Conditions
0
–
4
MHz
Input signal frequency for down
mixing[29]
0
–
14
MHz
Notes
29. Based on device characterization (Not production tested).
30. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V.
Document Number: 001-55035 Rev. *G
Page 73 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.9 Continuous Time Mixer
The continuous time mixer is used for modulating (shift) frequencies up or down, to a limit of 1.0 MHz. The continuous time mixer is
created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full AC/DC specifications, and APIs
and example code.
Table 11-31. Continuous Time Mixer DC Specifications
Parameter
Description
Conditions
Analog input noise injection (RMS) No input signal
Input voltage[31]
Min
Typ
Max
Units
–
VSSA
–
10
µV
–
VDDA
V
Input offset voltage
–
–
10
mV
Quiescent current
–
0.9
2
mA
Min
Typ
Max
Units
–
–
1
MHz
–
–
1
MHz
Table 11-32. Continuous Time Mixer AC Specifications
Parameter
LO
Description
Conditions
Local oscillator frequency[32]
Input signal
frequency[32]
11.5.10 Transimpedance Amplifier
The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full AC/DC specifications, and
APIs and example code.
Table 11-33. Transimpedance Amplifier (TIA) DC Specifications
Parameter
VIOFF
Description
Conditions
Input offset voltage
Min
Typ
Max
Units
–
–
10
mV
Conversion resistance[33]
Rconv
R = 20K
40 pF load
–20
–
+30
%
R = 30K
40 pF load
–20
–
+30
%
R = 40K
40 pF load
–20
–
+30
%
R = 80K
40 pF load
–20
–
+30
%
R = 120K
40 pF load
–20
–
+30
%
R = 250K
40 pF load
–20
–
+30
%
R= 500K
40 pF load
–20
–
+30
%
R = 1M
40 pF load
–20
–
+30
%
–
900
–
µA
Min
Typ
Max
Units
R = 20K
1800
–
–
kHz
R = 120K
330
–
–
kHz
R = 1M
47
–
–
kHz
R = 20K
1500
–
–
kHz
R = 120K
300
–
–
kHz
R = 1M
46
–
–
kHz
Quiescent current
Table 11-34. Transimpedance Amplifier (TIA) AC Specifications
Parameter
Description
Conditions
Input bandwidth (–3 dB) – 20 pF load[31]
Input bandwidth (3 dB) – 40 pF load
Notes
31. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V.
32. Based on device characterization (Not production tested).
33. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision
Document Number: 001-55035 Rev. *G
Page 74 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.11 Programmable Gain Amplifier
The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full AC/DC specifications,
and APIs and example code.
Table 11-35. PGA DC Specifications
Parameter
VOS
Description
Conditions
Min
Typ
Max
Units
–
–
10
mV
–
±30
–
–
250
µA
100 kHz
69
–
–
dB
1 MHz
38
–
–
dB
For non inverting inputs
35
–
–
M
–
–
±0.15
%
±1
%
Input offset voltage[34]
DeltaV/DeltaTa Input offset voltage
drift[34]
Output current source capability[34] Drive setting 3, VDDA = 1.71 V
PSRR
Zin
Power supply rejection
Input
ratio[34]
impedance[34]
µV/°C
Gain Error[34]
Non inverting mode, reference = VSSA
Ge1
Gain = 1
Rin of 40 K
Ge2
Gain = 2
Rin of 40 K
Ge4
Gain = 4
Rin of 40 K
–
–
±1.03
%
Ge8
Gain = 8
Rin of 40 K
–
–
±1.23
%
Ge16
Gain = 16
Rin of 40 K
–
–
±2.5
%
Ge32
Gain = 32
Rin of 40 K
–
–
±5
%
Ge50
Gain = 50
Rin of 40 K
–
–
±5
%
VONL
DC output non linearity G = 1[34]
–
–
0.01
% of FSR
VOH, VOL
Output voltage swing
VSSA +
0.15
–
VDDA –
0.15
V
Quiescent current[15]
–
–
1.65
mA
Conditions
Min
Typ
Max
Units
Table 11-36. PGA AC Specifications
Parameter
Description
–3 db Bandwidth[34]
BW1
Gain = 1
Noninverting mode, 300 mV  VIN
 VDDA – 1.2 V, Cl  25 pF
7
–
–
MHz
BW24
Gain = 24
Noninverting mode, 300 mV  VIN
 VDDA – 1.2 V, Cl  25 pF
360
–
–
kHz
BW48
Gain = 48
Noninverting mode, 300 mV  VIN
 VDDA – 1.2 V, Cl  25 pF
215
–
–
kHz
3
–
–
V/µs
Slew Rate[34]
SR1
Gain = 1
VDDA = 1.71 V 5% to 90% FS
output
SR24
Gain = 24
RC limited
0.5
–
–
V/µs
SR48
Gain = 48
RC limited
0.5
–
–
V/µs
Input Noise Voltage Density[34]
eni1
Gain = 1
10 kHz
–
38
–
nV/sqrtHz
eni24
Gain = 24
10 kHz
–
38
–
nV/sqrtHz
eni48
Gain = 48
10 kHz
–
38
–
nV/sqrtHz
Note
34. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 75 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.5.12 Unity Gain Buffer
The unity gain buffer is created using a SC/CT analog block. See the Unity Gain Buffer component datasheet in PSoC Creator for full
AC/DC specifications, and APIs and example code.
Table 11-37. Unity Gain Buffer DC Specifications
Parameter
VOS
Description
Input offset
Conditions
voltage[35]
Offset voltage drift
Input voltage range
VOH, VOL
Min
Typ
Max
Units
–
–
10
mV
–
–
30
µv/°C
VSSA
–
VDDA
V
VSSA +
0.15
–
VDDA –
0.15
V
Output current source capability[35] Drive setting 3, VDDA = 1.71 V
–
–
250
µA
Quiescent current
–
900
–
µA
Output voltage range
Table 11-38. Unity Gain Buffer AC Specifications
Parameter
Min
Typ
Max
Units
Bandwidth[35, 36]
Description
Noninverting mode, 300 mV  VIN 
VDDA – 1.2 V, Cl  25 pF
Conditions
7
–
–
MHz
Slew rate[35]
VDDA = 1.71 V 5% to 90% FS output,
CL = 50 pF
3
–
–
V/µs
–
38
–
nV/sqrtHz
Min
Typ
Max
Units
–
±5
–
°C
Input noise spectral density[35]
11.5.13 Temperature Sensor
Table 11-39. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
11.5.14 LCD Direct Drive
Table 11-40. LCD Direct Drive DC Specifications
Parameter
Description
Min
Typ
Max
Units
–
19
–
A
LCD bias range (VBIAS refers to the VDDA  3 V and VDDA  VBIAS
main output voltage(V0) of LCD
DAC)
2
–
5.5
V
VDDA  3 V and VDDA  VBIAS
–
9.1 x VDDA
–
mV
Drivers may be combined.
–
500
5000
pF
–
–
10
mV
528
–
655
µA
220
260
300
µA
ICC
LCD operating current
VBIAS
LCD bias step size
LCD capacitance per
segment/common driver
Conditions
16x4 segment display at 50 Hz [37].
Long term segment offset
IOUT (Output drive current per segment driver)
Strong drive
Output current in strong drive mode
for VDDIO = 5.5 V
ICC per segment driver
Strong drive
Notes
35. Based on device characterization (Not production tested).
36. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V.
37. This is the LCD system operating current when there is no LCD display. Connecting an actual LCD display increases the current consumption based on the size
of the LCD glass.
Document Number: 001-55035 Rev. *G
Page 76 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-40. LCD Direct Drive DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
Weak drive
–
11
–
µA
Weak drive 2
–
22
–
µA
No drive
–
<25
–
nA
Static (1 common)
IccLCD
LCD system operating current
VBIAS = 5 V
Number of LCD pins: 33 (32x1)
Number of segments: 32[38]
–
12
–
µA
IccLCD
LCD system operating current
VBIAS = 3 V
Number of LCD pins: 33 (32x1)
Number of segments: 32[38]
–
10
–
µA
IccLCD
LCD system operating current
VBIAS = 5 V
Number of LCD pins: 36 (32x4)
Number of segments: 128[38]
–
24
–
µA
IccLCD
LCD system operating current
VBIAS = 3 V
Number of LCD pins: 36 (32x4)
Number of segments: 128[38]
–
21
–
µA
1/4 duty (4 commons)
1/16 duty (16 commons)
IccLCD
LCD system operating current
VBIAS = 5 V
Number of LCD pins: 48 (32x16)
Number of segments: 512[38]
–
93
–
µA
IccLCD
LCD system operating current
VBIAS = 3 V
Number of LCD pins: 48 (32x16)
Number of segments: 512[38]
–
83
–
µA
Min
Typ
Max
Units
10
50
150
Hz
Table 11-41. LCD Direct Drive AC Specifications
Parameter
fLCD
Description
LCD frame rate
Conditions
Note
38. Additional conditions: All segments on; 2000 pF glass capacitance; Type A waveform; 32 Hz LCD refresh rate; Operating temperature = 25 °C; Boost converter not
used.
Document Number: 001-55035 Rev. *G
Page 77 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.6 Digital Peripherals
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.6.1 Timer
Table 11-42. Timer DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
3 MHz
12 MHz
48 MHz
67 MHz
80 MHz
Min
–
Typ
–
Max
–
Units
µA
–
–
–
–
–
8
30
120
165
195
–
–
–
–
–
µA
µA
µA
µA
µA
Min
Typ
Max
Units
DC
–
80
MHz
Table 11-43. Timer AC Specifications
Parameter
Description
Conditions
Operating frequency
Capture pulse width (Internal)
13
–
–
ns
Capture pulse width (external)
30
–
–
ns
Timer resolution
13
–
–
ns
Enable pulse width
13
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
13
–
–
ns
Reset pulse width (external)
30
–
–
ns
Conditions
Min
Typ
Max
Units
16-bit counter, at listed input clock
frequency
–
–
–
µA
–
8
–
µA
11.6.2 Counter
Table 11-44. Counter DC Specifications
Parameter
Description
Block current consumption
3 MHz
12 MHz
–
30
–
µA
48 MHz
–
120
–
µA
67 MHz
–
165
–
µA
80 MHz
–
195
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
80
MHz
Capture pulse
13
–
–
ns
Table 11-45. Counter AC Specifications
Parameter
Description
Conditions
Resolution
13
–
–
ns
Pulse width
13
–
–
ns
Pulse width (external)
30
–
–
ns
Enable pulse width
13
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
13
–
–
ns
Reset pulse width (external)
30
–
–
ns
Document Number: 001-55035 Rev. *G
Page 78 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.6.3 Pulse Width Modulation
Table 11-46. PWM DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
8
–
µA
12 MHz
–
30
–
µA
48 MHz
–
120
–
µA
67 MHz
–
165
–
µA
80 MHz
–
195
–
µA
Min
Typ
Max
Units
DC
–
80
MHz
Pulse width
13
–
–
ns
Pulse width (external)
30
–
–
ns
Kill pulse width
13
–
–
ns
Kill pulse width (external)
30
–
–
ns
Table 11-47. PWM AC Specifications
Parameter
Description
Conditions
Operating frequency
Enable pulse width
13
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
13
–
–
ns
Reset pulse width (external)
30
–
–
ns
Min
Typ
Max
Units
11.6.4 I2C
Table 11-48. Fixed I2C DC Specifications
Parameter
Description
Block current consumption
Conditions
Enabled, configured for 100 kbps
–
–
64
µA
Enabled, configured for 400 kbps
–
–
74
µA
Wake from sleep mode
–
–
TBD
µA
Min
Typ
Max
Units
–
–
1
Mbps
Table 11-49. Fixed I2C AC Specifications
Parameter
Description
Conditions
Bit rate
11.6.5 Controller Area Network[39]
Table 11-50. CAN DC Specifications
Parameter
Description
Block current consumption
Min
Typ
Max
Units
500 kbps
Conditions
–
–
285
µA
1 Mbps
–
–
330
µA
Min
Typ
Max
Units
–
–
1
Mbit
Table 11-51. CAN AC Specifications
Parameter
Description
Bit rate
Conditions
Minimum 8 MHz clock
Note
39. Refer to ISO 11898 specification for details.
Document Number: 001-55035 Rev. *G
Page 79 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.6.6 USB
Table 11-52. USB DC Specifications
Parameter
Description
Conditions
Operating current
USB enabled bus idle
Min
Typ
Max
Units
–
0.68
–
mA
11.6.7 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-53. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
80
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
80
MHz
FMAX_CRC
–
–
80
MHz
–
–
80
MHz
Datapath Performance
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C operating temperature
out, see Figure 11-1.
–
TBD
TBD
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-1.
and pin selection
–
TBD
TBD
ns
Figure 11-1. Clock to Output Performance
Document Number: 001-55035 Rev. *G
Page 80 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.7 Memory
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.7.1 Flash
Table 11-54. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Table 11-55. Flash AC Specifications
Min
Typ
Max
Units
TWRITE
Parameter
Row write time (erase + program)
–
–
15
ms
TERASE
Row erase time
–
–
10
ms
Row program time
–
–
5
ms
Bulk erase time (256 KB)
–
–
80
ms
Sector erase time (16 KB)
–
–
15
ms
Total device program time 
(including JTAG, and so on)
–
–
5
seconds
100 k
–
–
program/
erase
cycles
20
–
–
years
Min
Typ
Max
Units
1.71
–
5.5
V
Min
Typ
Max
Units
–
2
15
ms
1M
–
–
program/
erase
cycles
20
–
–
years
Min
Typ
Max
Units
1.71
–
5.5
V
TBULK
Description
Conditions
Flash endurance
Flash data retention time
Retention period measured from
last erase cycle
11.7.2 EEPROM
Table 11-56. EEPROM DC Specifications
Parameter
Description
Conditions
Erase and program voltage
Table 11-57. EEPROM AC Specifications
Parameter
TWRITE
Description
Conditions
Single byte erase/write cycle time
EEPROM endurance
EEPROM data retention time
Retention period measured from
last erase cycle (up to 100 K cycles)
11.7.3 Nonvolatile Latches (NVL)
Table 11-58. NVL DC Specifications
Parameter
Description
Erase and program voltage
Document Number: 001-55035 Rev. *G
Conditions
VDDD pin
Page 81 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-59. NVL AC Specifications
Parameter
Description
Conditions
NVL endurance
NVL data retention time
Min
Typ
Max
Units
Programmed at 25 °C
1K
–
–
program/
erase
cycles
Programmed at 0 °C to 70 °C
100
–
–
program/
erase
cycles
Programmed at 25 °C
20
–
–
years
Programmed at 0 °C to 70 °C
20
–
–
years
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
80
MHz
Units
11.7.4 SRAM
Table 11-60. SRAM DC Specifications
Parameter
VSRAM
Description
Conditions
SRAM retention voltage
Table 11-61. SRAM AC Specifications
Parameter
FSRAM
Description
Conditions
SRAM operating frequency
11.7.5 External Memory Interface
Figure 11-2. Asynchronous Read Cycle Timing
Tcel
EM_CEn
Taddrv
EM_Addr
Taddrh
Address
Toev
Toeh
Toel
EM_OEn
EM_WEn
Tdoesu
Tdoeh
Tdceh
Tdcesu
EM_Data
Data
Table 11-62. Asynchronous Read Cycle Specifications
Min
Typ
Max
T
Parameter
EMIF clock period
Description
Conditions
30.3
–
–
ns
Tcel
EM_CEn low time
2×T–1
–
2×T+2
ns
Taddrv
EM_CEn low to EM_Addr valid
–
–
5
ns
Taddrh
Address hold time after EM_OEn high
2
–
–
ns
Toev
EM_CEn low to EM_OEn low
–5
–
5
ns
Document Number: 001-55035 Rev. *G
Page 82 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 11-62. Asynchronous Read Cycle Specifications (continued)
Parameter
Description
Toel
EM_OEn low time
Toeh
EM_OEn high to EM_CEn high hold time
Conditions
Min
Typ
Max
Units
2×T–1
–
2×T+2
ns
–5
–
5
ns
Tdoesu
Data to EM_OEn high setup time
T + 20
–
–
ns
Tdcesu
Data to EM_CEn high setup time
T + 20
–
–
ns
Tdoeh
Data hold time after EM_OEn high
3
–
–
ns
Tdceh
Data hold time after EM_CEn high
3
–
–
ns
Max
Units
Figure 11-3. Asynchronous Write Cycle Timing
Taddrv
EM_ Addr
Taddrh
Address
Tcel
EM_ CEn
EM_ OEn
Twev
Twel
Tweh
EM_WEn
Tdweh
Tdcev
Data
EM_ Data
Table 11-63. Asynchronous Write Cycle Specifications
Parameter
Description
T
EMIF clock period
Taddrv
EM_CEn low to EM_Addr valid
Taddrh
Address hold time after EM_WEn high
Tcel
EM_CEn low time
Twev
EM_CEn low to EM_WEn low
Twel
EM_WEn low time
Tweh
Tdcev
Tdweh
Conditions
Min
Typ
30.3
–
–
ns
–
–
5
ns
T+2
–
–
ns
2×T–1
–
2×T+2
ns
–5
–
5
ns
T–1
–
T+2
ns
EM_WEn high to EM_CEn high hold time
T
–
–
ns
EM_CEn low to data valid
–
–
7
ns
Data hold time after EM_WEn high
T
–
–
ns
Document Number: 001-55035 Rev. *G
Page 83 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 11-4. Synchronous Read Cycle Timing
Tcp
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddrv
Taddriv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tdh
Tds
EM_ Data
Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-64. Synchronous Read Cycle Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
T
EMIF clock period
30.3
–
–
ns
Tcp
EM_clock period
30.3
–
–
ns
Tceld
EM_clock low to EM_CEn low
–
–
5
ns
Tcehd
EM_clock high to EM_CEn high
T/2 – 2
–
–
ns
Taddrv
EM_clock low to EM_Addr valid
–
–
5
ns
Taddriv
EM_clock high to EM_Addr invalid
T/2 – 2
–
–
ns
ns
Toeld
EM_clock low to EM_OEn low
–
–
5
Toehd
EM_clock high to EM_OEn high
T+2
–
–
ns
Tds
Data valid before EM_Clock high
20
–
–
ns
Tdh
Data valid after EM_Clock high
2
–
–
ns
Tadscld
EM_clock low to EM_ADSCn low
–
–
5
ns
Tadschd
EM_clock high to EM_ADSCn high
T/2 – 2
–
–
ns
Document Number: 001-55035 Rev. *G
Page 84 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 11-5. Synchronous Write Cycle Timing
Tcp
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddrv
Taddriv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-65. Synchronous Write Cycle Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
T
EMIF clock period
30.3
–
–
ns
Tcp
EM_clock period
30.3
–
–
ns
Tceld
EM_clock low to EM_CEn low
–
–
5
ns
Tcehd
EM_clock high to EM_CEn high
T/2 – 2
–
–
ns
Taddrv
EM_clock low to EM_Addr valid
–
–
5
ns
Taddriv
EM_clock high to EM_Addr invalid
T/2 – 2
–
–
ns
Tweld
EM_clock low to EM_WEn low
Twehd
EM_clock high to EM_WEn high
Tds
Data valid after EM_Clock low
Tadscld
EM_clock low to EM_ADSCn low
Tadschd
EM_clock high to EM_ADSCn high
Document Number: 001-55035 Rev. *G
–
–
5
ns
T/2 – 2
–
–
ns
–
–
5
ns
–
–
5
ns
T/2 – 2
–
–
ns
Page 85 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.8 PSoC System Resources
Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.8.1 POR with Brown Out
For brown out detect in regulated mode, VDDD and VDDA must be  2.0 V. Brown out detect is available in externally regulated mode.
Table 11-66. Precise Power On Reset (PRES) with Brown Out DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Precise POR (PPOR)
PRESR
Rising trip voltage
1.66
–
1.73
V
PRESF
Falling trip voltage
1.63
–
1.70
V
Min
Typ
Max
Units
–
–
250
ns
–
5
TBD
V/µs
Min
Typ
Max
Units
Table 11-67. Power On Reset (POR) with Brown Out AC Specifications
Parameter
Description
Conditions
PRES_TR Response time
VDDD/VDDA drop rate
Sleep mode
11.8.2 Voltage Monitors
Table 11-68. Voltage Monitors DC Specifications
Parameter
LVI
Description
Conditions
Trip voltage
–
–
–
LVI_A/D_SEL[3:0] = 0000b
1.68
1.73
1.77
V
LVI_A/D_SEL[3:0] = 0001b
1.91
1.95
1.99
V
LVI_A/D_SEL[3:0] = 0010b
2.16
2.21
2.25
V
LVI_A/D_SEL[3:0] = 0011b
2.40
2.45
2.50
V
LVI_A/D_SEL[3:0] = 0100b
2.65
2.71
2.76
V
LVI_A/D_SEL[3:0] = 0101b
2.90
2.96
3.01
V
LVI_A/D_SEL[3:0] = 0110b
3.14
3.21
3.27
V
LVI_A/D_SEL[3:0] = 0111b
3.39
3.46
3.53
V
LVI_A/D_SEL[3:0] = 1000b
3.63
3.71
3.78
V
LVI_A/D_SEL[3:0] = 1001b
3.88
3.96
4.03
V
LVI_A/D_SEL[3:0] = 1010b
4.12
4.21
4.29
V
LVI_A/D_SEL[3:0] = 1011b
4.36
4.45
4.54
V
LVI_A/D_SEL[3:0] = 1100b
4.61
4.70
4.79
V
LVI_A/D_SEL[3:0] = 1101b
4.88
4.98
5.08
V
LVI_A/D_SEL[3:0] = 1110b
5.11
5.22
5.32
V
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
5.36
5.47
5.57
V
5.630
5.745
5.860
V
Min
Typ
Max
Units
–
–
500
ns
Table 11-69. Voltage Monitors AC Specifications
Parameter
Description
Response time
Document Number: 001-55035 Rev. *G
Conditions
Page 86 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.8.3 Interrupt Controller
Table 11-70. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from main line code
longest instruction DIV with 6
cycles
–
–
20
Tcy CPU
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
–
–
20
Tcy CPU
Min
Typ
Max
Units
MHz
11.8.4 JTAG Interface
Table 11-71. JTAG Interface AC Specifications[40]
Parameter
f_TCK
Description
TCK frequency
Conditions
3.3 V  VDDD  5 V
–
–
14[41]
1.71 V  VDDD < 3.3 V
–
–
7[41]
MHz
ns
T_TDI_setup
TDI, TMS setup before TCK high
0
–
–
T_TDI_hold
TDI, TMS hold after TCK high
T = 1/f_TCK
T/4
–
–
T_TDO_valid
TCK low to TDO valid
T = 1/f_TCK
2T/5
–
–
T_TDO_hold
TDO hold after TCK high
T = 1/f_TCK
T/4
–
–
–
–
TBD
ns
Min
Typ
Max
Units
–
–
14[42]
MHz
MHz
MHz
TCK to device outputs valid
11.8.5 SWD Interface
Table 11-72. SWD Interface AC Specifications[40]
Parameter
f_SWDCK
Description
SWDCLK frequency
Conditions
3.3 V  VDDD  5 V
1.71 V  VDDD < 3.3 V
–
–
7[42]
1.71 V  VDDD < 3.3 V, SWD over
USBIO pins
–
–
5.5[42]
T/4
–
–
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK
T_SWDI_hold
SWDIO input hold after SWDCK high
T = 1/f_SWDCK
T/4
–
–
T = 1/f_SWDCK
2T/5
–
–
T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK
T/4
–
–
Min
Typ
Max
Units
–
–
33[43]
MHz
–
33[43]
Mbit
T_SWDO_valid SWDCK low to SWDIO output valid
11.8.6 TPIU Interface
Table 11-73. TPIU Interface AC Specifications[40]
Parameter
Description
TRACEPORT (TRACECLK) frequency
SWV bit rate
Conditions
–
Notes
40. Based on device characterization (Not production tested).
41. f_TCK must also be no more than 1/3 CPU clock frequency.
42. f_SWDCK must also be no more than 1/3 CPU clock frequency.
43. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency. See “GPIO” on page 63.for AC Specifications.
Document Number: 001-55035 Rev. *G
Page 87 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.9 Clocking
Specifications are valid for –40 °C TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.9.1 32 kHz External Crystal
Table 11-74. 32 kHz External Crystal DC Specifications[44]
Parameter
Description
Operating current
ICC
CL
External crystal capacitance
DL
Drive level
Conditions
Low power mode
Min
–
–
–
Typ
–
6
–
Max
0.25
–
1
Units
µA
pF
µW
Min
–
20
–
Typ
32.768
50
1
Max
–
80
–
Units
kHz
%
s
Min
Typ
Max
Units
–
–
–
–
–
–
–
–
–
–
–
–
–
–
600
500
500
300
200
180
150
µA
µA
µA
µA
µA
µA
µA
Min
Typ
Max
Units
–7
–5
–4
–0.25
–3
–2
–1
–
–
–
–
–
–
–
–
–
7
5
4
0.25
3
2
1
12
%
%
%
%
%
%
%
µs
–
–
0.9
1.6
–
–
ns
ns
–
–
0.9
12
–
–
ns
ns
Table 11-75. 32 kHz External Crystal AC Specifications
Parameter
Description
F
Frequency
DC
Output duty cycle[44]
Startup time
TON
Conditions
High power mode
11.9.2 Internal Main Oscillator)
Table 11-76. IMO DC Specifications
Parameter
Description
Supply current
74.7 MHz
48 MHz
24 MHz – USB mode
24 MHz – non USB mode
12 MHz
6 MHz
3 MHz
Conditions
With oscillator locking to USB bus
Table 11-77. IMO AC Specifications
Parameter
FIMO
Jp-p
Jperiod
Description
Conditions
IMO frequency stability (with factory trim)
74.7 MHz
48 MHz
24 MHz – Non USB mode
24 MHz – USB mode
With oscillator locking to USB bus
12 MHz
6 MHz
3 MHz
From enable (during normal system
Startup time[44]
operation) or wakeup from low power
state
[44]
Jitter (peak to peak)
F = 24 MHz
F = 3 MHz
Jitter (long term)[44]
F = 24 MHz
F = 3 MHz
Note
44. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 88 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.9.3 Internal Low Speed Oscillator
Table 11-78. ILO DC Specifications
Parameter
Description
Operating current
ICC
Leakage current
Conditions
Min
Typ
Max
Units
FOUT = 1 kHz
–
0.3
1.7
µA
FOUT = 33 kHz
–
1.0
2.6
µA
FOUT = 100 kHz
–
1.0
2.6
µA
Power down mode
–
2.0
15
nA
Min
Typ
Max
Units
Table 11-79. ILO AC Specifications
Parameter
Description
Conditions
Startup time
Turbo mode
–
–
2
ms
Startup time
Non turbo mode, pd_mode = 0
–
–
2
ms
Startup time
Non turbo mode, pd_mode = 1
–
–
15
ms
47
50
53
%
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
100 kHz
30
100
300
kHz
1 kHz
0.3
1
3.5
kHz
Min
Typ
Max
Units
4
–
33
MHz
40
50
60
%
Min
Typ
Max
Units
Duty cycle
ILO frequencies (trimmed)
FILO
ILO frequencies (untrimmed)
11.9.4 External Crystal Oscillator
Table 11-80. ECO AC Specifications
Parameter
F
DC
Description
Conditions
Crystal frequency range
Duty
cycle[45]
11.9.5 External Clock Reference
Table 11-81. External Clock Reference AC Specifications[45]
Parameter
Description
Conditions
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.1
–
–
V/ns
Note
45. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 89 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
11.9.6 Phase-Locked Loop
Table 11-82. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Conditions
Min
Typ
Max
Units
In = 3 MHz, Out = 80 MHz
–
400
–
µA
In = 3 MHz, Out = 24 MHz
–
200
–
µA
Min
Typ
Max
Units
1
–
48
MHz
1
–
3
MHz
Table 11-83. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
PLL intermediate frequency[47]
Fpllout
Conditions
frequency[46]
Output of prescaler
PLL output frequency[46]
24
–
67
MHz
Lock time at startup
–
–
250
µs
–
–
250
ps
45
–
55
%
Jperiod-rms Jitter
(rms)[48]
PLL output duty cycle
All PLL output frequencies
Notes
46. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
47. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
48. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 90 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C53 device includes: up to 128 KB flash, 32 KB SRAM, 2 KB EEPROM, a
precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, JTAG/SWD programming and debug,
external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of
peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components
required by your application. All CY8C53 derivatives incorporate device and flash security in user-selectable security levels; see the
TRM for details.
Table 12-1. CY8C53 Family with ARM Cortex-M3 CPU
I/O[51]
Digital
UDBs[50]
16-bit Timer/PWM
Total I/O
GPIO
SIO
USBIO
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 20
4
62
8
0
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 20
4
– –
– –
70
8
46
38
8
0
68-pin QFN
0x0E122069
CY8C5385PVI-109
80
32
8
2
✔
- ✔ 20
4
-
-
29
25
4
0
48-SSOP
0x0E16D069
CY8C5385AXI-043
80
32
8
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 20
4
✔
72
62
8
2
CY8C5385LTI-104
80
32
8
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 20
CY8C5385PVI-042
80
32
8
2
✔
CY8C5385AXI-025
80
32
8
2
✔ 1 × 12-bit SAR 2
CY8C5385PVI-080
80
32
8
2
✔
CY8C5385AXI-096
80
32
8
2
✔ 1 × 12-bit SAR 2
CY8C5385PVI-010
80
32
8
2
✔
CY8C5386AXI-076
80
64
16
2
CY8C5386LTI-005
80
64
16
2
CY8C5386PVI-070
80
64
16
2
✔
CY8C5386AXI-001
80
64
16
2
CY8C5386LTI-053
80
64
16
CY8C5386PVI-057
80
64
16
CY8C5386AXI-081
80
64
CY8C5386PVI-040
80
CY8C5386AXI-105
80
CY8C5386PVI-098
CAN 2.0b
Package
FS USB
DFB
CapSense
8
32
Opamps
EEPROM (KB)
32
80
Comparators
SRAM (KB)
80
CY8C5385LTI-034
DAC
Flash (KB)
CY8C5385AXI-015
Part Number
ADC
CPU Speed (MHz)
SC/CT Analog Blocks[49]
Analog
LCD Segment Drive
MCU Core
JTAG ID[52]
32 KB Flash
1x12-bit SAR
1x12-bit SAR
1x12-bit SAR
2 4 2 2
100-pin TQFP 0x0E10F069
4
✔
–
–
48
38
8
2
68-pin QFN
0x0E168069
- ✔ 20
4
✔
-
31
25
4
2
48-SSOP
0x0E12A069
4 2 2 – ✔ 20
4
–
✔
70
62
8
0
2 4 2 2
100-pin TQFP 0x0E119069
- ✔ 20
4
-
✔
29
25
4
0
4 2 2 – ✔ 20
4
✔
✔
72
62
8
2
- ✔ 20
4
✔
✔
31
25
4
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
62
8
0
4 2 2 – ✔ 24
4
– –
– –
70
✔ 1 × 12-bit SAR 2
46
38
8
0
68-pin QFN
0x0E105069
- ✔ 24
4
-
-
29
25
4
0
48-SSOP
0x0E146069
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
✔
72
62
8
2
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
2
✔
16
2
✔ 1 × 12-bit SAR 2
64
16
2
✔
64
16
2
✔ 1 × 12-bit SAR 2
80
64
16
2
✔
CY8C5387AXI-099
80
128 32
2
CY8C5387LTI-075
80
128 32
CY8C5387PVI-031
80
128 32
CY8C5387AXI-108
80
CY8C5387LTI-003
80
1x12-bit SAR
2 4 2 2
100-pin TQFP 0x0E12B069
2 4 2 2
48-SSOP
0x0E150069
100-pin TQFP 0x0E160069
48-SSOP
0x0E10A069
64 KB Flash
1x12-bit SAR
1x12-bit SAR
1x12-bit SAR
2 4 2 2
4
✔
–
–
48
38
8
2
68-pin QFN
0x0E135069
- ✔ 24
4
✔
-
31
25
4
2
48-SSOP
0x0E139069
4 2 2 – ✔ 24
4
–
✔
70
62
8
0
2 4 2 2
- ✔ 24
4
-
✔
29
25
4
0
4 2 2 – ✔ 24
4
✔
✔
72
62
8
2
- ✔ 24
4
✔
✔
31
25
4
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
70
62
8
0
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
2
✔
128 32
2
128 32
2
1x12-bit SAR
100-pin TQFP 0x0E14C069
2 4 2 2
2 4 2 2
100-pin TQFP 0x0E101069
100-pin TQFP 0x0E151069
48-SSOP
0x0E128069
100-pin TQFP 0x0E169069
48-SSOP
0x0E162069
128 KB Flash
4
– –
– –
46
38
8
0
68-pin QFN
0x0E14B069
- ✔ 24
4
-
-
29
25
4
0
48-SSOP
0x0E11F069
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
✔
72
62
8
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
✔
–
–
48
38
8
2
1x12-bit SAR
2 4 2 2
100-pin TQFP 0x0E163069
100-pin TQFP 0x0E16C069
68-pin QFN
0x0E103069
Notes
49. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 34 for more information on how analog blocks
can be used.
50. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 34 for more information on how UDBs can be used.
51. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 28 for details on the functionality of each of
these types of I/O.
52. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-55035 Rev. *G
Page 91 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Table 12-1. CY8C53 Family with ARM Cortex-M3 CPU (continued)
CY8C5387PVI-036
80
128 32
2
✔
CY8C5387AXI-023
80
128 32
2
✔ 1 × 12-bit SAR 2
1x12-bit SAR
CY8C5387PVI-045
80
128 32
2
✔
CY8C5387AXI-083
80
128 32
2
✔ 1 × 12-bit SAR 2
CY8C5387PVI-072
80
128 32
2
✔
CY8C5388AXI-008
80
256 64
2
CY8C5388LTI-032
80
256 64
2
CY8C5388PVI-055
80
256 64
2
✔
CY8C5388AXI-106
80
256 64
2
CY8C5388LTI-026
80
256 64
CY8C5388PVI-014
80
CY8C5388AXI-088
80
CY8C5388PVI-016
CY8C5388AXI-035
CY8C5388PVI-027
1x12-bit SAR
2 4 2 2
- ✔ 24
4
✔
-
31
25
4
2
4 2 2 – ✔ 24
4
–
✔
70
62
8
0
- ✔ 24
4
-
✔
29
25
4
0
4 2 2 – ✔ 24
2 4 2 2
48-SSOP
0x0E124069
100-pin TQFP 0x0E117069
48-SSOP
0x0E12D069
4
✔
✔
72
62
8
2
- ✔ 24
4
✔
✔
31
25
4
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
62
8
0
4 2 2 – ✔ 24
4
– –
– –
70
✔ 1 × 12-bit SAR 2
46
38
8
0
68-pin QFN
0x0E120069
- ✔ 24
4
-
-
29
25
4
0
48-SSOP
0x0E137069
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
✔
72
62
8
2
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
✔
–
–
48
38
8
2
256 64
2
✔
- ✔ 24
4
✔
-
31
25
4
2
256 64
2
✔ 1 × 12-bit SAR 2
4 2 2 – ✔ 24
4
–
✔
70
62
8
0
80
256 64
2
✔
80
256 64
2
✔ 1 × 12-bit SAR 2
80
256 64
2
✔
1x12-bit SAR
2 4 2 2
100-pin TQFP 0x0E153069
48-SSOP
0x0E148069
256 KB Flash
Document Number: 001-55035 Rev. *G
1x12-bit SAR
1x12-bit SAR
1x12-bit SAR
1x12-bit SAR
2 4 2 2
2 4 2 2
2 4 2 2
- ✔ 24
4
-
✔
29
25
4
0
4 2 2 – ✔ 24
4
✔
✔
72
62
8
2
4
✔
✔
31
25
4
2
2 4 2 2
- ✔ 24
100-pin TQFP 0x0E108069
100-pin TQFP 0x0E16A069
68-pin QFN
0x0E11A069
48-SSOP
0x0E10E069
100-pin TQFP 0x0E158069
48-SSOP
0x0E110069
100-pin TQFP 0x0E123069
48-SSOP
0x0E11B069
Page 92 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
12.1 Part Numbering Conventions
PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
 a: Architecture
3: PSoC 3
 5: PSoC 5

 b: Family group within architecture
2: CY8C52 family
3: CY8C53 family
 4: CY8C54 family
 5: CY8C55 family


 c: Speed grade


4: 40 MHz
8: 80 MHz
 d: Flash capacity
 ef: Package code
Two character alphanumeric
AX: TQFP
 LT: QFN
 PV: SSOP


 g: Temperature range
C: commercial
I: industrial
 A: automotive


 xxx: Peripheral set


Three character numeric
No meaning is associated with these three characters
5: 32 KB
6: 64 KB
 7: 128 KB
 8: 256 KB


Examples
CY8C
5 3 8 8 AX /PV I
- x x x
Cypress Prefix
5: PSoC 5
3: CY8C53 Family
Architecture
Family Group within Architecture
8: 80 MHz
Speed Grade
8: 256 KB
Flash Capacity
AX: TQFP, PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 5 CY8C53 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
Document Number: 001-55035 Rev. *G
Page 93 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package JA (68 QFN)
–
10.93
–
°C/Watt
TJA
Package JA (100 TQFP)
–
29.50
–
°C/Watt
Tjc
Package JC (48 SSOP)
-
25.48
-
°C/Watt
TJC
Package JC (68 QFN)
–
6.08
–
°C/Watt
TJC
Package JC (100 TQFP)
–
7.32
–
°C/Watt
Pb-free assemblies (20s to 40s) –
Sn-Ag-Cu solder paste reflow
temperature
235
–
245
°C
Pb-free assemblies (20s to 40s) – 
Sn-Pb solder paste reflow
temperature
205
–
220
°C
Table 13-2. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
48-pin SSOP
MSL 1
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
Figure 13-1. 48-pin (300 mil) SSOP Package Outline
.020
24
1
0.395
0.420
0.292
0.299
25
DIMENSIONS IN INCHES MIN.
MAX.
48
0.620
0.630
0.088
0.092
0.095
0.110
0.025
BSC
Document Number: 001-55035 Rev. *G
SEATING PLANE
0.005
0.010
.010
GAUGE PLANE
0.004
0.008
0.0135
0.008
0.016
0°-8°
0.024
0.040
51-85061-*D
Page 94 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Figure 13-2. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.900±0.100
5.7±0.10
8.000±0.100
0.200 REF
5
1
6
8
5
2
1
PIN 1 DOT
8.000±0.100
LASER MARK
1
7
0.20±0.05
3
5
3
0.400±0.1005
0.05 MAX
C
0.08
NOTES:
1.
3
4
1
8
1
7
6.40 REF
SEATING PLANE
3
4
1
8
SOLDERABLE
EXPOSED
PAD
5.7±0.10
6.40 REF
5
1
1
PIN1 ID
R 0.20
0.400 PITCH
5
2
6
8
HATCH AREA IS SOLDERABLE EXPOSED METAL.
001-09618 *C
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.17g
4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 13-3. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
NOTE:
16.00±0.25 SQ
1. JEDEC STD REF MS-026
14.00±0.05 SQ
100
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
76
1
75
0.22±0.05
3. DIMENSIONS IN MILLIMETERS
R 0.08 MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.50
TYP.
25
0.25
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
DETAIL
A
0°-7°
0 0 12.0000
0.60±0.15
51
26
SEATING PLANE
1.60 MAX.
50
NOTE: PKG. CAN HAVE
OR
12°±1°
(8X)
1.40±0.05
TOP LEFT CORNER CHAMFER
4 CORNERS CHAMFER
0.08
0.20 MAX.
SEE DETAIL
Document Number: 001-55035 Rev. *G
A
51-85048-*D
Page 95 of 102
[+] Feedback
PRELIMINARY
14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Table 14-1. Acronyms Used in this Document
Acronym
PSoC® 5: CY8C53 Family Datasheet
Description
Acronym
Description
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
IC
integrated circuit
ALU
arithmetic logic unit
IDAC
current DAC, see also DAC, VDAC
AMUXBUS
analog multiplexer bus
IDE
integrated development environment
application programming interface
I2C,
API
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
common-mode rejection ratio
IPOR
initial power-on reset
CPU
central processing unit
IPSR
interrupt program status register
CRC
cyclic redundancy check, an error-checking
protocol
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DR
port write data registers
LVD
low-voltage detect, see also LVI
DRES
digital logic reset
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
Document Number: 001-55035 Rev. *G
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
Page 96 of 102
[+] Feedback
PRELIMINARY
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PSoC® 5: CY8C53 Family Datasheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PHUB
peripheral hub
SOF
start of frame
PHY
physical layer
SPI
PICU
port interrupt control unit
Serial Peripheral Interface, a communications
protocol
PLA
programmable logic array
SR
slew rate
PLD
programmable logic device, see also PAL
SRAM
static random access memory
PLL
phase-locked loop
SRES
software reset
PMDD
package material declaration datasheet
SWD
serial wire debug, a test protocol
POR
power-on reset
SWV
single-wire viewer
PRES
precise power-on reset
TD
transaction descriptor, see also DMA
PRS
pseudo random sequence
THD
total harmonic distortion
PS
port read data register
TIA
transimpedance amplifier
PSoC®
Programmable System-on-Chip™
TRM
technical reference manual
PSRR
power supply rejection ratio
TTL
transistor-transistor logic
PWM
pulse-width modulator
TX
transmit
RAM
random-access memory
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
RX
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
remote transmission request
VDAC
voltage DAC, see also DAC, IDAC
receive
WDT
watchdog timer
SAR
successive approximation register
WOL
write once latch, see also NVL
SC/CT
switched capacitor/continuous time
WRES
watchdog timer reset
SCL
I2C
XRES
external reset I/O pin
SDA
I2C serial data
XTAL
crystal
S/H
sample and hold
SIO
special input/output, GPIO with advanced
features. See GPIO.
SNR
signal-to-noise ratio
SOC
start of conversion
serial clock
Document Number: 001-55035 Rev. *G
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 5 Registers TRM
Page 97 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
k
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
megaohms
Msps
megasamples per second
µA
microamperes
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts

ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Document Number: 001-55035 Rev. *G
Page 98 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
17. Revision History
Description Title: PSoC® 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-55035
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
2759055
09/02/09
MKEA
New datasheet for new device CY8C53 Family Datasheet.
*A
2824626
12/09/09
MKEA
Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost
AC and DC specs); also added Shottky Diode specs. Changed current for
sleep/hibernate mode to include SIO; Added footnote to analog global specs.
Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3
(Hibernate and Sleep rows) and Power Modes section. Updated GPIO and
SIO AC specifications. Updated Gain error in IDAC and VDAC specifications.
Updated description of VDDA spec in Table 11-1 and removed GPIO Clamp
Current parameter. Moved FILO from ILO DC to AC table.
Added PCB Layout and PCB Schematic diagrams.
Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC
spec table. Added note for Sleep and Hibernate modes and Active Mode
specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site.
Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and
Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig
ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs.
Removed SPC ADC. Updated Boost Converter section.
Added section 'SIO as Comparator'; updated Hysteresis spec (differential
mode) in Table 11-10.
Updated VBAT condition and deleted Vstart parameter in Table 11-6.
Removed reference to Idle mode. CDT 59671: Updated footnotes and ADC
column in ordering information. Removed CSA (Section 8.7). Updated IMO
table and number of UDBs
*B
2873520
02/04/10
MKEA
Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification.
Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated
Sales links. Updated JTAG and SWD specifications. Removed Jp-p and
Jperiod from ECO AC Spec table. Added note on sleep timer in Table 11-2.
Updated ILO AC and DC specifications. Added Resolution parameter in
VDAC and IDAC tables. Updated IOUT typical and maximum values.
Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup
specification from Table 11-1
Document Number: 001-55035 Rev. *G
Page 99 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Description Title: PSoC® 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-55035
*C
2911720
04/13/10
Document Number: 001-55035 Rev. *G
MKEA
Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table.
Updated ICC parameter in LCD Direct Drive DC Specs table.
In page 1, updated internal oscillator range under Precision programmable
clocking to start from 3 MHz.
Updated IOUT parameter in LCD Direct Drive DC Specs table.
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section
12.
Removed some references to footnote [1].
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and
modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low power modes bullet in
page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for
VDDA and VDDD pins.
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-68.
Updated 6.3.1.1, Power Voltage Level Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from
flash.
Updated VREF specs in Table 11-21.
Updated IDAC uncompensated gain error in Table 11-25.
Added sentence to last paragraph of section 6.1.1.3.
Updated TRESP, high and low power modes, in Table 11-24.
Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74.
Updated SNR condition in Table 11-20.
Corrected unit of measurement in Table 11-21.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= VDDD < 3.3 V, SWD over USBIO pins value to Table 11-74.
Removed mention of hibernate reset (HRES) from page 1 features, Table
6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1.
Changed PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed
PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-68 (changed
title, values TBD), and Table 11-69 (changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section
6.3.1.1.
Changed IDD values on page 1, page 5, and Table 11-2.
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Removed VDDA = 1.65 V rows and changed BWag value in Table 11-22.
Changed VIOFF values and changed CMRR value in Table 11-23.
Changed INL max value in Table 11-27.
Added max value to the Quiescent current specs in Tables 11-29 and 11-31.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-57.
Changed max response time value in Tables 11-69 and 11-71.
Changed the Startup time in Table 11-79.
Added condition to intermediate frequency row in Table 11-85.
Added row to Table 11-69.
Added brown out note to Section 11.8.1.
Page 100 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Description Title: PSoC® 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-55035
*D
2936486
05/24/10
MKEA
*E
2944841
6/4/2010
FSU
*F
2960407
06/24/10
MKEA
Corrected typo in Table 11-3 (V/ms to V/ns) and Tables 11-29 and 11-31 (µA
to mA)
*G
3019464
08/31/10
MKEA
Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram
Added to Table 6-6 a footnote and references to same.
Added sentences to the resistive pull-up and pull-down description bullets.
Added sentence to Section 6.4.11, Adjustable Output Level.
Updated section 5.5 External Memory Interface
Updated Table 11-73 JTAG Interface AC Specifications
Updated Table 11-74 SWD Interface AC Specifications
A footnote, TRACEPORT / TRACECLK max frequency is limited by GPIO
max frequency, is added to the section 11.8.6.
48-SSOP package added.
Document Number: 001-55035 Rev. *G
Replaced VDDIO with VDDD in USBIO diagram and specification tables,
added text in USBIO section of Electrical Specifications.
Added Table 13-2 (Package MSL)
Modified Tstorag condition and changed maximum value to 100
Added bullet (Pass) in ALU (section 7.2.2.2)
Added figures for kHzECO and MHzECO in the External Oscillator section
Updated Figure 6-1(Clocking Subsystem diagram)
Resolved discrepancies with the EROS in Electrical Specifications sections
Updated PSoC Creator Framework image
Updated SIO DC Specifications (VIH and VIL parameters)
Updated values in Low power modes bullet on page 1
Updated Figure 8-2
Updated PCB Layout and Schematic, updates as per MTRB review
comments
Updated Table 6-3 (power changed to current)
In 32kHZ EC DC Specifications table , changed ICC Max to 0.25
In IMO DC Specifications table, updated Supply Current values
Updated GPIO DC Specs table
Removed all references to 48-SSOP package
Minor update to post to cypress.com.
Page 101 of 102
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
PSoC Solutions
cypress.com/go/automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-55035 Rev. *G
®
®
®
®
Revised September 2, 2010
Page 102 of 102
®
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
Similar pages