LINER LTC1274CSW 12-bit, 10mw, 100ksps adcs with 1î¼a shutdown Datasheet

LTC1274/LTC1277
12-Bit, 10mW, 100ksps
ADCs with 1µA Shutdown
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FEATURES
DESCRIPTIO
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The LTC ®1274/LTC1277 are 8µs sampling 12-bit A/D
converters which draw only 2mA (typ) from single 5V or
±5V supplies. These easy-to-use devices come complete
with a 2µs sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion
modes add to the flexibility of the ADCs.
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Low Power Dissipation: 10mW
Sample Rate: 100ksps
Samples Inputs Beyond Nyquist, 72dB S/(N + D)
and 82dB THD at fIN = 100kHz
Single Supply 5V or ±5V Operation
Power Shutdown to 1µA in Sleep Mode
180µA Nap Mode (LTC1277) with Instant Wake-Up
Internal Reference Can Be Overdriven
Internal Synchronized Clock
0V to 4.096V or ±2.048V Input Ranges (1mV/LSB)
24-Lead SO Package
Two power-down modes are available in the LTC1277. In
Nap mode, the LTC1277 draws only 180µA and the instant
wake-up from Nap mode allows the LTC1277 to be powered down even during brief inactive periods. In Sleep
mode only 1µA will be drawn. A REFRDY signal is used to
show the ADC is ready to sample after waking up from
Sleep mode. The LTC1274 also provides the Sleep mode
and REFRDY signal.
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APPLICATI
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S
Battery-Powered Portable Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
The A/D converters convert 0V to 4.096V unipolar inputs
from a single 5V supply or ±2.048V bipolar inputs from
±5V supplies.
The LTC1274 has a single-ended input and a 12-bit
parallel data format. The LTC1277 offers a differential
input and a 2-byte read format. The bipolar mode is
formatted as 2’s complement for the LTC1274 and offset
binary for the LTC1277.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATI
Single 5V Supply, 10mW, 100kHz, 12-Bit ADC
LTC1277
5V
VDD
VSS
BUSY
CS
RD
CONVST
HBEN
VLOGIC
D0/8
D1/9
D2/10
D3/11
10000
24
22
21
20
CREF = 4.7µF
+
23
10µF
µP
CONTROL
LINES
19
18
17
16
OPTIONAL 3V SUPPLY
TO INTERFACE WITH 3V
PROCESSOR
15
WITHOUT SLEEP OR NAP
0.1µF
1000
SUPPLY CURRENT (µA)
ANALOG 1 AIN+
DIFFERENTIAL INPUTS 2
AIN–
(0V TO 4.096V)
3
2.42V
VREF
VREF OUTPUT
+
4
AGND
0.1µF
10µF
5
REFRDY
6
SLEEP
7
NAP
8
D7
9
D6
10
D5
8-BIT
11
D4
PARALLEL
12
BUS
DGND
Supply Current vs Sample Rate with
Sleep and Nap Modes
NAP MODE
100
NAP = REFRDY
(SLEEP MODE)
10
NAP = 5V
(SLEEP MODE)
14
13
1
0.1
LTC1274/77 • TA01
1
10
100
1k
10k
100k
SAMPLE RATE (Hz)
LTC1274/77 • TA02
1
LTC1274/LTC1277
W W
W
AXI U
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ABSOLUTE
RATI GS
(Notes 1, 2)
Supply Voltage (VDD) ................................................ 7V
Negative Supply Voltage (VSS)
Bipolar Operation Only .......................... – 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation............... VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)
Unipolar Operation .............................. – 0.3V to 12V
Bipolar Operation.......................... VSS – 0.3V to 12V
Digital Output Voltage
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation...................... – 0.3V to VDD + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER
PART NUMBER
TOP VIEW
ORDER
PART NUMBER
VREF
2
23 VSS
AIN+
AIN–
2
23 VSS
AGND
3
22 BUSY
VREF
3
22 BUSY
D11 (MSB)
4
21 CS
AGND
4
21 CS
D10
5
20 RD
REFRDY
5
20 RD
D9
6
19 CONVST
SLEEP
6
19 CONVST
D8
7
18 SLEEP
NAP
7
18 HBEN
D7
8
17 REFRDY
D7
8
D6
9
16 D0
D6
9
17 VLOGIC
16 D0/8
D5 10
15 D1
D5 10
15 D1/9
D4 11
14 D2
D4 11
14 D2/10
DGND 12
13 D3
DGND 12
AIN
1
24 VDD
LTC1274CSW
LTC1274ISW
1
24 VDD
LTC1277CSW
LTC1277ISW
13 D3/11
(D11 = MSB)
SW PACKAGE
24-LEAD PLASTIC SO WIDE
SW PACKAGE
24-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 130°C/W
TJMAX = 110°C, θJA = 130°C/W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
●
Resolution (No Missing Codes)
Integral Linearity Error
With Internal Reference (Notes 5, 6)
(Note 7)
Differential Linearity Error
TYP
12
Bits
±1
LSB
●
±1
LSB
●
±6
±8
LSB
LSB
●
±8
±10
LSB
LSB
±20
LSB
±45
ppm/°C
(Note 8)
Gain Error
Gain Error Tempco
2
IOUT(REF) = 0
UNITS
●
Unipolar Offset Error
Bipolar Offset Error
MAX
●
±10
LTC1274/LTC1277
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A ALOG I PUT
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 10)
4.75V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar)
●
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
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DY A IC ACCURACY
MIN
TYP
MAX
0 to 4.096
±2.048
UNITS
V
V
±1
45
5
µA
pF
pF
(Notes 5, 9)
SYMBOL PARAMETER
CONDITIONS
S/(N + D) Signal-to-Noise
Plus Distortion Ratio
50kHz Input Signal
100kHz Input Signal
●
THD
Total Harmonic Distortion
Up to 5th Harmonic
50kHz Input Signal
100kHz Input Signal
●
– 84
– 82
– 76
dB
dB
Peak Harmonic or
Spurious Noise
50kHz Input Signal
100kHz Input Signal
●
– 84
– 82
– 76
dB
dB
Intermodulation Distortion
fa = 96.95kHz, fb = 97.68kHz
IMD
TYP
70
73
72.5
2nd Order Terms
3rd Order Terms
MAX
UNITS
dB
dB
– 78
– 81
dB
dB
Full Power Bandwidth
2
MHz
Full Linear Bandwidth
[S/(N + D) ≥ 68dB]
350
kHz
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I TER AL REFERE CE CHARACTERISTICS
PARAMETER
(Note 5)
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
VREF Load Regulation
– 5mA ≤ IOUT ≤ 70µA
TYP
MAX
2.400
2.420
2.440
±10
±45
0.01
0.01
CONDITIONS
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage, All Logic Outputs
MIN
●
VLOGIC = 2.7V (LTC1277)
IO = – 10µA
IO = – 200µA
VDD = 4.75V
IO = 160µA
IO = 1.6mA
VLOGIC =2.7V (LTC1277)
IO = 160µA
IO = 1.6mA
V
ppm/°C
LSB/mA
(Note 5)
VIH
VDD = 4.75V
IO = – 10µA
IO = – 200µA
UNITS
LSB/V
LSB/V
2
SYMBOL PARAMETER
Low Level Output Voltage,
All Logic Outputs
MIN
●
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DIGITAL I PUTS A D DIGITAL OUTPUTS
VOL
MIN
●
TYP
MAX
2.4
UNITS
V
0.8
V
±10
µA
5
pF
4.70
V
V
2.65
2.60
V
V
4.0
0.05
0.10
0.05
0.10
0.4
V
V
V
V
3
LTC1274/LTC1277
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DIGITAL I PUTS A D DIGITAL OUTPUTS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
IOZ
High-Z Output Leakage D11 to D0/8
VOUT = 0V to VDD, CS High
●
COZ
High-Z Output Capacitance D11 to D0/8
CS High (Note 10)
●
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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POWER REQUIRE E TS
MIN
TYP
MAX
UNITS
±10
µA
15
pF
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage (Notes 11, 12)
Unipolar and Bipolar Mode
4.75
VLOGIC
Logic Supply (Notes 11,12)
Unipolar and Bipolar Mode (LTC1277)
VSS
Negative Supply Voltage (Note 11)
Bipolar Mode Only
IDD
Positive Supply Current
fSAMPLE = 100ksps
NAP = 0V (LTC1277 Only)
SLEEP = 0V
●
●
●
2
180
0.3
4
320
5
mA
µA
µA
ISS
Negative Supply Current
fSAMPLE = 100ksps, Bipolar Mode Only
SLEEP = 0V
●
●
40
0.3
70
5
µA
µA
PDISS
Power Dissipation
fSAMPLE = 100ksps
NAP = 0V (LTC1277 Only)
SLEEP = 0V (Unipolar/Bipolar)
●
●
●
10
0.9
20
1.8
25/50
mW
mW
µW
TYP
MAX
UNITS
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TI I G CHARACTERISTICS
TYP
MAX
UNITS
5.25
V
2.7 to 5.25
– 2.45
V
– 5.25
V
(Note 5) See Figures 13 to 17.
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
(Note 11)
MIN
tCONV
Conversion Time
tACQ
Acquisition Time
t1
CS↓ to RD↓ Setup Time
(Note 10)
●
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Note 10)
●
30
ns
t3
NAP↑ to CONVST↓ Wake-Up Time
(LTC1277 Only) (Note 11)
t4
CONVST Low Time
(Note 13)
●
40
t5
CONVST↓ to BUSY↓ Delay
CL = 100pF
●
t6
Data Ready Before BUSY↑
CL = 100pF
●
t7
Delay Between Conversions
(Note 11)
●
t8
Wait Time RD↓ After BUSY↑
(Note 10)
●
t9
Data Access Time After RD↓
CL = 20pF (Note 10)
●
100
●
●
ksps
6
8
0.35
2
620
CL = 100pF
●
20
20
ns
ns
2
µs
ns
50
110
140
ns
ns
65
125
170
ns
ns
60
90
100
ns
ns
●
Bus Relinquish Time
150
– 20
●
t10
ns
65
0.35
CL = 100pF
µs
ns
70
20
µs
t11
RD Low Time
(Note 10)
●
t9
ns
t12
CONVST High Time
(Notes 10, 13)
●
40
ns
t13
Aperture Delay of Sample-and-Hold
35
ns
t14
SLEEP↑ to REFRDY↑ Wake-Up Time 10µF Bypass at VREF Pin
4.7µF Bypass at VREF Pin
4.2
3.3
ms
ms
t15
HBEN↑ to High Byte Data Valid
4
CL = 100pF (LTC1277 Only)
●
35
100
ns
LTC1274/LTC1277
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TI I G CHARACTERISTICS
(Note 5) See Figures 13 to 17.
SYMBOL
PARAMETER
CONDITIONS
t16
HBEN↓ to Low Byte Data Valid
CL = 100pF (LTC1277 Only)
●
t17
HBEN↑ to RD↓ Setup Time
(Note 10) (LTC1277 Only)
●
10
ns
t18
RD↑ to HBEN↓ Setup Time
(Note 10) (LTC1277 Only)
●
10
ns
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together and VLOGIC is tied to VDD in LTC1277 (unless
otherwise noted).
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VDD, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below VSS (ground for
unipolar mode) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.
Note 5: VDD = 5V (VSS = – 5V for bipolar mode), VLOGIC = VDD (LTC1277),
fSAMPLE = 100ksps, tr = tf = 5ns unless otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
MIN
TYP
MAX
UNITS
45
100
ns
Note 8: For LTC1274, bipolar offset is the offset voltage measured from
– 0.5LSB when the output code flickers between 0000 0000 0000 and
1111 1111 1111. For LTC1277, bipolar offset voltage is measured from
– 0.5LSB when the output code flickers between 0111 1111 1111 and
1000 0000 0000.
Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10: Guaranteed by design, not subject to test.
Note 11: Recommended operating conditions.
Note 12: AIN must not exceed VDD or fall below VSS by more than 50mV to
specified accuracy.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (i.e., before the first bit decision) or
after BUSY rises (i.e., after the last bit test). See timing diagrams Modes
1a and 1b (Figures 13, 14).
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
0.50
0
–0.50
1.00
12
fSAMPLE = 100kHz
EFFECTIVE NUMBER OF BITS (ENOBs)
DIFFERENTIAL NONLINEARITY ERROR (LSB)
fSAMPLE = 100kHz
0.50
0
–0.50
–1.00
–1.00
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1274/77 • TPC01
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1274/77 • TPC02
74
11
10
9
68
NYQUIST
FREQUENCY
62
56
8
50
7
6
5
4
S/(N + D)(dB)
INTEGRAL NONLINEARITY ERROR (LSB)
1.00
ENOBs and S/(N + D) vs
Input Frequency
3
2
1
0
10k
fSAMPLE = 100kHz
100k
INPUT FREQUENCY (Hz)
1M
2M
LTC1274/77 • TPC03
5
LTC1274/LTC1277
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
80
70
VIN = – 20dB
50
40
30
20
VIN = – 60dB
10
50
40
30
100k
INPUT FREQUENCY (Hz)
1M
–60
2ND HARMONIC
–80
THD
3RD HARMONIC
–100
fSAMPLE = 100kHz
0
10k
2M
–40
20
10
fSAMPLE = 100kHz
0
10k
–20
60
DISTORTION (dB)
SIGNAL-TO-NOISE RATIO (dB)
SIGNAL/(NOISE + DISTORTION)(dB)
60
0
fSAMPLE = 100kHz
VIN = 0dB
70
100k
INPUT FREQUENCY (Hz)
LTC1274/77 • TPC04
1M
2M
–120
10k
100k
INPUT FREQUENCY (Hz)
LTC1274/77 • TPC05
Spurious-Free Dynamic Range vs
Input Frequency
1M
2M
LTC1274/77 • TPC06
Intermodulation Distortion Plot
0
0
SPURIOUS-FREE DYNAMIC RANGE (dB)
Distortion vs Input Frequency
80
fSAMPLE = 100kHz
fa = 9.54kHz
fb = 9.79kHz
fSAMPLE = 100kHz
–10
–20
–20
AMPLITUDE (dB)
–30
–40
–50
–60
–70
–80
–40
–60
fb – fa
fb – fa
–80
2fb – fa
2fa – fb
2fa – fb
3fa
2fa
fa + 2fb
3fb
2fb
–100
–90
–100
10k
–120
100k
INPUT FREQUENCY (Hz)
1M
2M
10
0
20
30
LTC1274/77 • TPC07
LTC1274/77 • TPC08
Acquistion Time vs
Source Impedance
Intermodulation Distortion Plot
0
3.5
fa
fSAMPLE = 100kHz
fa = 96.948kHz
fb = 97.681kHz
fb
fb – fa
TA = 25°C
3.0
2fb – fa
2fa – fb
2fb fa + fb
2fa
3fb
2fb + fa
2fa + fb
–40
–60
–80
ACQUISITION TIME (µs)
AMPLITUDE (dB)
–20
3fa
–100
2.5
2.0
1.5
1.0
0.5
–120
0
0
10k
20k
FREQUENCY (Hz)
30k
40k
50k
LTC1274/77 • TPC09
6
50
40
FREQUENCY (kHz)
10
100
1k
SOURCE RESISTANCE (Ω)
10k
LTC1274/75 • TPC10
LTC1274/LTC1277
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3.0
fSAMPLE = 100kHz
2.0
1.5
1.0
0.5
0
–55 –25
50
25
75
0
TEMPERATURE (°C)
100
125
0
2.435
fSAMPLE = 100kHz
–10
2.430
–20
–30
–40
DGND (VRIPPLE = 0.1V)
–50
–60 V (V
SS RIPPLE = 10mV)
–70
–80
–100
10
100
RIPPLE FREQUENCY (kHz)
1
2.415
1000
2.405
Supply Current vs
Supply Voltage
8
1000
SUPPLY CURRENT (µA)
1
TA = 25°C
9
WITHOUT SLEEP OR NAP
2.5
1.0
0
10
CREF = 4.7µF
1.5
–3 –2
–1
–4
LOAD CURRENT (mA)
Wake-Up Time vs
CREF (Sleep Mode)
10000
fSAMPLE = 100kHz
2.0
–5
LT1274/77 • TPC13
Supply Current vs Sample Rate
With Sleep and Nap Modes
3.0
–6
LTC1274/77 • TPC12
LT1274/77 • TPC11
SUPPLY CURRENT (mA)
2.420
2.410
AVDD (VRIPPLE = 1mV)
–90
2.425
WAKE-UP TIME (ms)
SUPPLY CURRENT (mA)
2.5
Reference Voltage vs
Load Current
Power Supply Feedthrough vs
Ripple Frequency
REFERENCE VOLTAGE (V)
Supply Current vs Temperature
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
NAP MODE
100
NAP = REFRDY
(SLEEP MODE)
10
NAP = 5V
(SLEEP MODE)
0.5
7
6
5
4
3
2
1
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
1
0.1
1
10
100
1k
10k
100k
SAMPLE RATE (Hz)
LTC1274/77 • TPC14
LTC1274/77 • TPC15
0
0
5
10 15 20 25 30 35 40 45 50
CREF (µF)
LTC1274/77 • TPC16
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PI FU CTIO S
LTC1274
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
AIN (Pin 1): Analog Input. 0V to 4.096V, unipolar (VSS =
0V) or ±2.048V, bipolar (VSS = – 5V).
REFRDY (Pin 17): Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic). VREF can be
overdriven positive with an external reference voltage.
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 4 to 11): Three-State Data Outputs. D11
is the Most Significant Bit.
SLEEP (Pin 18): SLEEP Mode Input. Tie this pin to low to
put the ADC in Sleep mode and save power (REFRDY will
go low). The device will draw 1µA in this mode.
CONVST (Pin 19): Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low.)
DGND (Pin 12): Digital Ground.
7
LTC1274/LTC1277
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PI FU CTIO S
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
D7 to D4* (Pins 8 to 11): Three-State Data Outputs.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
D3/11 to D0/8* (Pins 13 to 16): Three-State Data Outputs.
D11 is the Most Significant Bit.
BUSY (Pin 21): The BUSY output shows the converter
status. It is low when a conversion is in progress. The
rising Busy edge can be used to latch the conversion
result.
VLOGIC (Pin 17): 5V or 3V Digital Power Supply. This pin
allows a 5V or 3V logic interface with the processor. All
logic outputs (Data Bits, BUSY and REFRDY) will swing
between 0V and VLOGIC.
VSS (Pin 23): Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
HBEN (Pin 18): High Byte Enable Input. The four Most
Significant Bits will appear at Pins 13 to 16 when this pin
is high. The LTC1277 uses straight binary for unipolar
mode and offset binary for bipolar mode.
VDD (Pin 24): Positive 5V Supply. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
LTC1277
AIN+ (Pin 1): Positive Analog Input. (AIN+ – AIN–) = 0V to
4.096V, unipolar (VSS = 0V) or ±2.048V, bipolar (VSS = –5V).
AIN– (Pin 2): Negative Analog Input. This pin needs to be
free of noise during conversion. For single-ended inputs
tie AIN– to analog ground.
VREF (Pin 3): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic). VREF can be
overdriven positive with an external reference voltage.
AGND (Pin 4): Analog Ground.
REFRDY (Pin 5): Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
SLEEP (Pin 6): SLEEP Mode Input. Tie this pin to low to put
the ADC in Sleep mode and save power (REFRDY will go
LOW). The device will draw 1µA in this mode.
NAP (Pin 7): NAP Mode Input. Pulling this pin low will shut
down all currents in the ADC except the reference. In this
mode the ADC draws 180µA. Wake-up from Nap mode is
about 620ns.
*The LTC1277 bipolar mode is in offset binary.
8
DGND (Pin 12): Digital Ground.
CONVST (Pin 19): Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low).
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.
VSS (Pin 23): Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
VDD (Pin 24): 5V Positive Supply. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
Table 1. LTC1277 Two-Byte Read Data Bus Status
DATA
OUTPUTS
D7
D6
D5
D4
D3/11
D2/10
Low Byte
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High Byte
Low
Low
Low
Low
DB11
DB10
DB9
DB8
D1/9 D0/8
LTC1274/LTC1277
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LTC1274
CSAMPLE
VDD
AIN
ZEROING SWITCHES
VREF
VSS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
2.42V REF
REFRDY
COMPARATOR
12-BIT CAPACITIVE DAC
AGND
DGND
12
SUCCESSIVE APPROXIMATION
REGISTER
INTERNAL
CLOCK
D11
•
•
•
OUTPUT LATCHES
D0
CONTROL LOGIC
LTC1274 • BD
SLEEP
CONVST
RD
CS
BUSY
LTC1277
CSAMPLE
AIN+
VDD
AIN–
VREF
ZEROING SWITCHES
VSS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
2.42V REF
REFRDY
COMPARATOR
12-BIT CAPACITIVE DAC
AGND
DGND
12
SUCCESSIVE APPROXIMATION
REGISTER
INTERNAL
CLOCK
•
•
•
•
•
OUTPUT LATCHES
D7
D1/9
D0/8
CONTROL LOGIC
LTC1277 • BD
HBEN SLEEP NAP CONVST RD CS
BUSY
VLOGIC
3V OR 5V
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
3k
3k
DBN
DBN
DBN
3k
CL
DGND
A) HIGH-Z TO VOH (t9)
AND VOL TO VOH (t6)
CL
DGND
B) HIGH-Z TO VOL (t9)
AND VOH TO VOL (t6)
DBN
10pF
3k
DGND
A) VOH TO HIGH-Z
10pF
DGND
B) VOL TO HIGH-Z
1274/77 • TC02
1274/77 • TC01
9
LTC1274/LTC1277
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TI I G DIAGRA S
CS to CONVST Setup Timing
CS to RD Setup Timing
CS
CS
t1
t2
RD
CONVST
LTC1274/77 • TD01
LTC1274/77 • TD02
SLEEP to REFRDY Wake-Up Timing
NAP to CONVST Wake-Up Timing (LTC1277)
NAP
SLEEP
t3
t14
CONVST
REFRDY
LTC1274/77 • TD03
LTC1274/77 • TD04
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CONVERSION DETAILS
The LTC1274/LTC1277 use a successive approximation
algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADCs
are complete with a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit
(MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN (LTC1274) or AIN+ (LTC1277) input connects to the sample-and-hold capacitor during the acquire
phase, and the comparator offset is nulled by the feedback
switch. In this acquire phase, a minimum delay of 2µs will
provide enough time for the sample-and-hold capacitor to
acquire the analog signal. During the convert phase, the
comparator feedback switch opens, putting the comparator
into the compare mode. The input switch connects CSAMPLE
to ground (LTC1274) or AIN– (LTC1277), injecting the
analog input charge onto the summing junction. This input
charge is successively compared with the binary-weighted
10
charges supplied by the capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the DAC output balances the AIN (LTC1274) or
AIN+ – AIN– (LTC1277) input charge. The SAR contents (a 12bit data word) which represent the AIN (LTC1274) or
AIN+ – AIN– (LTC1277) are loaded into the 12-bit output latches.
SAMPLE
SAMPLE
CSAMPLE
SI
–
AIN
HOLD
COMPARATOR
CDAC
DAC
+
VDAC
S
A
R
12-BIT
LATCH
1274 • F01
Figure 1. LTC1274 AIN Input
DYNAMIC PERFORMANCE
The LTC1274/LTC1277 have excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADCs’ frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
LTC1274/LTC1277
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using an FFT algorithm, the ADCs’ spectral content can be
examined for frequencies outside the fundamental. Figures
2a and 2b show typical LTC1274 FFT plots.
0
AMPLITUDE (dB)
68
NYQUIST
FREQUENCY
10
9
62
56
8
50
7
6
5
4
3
2
1
fSAMPLE = 100kHz
0
10k
100k
INPUT FREQUENCY (Hz)
1M
2M
LTC1274/77 • F03
Figure 3. ENOBs and S/(N + D) vs Input Frequency
fSAMPLE = 100kHz
fIN = 48.85kHz
–20
74
11
S/(N + D)(dB)
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band
limited to frequencies above DC and below half the sampling frequency. Figure 2a shows a typical spectral content
with a 100kHz sampling rate and a 48.85kHz input. The
dynamic performance is excellent for input frequencies well
beyond Nyquist as shown in Figure 2b and Figure 3.
EFFECTIVE NUMBER OF BITS (ENOBs)
Signal-to-Noise Ratio
12
–40
Effective Number of Bits
–60
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–80
–100
–120
0
10
20
30
40
INPUT FREQUENCY (kHz)
50
LTC1274/77 • F02a
Figure 2a. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 50kHz Input Frequency
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 100kHz, the LTC1274/LTC1277 maintain very
good ENOBs over 300kHz. Refer to Figure 3.
0
fSAMPLE = 100kHz
fIN = 97.68kHz
AMPLITUDE (dB)
–20
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling
frequency. THD is expressed as:
–40
–60
–80
–100
THD = 20log
–120
0
10
20
30
40
INPUT FREQUENCY (kHz)
50
LTC1274/77 • F02b
Figure 2b. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 100kHz Input Frequency
√V22 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input fre-
11
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quency is shown in Figure 4. The ADCs have good distortion performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of the
2nd order IMD products can be expressed by the following
formula:
IMD (fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 97kHz input.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
fSAMPLE = 100kHz
fa
–20
–20
–40
–40
AMPLITUDE (dB)
DISTORTION (dB)
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1274/LTC1277 have been designed to optimize input
bandwidth, allowing ADCs to undersample input signals
with frequencies above the converter’s Nyquist frequency.
The noise floor stays very low at high frequencies;
S/(N + D) becomes dominated by distortion at frequencies
far beyond Nyquist.
Driving the Analog Input
The analog input of the LTC1274/LTC1277 is easy to
drive. It draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During conversion the analog input draws only a
small leakage current. The only requirement is that the
amplifier driving the analog input must settle after the
small current spike before the next conversion starts.
Any op amp that settles in 2µs to small current transients
will allow maximum speed operation. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions. Suitable devices capable of
driving the ADC AIN input include the LT ®1006, LT1007,
LT1220, LT1223 and LT1224 op amps.
0
0
–60
2ND HARMONIC
–80
Full-Power and Full-Linear Bandwidth
THD
fb – fa
2fb – fa
2fa – fb
2fb fa + fb
2fa
3fb
2fb + fa
2fa + fb
–60
–80
3fa
3RD HARMONIC
–100
–120
10k
fSAMPLE = 100kHz
fa = 96.948kHz
fb = 97.681kHz
fb
–100
–120
100k
INPUT FREQUENCY (Hz)
1M
2M
0
10k
20k
30k
FREQUENCY (Hz)
LTC1274/77 • F04
Figure 4. Distortion vs Input Frequency
12
40k
50k
LTC1274/77 • F05
Figure 5. Intermodulation Distortion
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LTC1277 AIN+/AIN– Input Settling
The input capacitor for the LTC1277 is switched onto the
AIN+ input during the sample phase. The voltage on the
AIN+ input must settle completely within the sample
period. At the end of the sample phase the input capacitor
switches to the AIN– input and the conversion starts.
During the conversion the AIN+ input voltage is effectively “held” by the sample-and-hold and will not affect
the conversion result. It is critical that the AIN– input
voltage be free of noise and settles completely during the
conversion.
Internal Reference
The ADCs have an on-chip, temperature compensated,
curvature corrected bandgap reference which is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to
provide up to 1mA current to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
The VREF pin can be driven with a DAC or other means to
provide input span adjustment. The VREF pin must be
driven to at least 2.45V to prevent conflict with the internal
reference. The reference should be driven to no more than
INPUT RANGE:
±0.846VREF(OUT)
IN BIPOLAR MODE
0 TO 1.69VREF(OUT) IN
UNIPOLAR MODE
5V
+
VREF(OUT) ≥ 2.45V
VREF
LT1006
–
LTC1274
AIN
3Ω
10µF
AGND
LTC1274/77 • F06
Figure 6. Driving the VREF with the LT1006 Op Amp
3V to keep the input span within the 5V supply in unipolar
mode. In bipolar mode the reference should be driven to
no more than 5V, the positive supply voltage of the chip.
Figure 6 shows an LT1006 op amp driving the Reference
pin. In unipolar mode, the reference can be driven up to
2.95V at which point it will provide a 0V to 5V input span.
For the bipolar mode, the reference can be driven up to 5V
at which point it will provide a ±4.23V input span. Figure
7 shows a typical reference, the LT1019A-2.5 connected
to the LTC1274. This will provide an improved drift (equal
to the maximum 5ppm/°C of the LT1019A-2.5) and a
±2.115V (bipolar) or 4.231V (unipolar) full scale.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1274/LTC1277, a printed circuit board is required. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC. The analog input
should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in
INPUT RANGE:
±2.115V (±0.846 × VREF)
IN BIPOLAR AND
0V TO 4.231V (1.69VREF(OUT))
IN UNIPOLAR MODE
5V
5V
LTC1274
AIN
VIN
VOUT
LT1019A-2.5
GND
VREF
3Ω
10µF
AGND
LTC1274/77 • F07
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1274 with the LT1019A-2.5
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Figure 8. For bipolar mode, a 0.1µF ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
ground plane at AGND or as close as possible to the ADC.
DGND (Pin 12) and all other analog grounds should be
connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state
during conversion or by using three-state buffers to
isolate the ADC data bus. Figure 9 is a typical application
circuit for the LTC1274.
Input signal leads to AIN and signal return leads from
AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be
kept as short as possible to minimize input noise coupling. In applications where this is not possible a shielded
cable between source and ADC is recommended.
Also, since any potential difference in grounds between
the signal source and the ADC appears as an error voltage
in series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.
A single point analog ground separate from the logic
system ground should be established with an analog
1
AGND
+
ANALOG
INPUT
CIRCUITRY
–
DIGITAL
SYSTEM
LTC1274
AIN
AVDD DVDD DGND
VREF
3
2
10µF
24
0.1µF
10µF
17
12
GROUND CONNECTION
TO DIGITAL CIRCUITRY
0.1µF
LTC1274/77 • F08
ANALOG GROUND PLANE
Figure 8. Power Supply Grounding Practice
2.42V
VREF OUTPUT
+
10µF
LTC1274
ANALOG INPUT 1
(0V TO 4.095V)
VDD
AIN
2
VREF
VSS
3
AGND
BUSY
0.1µF
4
D11 (MSB)
CS
5
D10
RD
6
D9
CONVST
7
D8
SLEEP
8
D7
REFRDY
12-BIT
9
D6
D0
PARALLEL
10
BUS
D5
D1
11
D4
D2
12
DGND
D3
5V
24
+
23
22
21
20
19
18
17
10µF
CONVERSION START INPUT
SLEEP MODE INPUT
REFERENCE READY SIGNAL
16
15
14
13
LTC1274/77 • F09
Figure 9. LTC1274 Typical Circuit
14
0.1µF
µP
CONTROL
LINES
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DIGITAL INTERFACE
The ADCs are designed to interface with microprocessors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
A separate CONVST is used to initiate a conversion.
Figures 10a to 10c are the input/output characteristics of
the ADCs. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB…FS – 1.5LSV). The output code is scaled such
that 1.0LSB = FS/4096 = 4.096V/4096 = 1.0mV.
Unipolar Offset and Full-Scale Error Adjustments
error must be adjusted before full-scale error. Figure 11a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 11b can be used. For zero
offset error, apply 0.50mV (i.e., 0.5LSB) at the input and
adjust the offset trim until the LTC1274/LTC1277 output
code flickers between 0000 0000 0000 and 0000 0000
0001. For zero full-scale error, apply an analog input of
4.0945V (i.e., FS – 1.5LSB or last code transition) at the
input and adjust R5 until the ADC output code flickers
between 1111 1111 1110 and 1111 1111 1111.
Bipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important, then
offset and full-scale errors can be adjusted to zero. Offset
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
1LSB = FS = 4.096V = 1mV
4096
4096
111...111
011...111
111...110
BIPOLAR
ZERO
011...110
OUTPUT CODE
111...100
UNIPOLAR
ZERO
000...011
000...001
000...000
111...111
111...110
000...010
100...001
000...001
100...000
1LSB = FS = 4.096V = 1mV
4096
4096
000...000
0V
1
LSB
FS – 1LSB
–FS/2
INPUT VOLTAGE (V)
LTC1274/77 F10a
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
LTC1274/77 • F10b
Figure 10a. LTC1274/LTC1277 Unipolar
Transfer Characteristics
Figure 10b. LTC1274 Bipolar Transfer
Characteristics (2’s Complement)
111...111
BIPOLAR
ZERO
111...110
OUTPUT CODE
OUTPUT CODE
111...101
100...001
100...000
011...111
011...110
000...001
1LSB = FS = 4.096V = 1mV
4096
4096
000...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
LTC1274/77 • F10c
Figure 10c. LTC1277 Bipolar Transfer Characteristics
(Offset Binary)
15
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adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset adjust while
the input voltage is 0.5LSB below ground. This is done by
applying an input voltage of – 0.50mV (– 0.5LSB) to the
input in Figure 11c and adjusting the R8 until the ADC’s
output code flickers between 0000 0000 0000 and 1111
1111 1111 in LTC1274 or between 0111 1111 1111 and
1000 0000 0000 in LTC1277. For full-scale adjustment, an
input voltage of 2.0465V (FS – 1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111 in LTC1274
or between 1111 1111 1110 and 1111 1111 1111 in
LTC1277.
Internal Clock
The A/D converters have an internal clock that eliminates
the need of synchronization between the external clock
and the CS and RD signals found in other ADCs. The
internal clock is factory trimmed to achieve a typical
conversion time of 6µs. No external adjustments are
required and with the maximum acquisition time of 2µs
throughput performance of 100ksps is assured.
R1
50Ω
+
V1
AIN (LTC1274)
AIN+ (LTC1277)
A1
–
R4
100Ω
R2
10k
R3
10k
LTC1274
LTC1277
FULL-SCALE
ADJUST
AGND
AIN– (LTC1277)
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
LTC1274/77 F11a
Figure 11a. Full-Scale Adjust Circuit
ANALOG
INPUT
0V TO
4.096V
R1
10k
+
R2
10k
R4
100k
–
10k
AIN (LTC1274)
AIN+ (LTC1277)
5V
R9
20Ω
R3
100k
R5
4.3k
FULL-SCALE
ADJUST
5V
R7
R8
100k
10k
LTC1274
LTC1277
AIN– (LTC1277)
LTC1274/77 F11b
OFFSET
ADJUST
R6
400Ω
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs in the LTC1274: CS, CONVST and
RD. For the LTC1277 there are four digital inputs: CS,
CONVST, RD and HBEN. Figure 12 shows the logic
structure associated with these inputs for LTC1277. A
falling edge on CONVST will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output and this
is low while conversion is in progress. The High Byte
Enable input (HBEN) in the LTC1277 is to multiplex the 12
bits of conversion data onto the lower D7 to D0/8
outputs.
Figures 13 through 17 show several different modes of
operation. In modes 1a and 1b (Figures 13 and 17) CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
16
Figure 11b. LTC1274/LTC1277 Unipolar Offset and
Full-Scale Adjust Circuit
ANALOG
INPUT
R1
10k
+
R2
10k
R4
100k
–
R3
100k
R6
200Ω
R5
4.3k
FULL-SCALE
ADJUST
5V
R7
R8
100k
20k
OFFSET
ADJUST
–5V
AIN (LTC1274)
AIN+ (LTC1277)
LTC1274
LTC1277
AIN– (LTC1277)
Figure 11c. LTC1274/LTC1277 Bipolar Offset and
Full-Scale Adjust Circuit
LTC1274/77 F11c
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The narrow logic pulse on CONVST ensures that CONVST
doesn’t return high during the conversion (see Note 13
following the Timing Characteristics table).
In Mode 2 (Figure 15) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
both are in three-state until read by the MPU with the RD
signal. Mode 2 can be used for operation with a shared
MPU databus.
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In slow memory and ROM modes (Figures 16 and 17) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In ROM mode the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the
previous conversion result. After the conversion is complete, the processor can read the new result and initiate
another conversion.
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
RD
BUSY
CS
D
CONVERSION
START (RISING
EDGE TRIGGER)
Q
FLIP
FLOP
CONVST
NAP
CLEAR
SLEEP
1274/77 • F12
Figure 12. Internal Logic for Control Inputs CS, RD, CONVST, NAP and SLEEP (LTC1277)
t16
CS = RD = 0
HBEN (LTC1277)
tCONV
CONVST
t15
t4
(SAMPLE N)
(SAMPLE N + 1)
t5
t7
BUSY
t6
LTC1274 DATA
DATA (N – 1)
DB11 TO DB0
LTC1277 DATA
DATA (N – 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA N
DB11 TO DB8
DATA (N + 1)
DB11 TO DB0
DATA N
DB7 TO DB0
DATA (N + 1)
DB7 TO DB0
LTC1274/77 • F13
Figure 13. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
17
LTC1274/LTC1277
W
U
U
UO
APPLICATI
S I FOR ATIO
CS = RD = 0
t16
HBEN (LTC1277)
t12
tCONV
(SAMPLE N)
CONVST
(SAMPLE N + 1)
t7
t5
t5
BUSY
t6
DATA (N – 1)
DB11 TO DB0
LTC1274 DATA
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
t15
LTC1277 DATA
DATA (N – 1)
DB7 TO DB0
DATA (N – 1)
DB11 TO DB8
DATA (N – 1)
DB7 TO DB0
DATA N
DB7 TO DB0
DATA N
DB11 TO DB8
DATA N
DB7 TO DB0
DATA (N + 1)
DB7 TO DB0
LTC1274/77 • F14
Figure 14. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t17
CS = 0
HBEN (LTC1277)
t4
t12
tCONV
(SAMPLE N)
CONVST
(SAMPLE N + 1)
t5
t7
BUSY
t8
t10
t11
RD
t9
LTC1274 DATA
DATA N
DB11 TO DB0
t16
LTC1277 DATA
DATA N
DB11 TO DB8
DATA N
DB7 TO DB0
LTC1274/77 • F15
Figure 15. Mode 2. CONVST Starts a Conversion. Data is Read by RD
18
LTC1274/LTC1277
W
U
U
UO
APPLICATI
S I FOR ATIO
t15
CS = 0
HBEN (LTC1277)
t7
t18
tCONV
(SAMPLE N)
RD = CONVST
(SAMPLE N + 1)
t5
t10
BUSY
t9
t6
LTC1274 DATA
DATA (N – 1)
DB11 TO DB0
LTC1277 DATA
DATA (N – 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA (N + 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA N
DB11 TO DB8
DATA (N + 1)
DB7 TO DB0
DATA (N + 1)
DB11 TO DB8
LTC1274/77 • F16
Figure 16. Slow Memory Mode
CS = 0
HBEN (LTC1277)
t15
tCONV
t18
(SAMPLE N)
RD = CONVST
(SAMPLE N + 1)
t7
t5
BUSY
t9
LTC1274 DATA
LTC1277 DATA
t10
DATA (N – 1)
DB11 TO DB0
DATA (N – 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA (N – 1)
DB11 TO DB8
DATA N
DB11 TO DB8
LTC1274/77 • F17
Figure 17. ROM Mode Timing
Power Shutdown
The LTC1274/LTC1277 provide shutdown features that
will save power when the ADC is in inactive periods. Both
ADCs have a Sleep mode. To power down the ADCs,
SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to
be driver low. When in Sleep mode, the LTC1274/LTC1277
will not start a conversion even though the CONVST goes
low. The parts draw 1µA. After release from the Sleep
mode, the ADCs need 3ms (4.7µF bypass capacitor on
VREF pin) to wake up and a REFRDY signal will go to high
to indicate the ADC is ready to do conversions.
The LTC1277 has an additional Nap mode. When NAP
(Pin 7) is tied low, all the power is off except the internal
reference which is still active and provides 2.42V output
voltage to the other circuitry. In this mode the ADC draws
0.9mW instead of 10mW (for minimum power, the logic
inputs must be within 600mV from the supply rails). The
wake-up time from the power shutdown to active state is
620ns. The typical performance graph on the front page of
this data sheet shows that the power will be reduced
greatly by using the Sleep and Nap modes.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1274/LTC1277
W
U
U
UO
APPLICATI
S I FOR ATIO
In the Sleep mode, the comparator of the ADC will start
consuming power after the rising edge of SLEEP as shown
in Figure 18a. If REFRDY is tied to NAP, the comparator will
be powered up after REFRDY’s rising edge. Hence more
power will be saved as in Figure 18b.
3ms
(CREF = 4.7µF)
3ms
(CREF = 4.7µF)
SLEEP
SLEEP
REFRDY
NAP = REFRDY
COMPARATOR
STATUS
ON
OFF
ON
COMPARATOR
STATUS
ON
OFF
ON
LTC1274/77 • F18a
Figure 18a. Power Saved in Sleep Mode (NAP = HIGH)
U
PACKAGE DESCRIPTIO
LTC1274/77 • F18b
Figure 18b. Power Saved in Sleep Mode (NAP = REFRDY)
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.598 – 0.614*
(15.190 – 15.600)
0.291 – 0.299**
(7.391 – 7.595)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.037 – 0.045
(0.940 – 1.143)
24
23
22
21
20
19
18
17
16
15
14
13
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.014 – 0.019
0.016 – 0.050
(0.356 – 0.482)
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
9
10
11
12
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1273/75/76
12-Bit, 300ksps Sampling A/D Converters with Reference
Complete with Clock, Reference
LTC1278
12-Bit, 500ksps Sampling A/D Converter with Shutdown
70dB SINAD at Nyquist, Low Power
LTC1279
12-Bit, 600ksps Sampling A/D Converter with Shutdown
70dB SINAD at Nyquist, Low Power
LTC1282
12-Bit, 140ksps Sampling A/D Converter with Reference
3V or ±3V ADC with Reference, Clock
LTC1409
12-Bit, 800ksps Sampling A/D Converter with Shutdown
Fast, Complete Low Power ADC, 80mV
LTC1410
12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
Fast, Complete Wideband ADC, 160mV
20
Linear Technology Corporation
LT/GP 1195 10K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
© LINEAR TECHNOLOGY CORPORATION 1995
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