LANSDALE ML145145VP 4-bit data bus input pll frequency synthesizer Datasheet

ML145145
4–Bit Data Bus Input PLL
Frequency Synthesizer
INTERFACES WITH SINGLE–MODULUS PRESCALERS
Legacy Device: Motorola MC145145-2
The ML145145 is programmed by a 4–bit input, with
strobe and address lines. The device features consist of a
reference oscillator, 12–bit programmable reference
divider, digital phase detector, 14–bit programmable
divide–by–N counter, and the necessary latch circuitry for
accepting the 4–bit input data.
P DIP 18 = VP
PLASTIC DIP
CASE 707
18
1
SOG 20 = -6P
SOG PACKAGE
CASE 751D
20
• Operating Temperature Range: TA – 40 to 85°C
• Low Power Consumption Through the Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• Single Modulus 4–Bit Data Bus Programming
• ÷N Range = 3 to 16,383, ÷R Range = 3 to 4,095
• “Linearized” Digital Phase Detector Enhances
Transfer Function Linearity
• Two Error Signal Options:
Single–Ended (Three–State)
Double–Ended
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
LANSDALE
PACKAGE
P DIP 18
MC145145P1
ML145145VP
SOG 20
MC145145DW2 ML145145-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENTS
PLASTIC DIP
BLOCK DIAGRAM
REFout
OSCin
12–BIT R COUNTER
OSCout
D0
D1
D2
D3
A0
A1
A2
LATCH 4
LATCH 5
LATCH 6
fR
LATCH
CONTROL
CIRCUITRY
fV
PHASE
DETECTOR
A
LATCH 0
LATCH 1
LATCH 2
L3
PHASE
DETECTOR
B
1
18
D2
D0
2
17
D3
fin
3
16
REFout
VSS
4
15
φR
VDD
5
14
φV
OSCin
6
13
LD
OSCout
7
12
PDout
A0
8
11
ST
A1
9
10
A2
LD
SOG PACKAGE
PDout
LATCHES
ST
fin
LOCK
DETECT
D1
φV
φR
14–BIT N COUNTER
D1
1
20
D2
D0
2
19
D3
NC
3
18
REFout
fin
4
17
φR
VSS
5
16
φV
VDD
6
15
LD
OSCin
7
14
PDout
OSCout
8
13
ST
A0
9
12
A2
A1
10
11
NC
NC = NO CONNECTION
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PIN DESCRIPTIONS
latch, the falling edge of strobe latches data into the latch. This
pin should normally be held low to avoid loading latches with
invalid data.
INPUT PINS
D0 – D3
Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19)
Information at these inputs is transferred to the internal
latches when the ST input is in the high state. D3 is most signigicant bit.
f in
Frequency Input (PDIP – Pin 3, SOG – Pin 4)
Input to ÷N portion of synthesizer. f in is typically derived
from the loop VCO and is ac couples. For larger amplitude signals (standard CMOS – logic levels) dc coupling may be used.
OSCin/OSCout
Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG
– Pins 7, 8)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin
may also serve as input for an externally–generated reference
signal. This signal is typically AC coupled to OSCin but for
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external refrence mode, no
connection is required to OSCout.
A0 – A2
Address Inputs (PDIP – Pins 8, 9, 10; SOG – Pins 9, 10, 12)
A0, A1 and A2 are used to define which latch receives the
information on the data input lines. The addresses refer to the
following latches:
OUTPUT PINS
PDout
Single–Ended Phase Detector output (PDIP – Pin 12, SOG
– Pin 14)
Three–state output of phase detector for use as loop–error
signal.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Impedance
State
LD
Lock Detector Signal (PDIP – Pin 13, SOG – Pin 15)
High level when loop is locked (fR, fV of same phase and
frequency). Pulses low when loop is out of lock.
φV, φR
Phase Detect or Outputs (PDIP – Pin 12, SOG – Pin 14)
These phase detector outputs can be combined externally for
a loop–error signal. A single–ended output is also available for
this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency of fV – fR and both are in phase, then both
φV and φR remain high except for a small minimum time period when both pulse low in phase.
REFout
Buffered Reference Output (DIP – Pin 16, SOG – Pin 18)
Buffered output of on–chip reference oscillator or externally
provided reference–input signal.
POWER SUPPLY PINS
ST
Strobe Transfer (PDIP – Pin 11, SOG – Pin 13)
The rising edge of strobe transfers data into the addressed
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VSS
Ground (PDIP – Pin 4, SOG – Pin 5)
Circuit Ground
VDD
Positive Power Supply (PDIP – Pin 5, SOG – Pin 6)
The positive supply voltage may range from 3.0 to 9.0 V
with respect to VSS.
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CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency sytnthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or DC coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct–coupled
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSCin may be used.
OSCout, and unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or similar publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is ac coupled to OSCin. For large amplitude signals (standard CMOS logic levels), DC coupling is used.
OSCout, an unbuffered output, should be left floating. In general, the highest freqency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 7.
For VDD = 5.0 V, the crystal should be specified for a loading capactitanc. CL, which does not exceed 32 pf for frequencies to approximately 8.0 to 15 MHz and 10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping
c–variations in stray and IC input/output capacitance, and realistic CL values. The shunt load capacitance. CL, presented
across the crystal can be estimated to be:
portion of all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and
OSCout pins to minimize distortion, stray capacitance, stray
inductance and startup stablilization time. In some cases, stray
capacitance should be added to the value for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal Re, in Figure 9. The drive level specified by the crystal
manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. R1 in
Figure 7 limits the drive level. The use of R1 may not be necessary in some cases (i.e., R1 = 0 Ω)
To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of
voltage at OSCout. (Care should be taken to minimize loading.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must
be increased in value if the overdriven condition exists. The
user should note that the oscillator start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufactureres have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful (see Table 1).
where
Cin = 5.0 pf (see Figure 8)
Cout = 6.0 pf (see Figure 8)
Ca = 1.0 pf (see Figure 8)
CO = the crystal’s holder capacitance (see Figure 9)
C1 and C2 = external capacitors (see Figure 7)
The oscillator can be “trimmed” on–frequency by making a
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RECOMMENDED READING
Technical Note TN–24, Stated Corp.
Technical Note TN–\7, Stated Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc IEEE, Vol. 57, No. 2 Feb.,
1969
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P.J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
LEGACY APPLICATIONS
The features of the ML145145 permit bus operation with a
dedicated wire needed only for the strobe input. In a micro-
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processor–controlled system this strobe input is accessed when
the PLL is addressed. The remaining data and address inputs
will directly interface to the microprocessor’s data and address
buses.
The ÷ R programability is used to advantage in Figure 10.
Here, the nominal ÷ R value is 3667, but by programming
small changes in this value, fine tuning is accomplised. Better
tuning resolution is achievable with this method than by changing the ÷ N due to the use of the large fixed prescaling value
of ÷ 256 provided by the ML12079.
The two–loop synthesizer, in Figure 11, takes advantage of
these features to control the phase–locked loop with a minumum of dedicated lines while preserving optimal loop performance. Both 25 Hz and 100 Hz steps are provided while the
relatively large reference frequencies of 10 Khz or 10.1 kHz
are maintained.
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OUTLINE DIMENSIONS
P DIP 18 = VP
(ML145145VP)
CASE 707–02
18
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
10
B
1
9
A
L
C
K
N
F
H
D
J
M
SEATING
PLANE
G
DIM
A
B
C
D
F
G
H
J
K
L
M
N
SOG 20W = -6P
(ML145145-6P)
CASE 751D–04
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
G
K
SEATING
PLANE
INCHES
MIN
MAX
0.875 0.915
0.240 0.260
0.140 0.180
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.060
0.008 0.012
0.115 0.135
0.300 BSC
0°
15°
0.020 0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOW ABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
MILLIMETERS
MIN
MAX
22.22 23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
0°
15°
0.51
1.02
X 45°
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0°
7°
0.395
0.415
0.010
0.029
M
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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