Maxim MAX1245AEAP 2.375v, low-power, 8-channel, serial 12-bit adc Datasheet

19-1066; Rev 1; 11/09
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
____________________________Features
The MAX1245 12-bit data-acquisition system combines
an 8-channel multiplexer, high-bandwidth track/hold, and
serial interface with high conversion speed and ultra-low
power consumption. It operates from a single +2.375V to
+3.3V supply, and its analog inputs are software configurable for unipolar/bipolar and single-ended/differential
operation.
♦ Single +2.375V to +3.3V Operation
♦ 8-Channel Single-Ended or 4-Channel
Differential Analog Inputs
♦ Low Power: 0.8mA (100ksps)
10µA (1ksps)
1µA (power-down mode)
♦ Internal Track/Hold, 100kHz Sampling Rate
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP/SSOP Packages
The 4-wire serial interface directly connects to SPI™,
QSPI™, and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1245
works with an external reference, and uses either the
internal clock or an external serial-interface clock to
perform successive-approximation analog-to-digital
conversions.
This device provides a hard-wired SHDN pin and a
software-selectable power-down, and can be programmed to automatically shut down at the end of a
conversion. Accessing the serial interface powers up
the MAX1245, and the quick turn-on time allows it to be
shut down between conversions. This technique can
cut supply current to under 10µA at reduced sampling
rates.
The MAX1245 is available in a 20-pin DIP package and
an SSOP that occupies 30% less area than an 8-pin DIP.
For supply voltages from +2.7V to +5.25V, use the pincompatible MAX147.
________________________Applications
Portable Data Logging
Medical Instruments
Battery-Powered Instruments
Data Acquisition
___________Typical Operating Circuit
+2.5V
0V to
+2.048V
ANALOG
INPUTS
VDD
VDD
CH0
0.1μF
CPU
MAX1245
+2.048V
0.1μF
VREF
CS
SCLK
DIN
DOUT
SSTRB
SHDN
PART*
TEMP RANGE
I/O
SCK (SK)*
MOSI (SO)
MISO (SI)
PIN-PACKAGE
INL
(LSB)
±1/2
MAX1245ACPP
0°C to +70°C
20 Plastic DIP
MAX1245BCPP
0°C to +70°C
20 Plastic DIP
MAX1245ACAP
0°C to +70°C
20 SSOP
20 SSOP
±1
±1/2
±1
MAX1245BCAP
0°C to +70°C
MAX1245AEPP
-40°C to +85°C
20 Plastic DIP
±1/2
MAX1245BEPP
-40°C to +85°C
20 Plastic DIP
±1
MAX1245AEAP
-40°C to +85°C
20 SSOP
±1/2
MAX1245BEAP
-40°C to +85°C
20 SSOP
±1
*Contact factory for availability of alternate surface-mount packages.
___________________Pin Configuration
TOP VIEW
CH0 1
20 VDD
CH1 2
19 SCLK
CH2 3
18 CS
CH3 4
DGND
AGND
COM
CH7
________________Ordering Information
MAX1245
17 DIN
CH4 5
16 SSTRB
CH5 6
15 DOUT
CH6 7
14 DGND
CH7 8
13 AGND
COM 9
12 VDD
SHDN 10
11 VREF
VSS
DIP/SSOP
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1245
________________General Description
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
ABSOLUTE MAXIMUM RATINGS
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C) .............. 889mW
Operating Temperature Ranges
MAX1245_C_P ................................................... 0°C to +70°C
MAX1245_E_P ................................................ -40°C to +85°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
VDD to AGND, DGND .............................................. -0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH7, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V)
VREF to AGND........................................... -0.3V to (VDD + 0.3V)
Digital Inputs to DGND............................................ -0.3V to +6V
Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.375V to +3.3V, COM = 0V, fCLK = 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DC ACCURACY (Note 1)
Resolution
MIN
TYP
MAX
12
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
UNITS
Bits
MAX1245A
±0.5
MAX1245B
±1.0
No missing codes over temperature
LSB
±1
LSB
Offset Error
±0.5
±4
LSB
Gain Error (Note 3)
±0.5
±4
LSB
Gain Temperature Coefficient
±0.25
ppm/°C
Channel-to-Channel Offset
Matching
±0.2
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0Vp-p to 2.048Vp-p, 100ksps, 1.5MHz external clock, bipolar input mode)
Signal-to-Noise + Distortion Ratio
SINAD
68
dB
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Up to the 5th harmonic
-76
76
dB
dB
Channel-to-Channel Crosstalk
50kHz, 2Vp-p (Note 4)
-85
dB
Small-Signal Bandwidth
-3dB rolloff
2.25
MHz
1.0
MHz
Full-Power Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
tCONV
tACQ
Internal clock, SHDN = FLOAT
5.5
7.5
Internal clock, SHDN = VDD
35
65
µs
External clock = 1.5MHz, 12 clocks/conversion
8
2.0
µs
External clock = 1.5MHz
Aperture Delay
40
ns
Aperture Jitter
<50
ps
Internal Clock Frequency
External Clock Frequency
2
SHDN = FLOAT
1.5
SHDN = VDD
Data transfer only
MHz
0.225
0.1
1.5
0
1.5
_______________________________________________________________________________________
MHz
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
(VDD = +2.375V to +3.3V, COM = 0V, fCLK = 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG/COM INPUTS
Input Voltage Range, SingleEnded and Differential (Note 6)
Unipolar, COM = 0V
Multiplexer Leakage Current
On/off leakage current, VIN = 0V or VDD
Input Capacitance
(Note 7)
0 to VREF
Bipolar, COM = VREF/2
±VREF/2
±0.01
±1
16
V
µA
pF
EXTERNAL REFERENCE
VREF Input Voltage Range
(Note 8)
1.0
VREF Input Current
VREF = 2.048V
VREF Input Resistance
82
18
0.01
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
IIN
VIN = 0V or VDD
DIN, SCLK, CS Input Capacitance
CIN
(Note 7)
SHDN Input High Voltage
VINH
SHDN Input Low Voltage
VINL
VIM
SHDN Voltage, Floating
VFLT
SHDN Maximum Allowed Leakage,
Mid Input
kΩ
10
±0.01
V
V
±1
µA
15
pF
VDD - 0.4
V
SHDN = 0V or VDD
VDD/2
- 0.3
SHDN = open
µA
V
0.2
DIN, SCLK, CS Input Leakage
SHDN Input Mid Voltage
µA
0.8
VHYST
IIN
120
2.0
VINL
SHDN Input Current
V
25
Shutdown VREF Input Current
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
VINH
DIN, SCLK, CS Input High Voltage
VDD +
50mV
0.4
V
±4.0
µA
VDD/2
+ 0.3
V
VDD/2
SHDN = open
V
±80
nA
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
VOL
Output Voltage High
VOH
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
Positive Supply Current
Supply Rejection (Note 9)
IL
COUT
ISINK = 5mA
ISOURCE =0.5mA
PSR
0.5
VDD - 0.375
CS = VDD
V
V
±0.01
CS = VDD (Note 7)
VDD
IDD
0.4
ISINK = 16mA
2.375
±10
µA
15
pF
3.3
V
Operating mode, full-scale input
0.8
1.3
mA
Power-down
1.2
10
µA
VDD = 2.375V to 3.3V, full-scale input,
external reference = 2.048V
±0.3
mV
_______________________________________________________________________________________
3
MAX1245
ELECTRICAL CHARACTERISTICS (continued)
TIMING CHARACTERISTICS
(VDD = +2.375V to +3.3V, COM = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
Acquisition Time
CONDITIONS
MIN
tACQ
2.0
DIN to SCLK Setup
tDS
200
DIN to SCLK Hold
tDH
SCLK Fall to Output Data Valid
tDO
Figure 1
CS Fall to Output Enable
tDV
Figure 1
tTR
Figure 2
CS Rise to Output Disable
TYP
MAX
UNITS
µs
ns
20
0
ns
260
ns
240
ns
400
ns
CS to SCLK Rise Setup
tCSS
200
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
300
ns
SCLK Pulse Width Low
tCL
300
SCLK Fall to SSTRB
tSSTRB
ns
Figure 1
260
ns
tSDV
External clock mode only, Figure 1
240
ns
CS Rise to SSTRB Output Disable
tSTR
External clock mode only, Figure 2
400
ns
SSTRB Rise to SCLK Rise
tSCK
Internal clock mode only (Note 7)
CS Fall to SSTRB Output Enable
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
0
ns
Tested at VDD = +2.375V; COM = 0V; unipolar single-ended input mode.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
External reference (VREF = +2.048V), offset nulled.
Ground “on” channel; sine wave applied to all “off” channels.
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
The common-mode range for the analog inputs is from AGND to VDD.
Guaranteed by design. Not subject to production testing.
ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Measured as |VFS(2.375V) - VFS(3.3V)|.
__________________________________________Typical Operating Characteristics
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
RL = ∞
CODE = 101010100000
0.50
0.45
0.40
0.85
0.35
0.75
0.80
INL (LSB)
CLOAD = 50pF
IDD (mA)
1.00
MAX1245-03
RL = ∞
CODE = 101010100000
MAX1245-02
0.90
MAX1245-01
1.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
IDD (mA)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
0.75
CLOAD = 20pF
0.30
0.25
0.20
0.15
0.10
0.70
0.05
0.50
2.375
4
2.625
2.875
VDD (V)
3.125
3.375
0.65
-55
-30
-5
20 45 70 95
TEMPERATURE (°C)
120 145
0.00
2.375
2.625
2.875
VDD (V)
_______________________________________________________________________________________
3.125
3.375
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.35
0.25
0.20
0.30
0.25
0.20
0.15
0.15
0.15
0.10
0.10
0.10
0.05
0.05
0.05
20 45 70 95
TEMPERATURE (˚C)
120 145
0.45
0.35
0.30
0.25
0.20
3.125
0
-55
3.375
0.40
0.35
0.35
0.30
0.25
0.20
0.25
0.20
0.10
0.05
0
-55
-30
-5
VDD (V)
0
2.375
120 145
0.45
0.30
0.25
0.20
0.15
0.40
0.35
0.30
0.25
0.20
0.15
0.35
0.30
0.25
0.20
0.15
0.10
0.10
0.05
0.05
0.05
-55
-30
-5
20
45
70
TEMPERATURE (˚C)
95
120 145
0
2.375
3.375
0.45
0.10
0
3.125
0.50
GAIN MATCHING (LSB)
GAIN MATCHING (LSB)
0.35
2.875
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
0.40
0.40
2.625
VDD (V)
MAX1245-11
0.50
MAX1245-10
0.45
70 95
TEMPERATURE (˚C)
45
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
0.50
20
120 145
0.30
0.05
3.375
95
0.45
0.40
0.05
3.125
70
0.50
0.15
2.875
45
GAIN ERROR
vs. SUPPLY VOLTAGE
0.10
2.625
20
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.10
0
2.375
-5
TEMPERATURE (˚C)
0.15
0.15
-30
VDD (V)
0.45
OFFSET MATCHING (LSB)
0.40
2.875
0.50
MAX1245-07
0.50
2.625
GAIN ERROR (LSB)
-5
MAX1245-08
-30
0
2.375
MAX1245-09
0.20
0.30
MAX1245-12
0.25
OFFSET (LSB)
0.40
0.35
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
GAIN ERROR (LSB)
0.45
0.35
0.30
MAX1245-06
0.45
0.40
0
-55
OFFSET MATCHING (LSB)
MAX1245-05
VDD = 2.375V
OFFSET vs. TEMPERATURE
0.50
0.40
OFFSET (LSB)
INL (LSB)
0.45
OFFSET vs. SUPPLY VOLTAGE
0.50
MAX1245-04
0.50
0
2.625
2.875
VDD (V)
3.125
3.375
-55
-30
-5
20 45 70 95
TEMPERATURE (˚C)
120 145
_______________________________________________________________________________________
5
MAX1245
____________________________Typical Operating Characteristics (continued)
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
____________________________Typical Operating Characteristics (continued)
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
EFFECTIVE NUMBER OF BITS
VDD = VREF = 2.5V
CODE = 101010100000
RL = ∞
IDD (μA)
100
10
8 CHANNELS
1
1 CHANNEL
0.1
MAX1245-14
12.0
MAX1245-13
1000
11.5
11.0
10.5
10.0
0.1
1
10
100
1k
10k
100k
1
10
100
INPUT FREQUENCY (kHz)
CONVERSIONS PER CHANNEL PER SECOND (Hz)
FFT PLOT
INTEGRAL NONLINEARITY
20
0.25
0.20
fTONE = 10ksps
fSAMPLE = 100ksps
0
0.15
-20
AMPLITUDE (dB)
0.10
INL (BITS)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
0.05
0
-0.05
-0.10
-40
-60
-80
-0.15
-100
-0.20
-120
-0.25
0
2048
DIGITAL CODE
6
4096
0
10
20
30
FREQUENCY (kHz)
_______________________________________________________________________________________
40
50
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
PIN
NAME
FUNCTION
1–8
CH0–CH7
9
COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
10
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current;
otherwise, the MAX1245 is fully operational. Letting SHDN float sets the internal clock frequency to 1.5MHz.
Pulling SHDN high sets the internal clock frequency to 225kHz. See Hardware Power-Down section.
11
VREF
External Reference Voltage Input for analog-to-digital conversion
12, 20
VDD
Positive Supply Voltage
13
AGND
Analog Ground
14
DGND
Digital Ground
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CS is high (external clock mode).
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19
SCLK
Sampling Analog Inputs
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
VDD
VDD
DOUT
DOUT
CLOAD
50pF
6k
CLOAD
50pF
DGND
DGND
a) High-Z to VOH and VOL to VOH
6k
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
6k
DOUT
DOUT
CLOAD
50pF
6k
DGND
a) VOH to High-Z
CLOAD
50pF
DGND
b) VOL to High-Z
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________
7
MAX1245
______________________________________________________________Pin Description
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________Detailed Description
The MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a
sample of the signal at IN+.
CS
SCLK
18
19
DIN
17
SHDN
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
VREF
11
2
3
4
5
6
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ = 9 x (RS + RIN) x 16pF
12-BIT CAPACITIVE DAC
VREF
INPUT
SHIFT
REGISTER
INT
CLOCK
CONTROL
LOGIC
CH0
CH1
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
T/H
CLOCK
IN
12-BIT
SAR
ADC
7
8
9
MAX1245
Figure 3. Block Diagram
8
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input, IN+, to the
negative input, IN- (In single-ended mode, IN- is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) (VIN-)] from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
REF
15
16
SSTRB
CH4
CH5
12, 20
14
OUT
CH3
13
VDD
DGND
AGND
CH6
CH7
ZERO
16pF
CH2
DOUT
COMPARATOR
INPUT
CHOLD
MUX –
+
RIN
12k
CSWITCH
TRACK
T/H
SWITCH
COM
HOLD
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
Figure 4. Equivalent Input Circuit
_______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quick Look
To quickly evaluate the MAX1245’s analog performance, use the circuit of Figure 5. The MAX1245
requires a control byte to be written to DIN before each
conversion. Tying DIN to VDD feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conversions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the 12-bit conversion result is
shifted out of DOUT. Varying the analog input to CH7
alters the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a
bit from DIN into the MAX1245’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
The MAX1245 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to
OSCILLOSCOPE
VDD
+2.5V
0.1μF
DGND
MAX1245
SCLK
AGND
COM
0V TO
2.048V
ANALOG
INPUT 0.01μF
CS
CH7
SSTRB
SCLK
+2.5V
DIN
DOUT
2.048V
VREF
SSTRB
SHDN
C1
0.1μF
N.C.
DOUT*
1.5MHz
OSCILLATOR
CH1
CH2
CH3
CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit
_______________________________________________________________________________________
9
MAX1245
where RIN = 12kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 2.0µs. Note
that source impedances below 1kΩ do not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
NAME
DESCRIPTION
BIT
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1
0(LSB)
PD1
PD0
Selects clock and power-down modes.
PD1
PD0
Mode
0
0
Power-down (IQ = 1.2µA)
0
1
Unassigned
1
0
Internal clock mode
1
1
External clock mode
DIF = 1)
Table 2. Channel Selection in Single-Ended Mode (SGL/D
SEL2
0
SEL1
0
SEL0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
CH0
+
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
DIF = 0)
Table 3. Channel Selection in Differential Mode (SGL/D
SEL2
SEL1
SEL0
CH0
CH1
0
0
0
+
–
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
10
–
CH2
CH3
+
–
CH4
CH5
+
–
CH6
CH7
+
–
–
+
+
–
+
–
+
______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 1.5MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
Clock Modes
The MAX1245 may use either an external serial clock or
the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock
shifts data in and out of the MAX1245. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and, simultaneously, receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and, simultaneously, receive byte RB3.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital conversion. SSTRB pulses high for one clock period after
the control byte’s last bit. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of idle time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
CS
tACQ
SCLK
1
4
SEL2 SEL1 SEL0 UNI/
BIP
DIN
8
SGL/ PD1
DIF
12
16
20
24
PD0
START
SSTRB
A/D STATE
B11
MSB
IDLE
RB3
RB2
RB1
DOUT
ACQUISITION
2.0μs
B10
B9
B8
B7
B6
CONVERSION
B5
B4
B3
B2
B1
B0
LSB
FILLED WITH
ZEROS
IDLE
(SCLK = 1.5MHz)
Figure 6. 24-Clock External-Clock-Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fCLK ≤ 1.5MHz)
______________________________________________________________________________________
11
MAX1245
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is two’s-complement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
perform a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the 12-bit
conversion result). See Figure 17 for MAX1245 QSPI
connections.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
•••
CS
tCSH
tCSS
tCL
tCH
SCLK
tCSH
•••
tDS
tDH
•••
DIN
tDV
tDO
tTR
•••
DOUT
Figure 7. Detailed Serial-Interface Timing
•••
CS
•••
tSTR
tSDV
SSTRB
•••
•••
tSSTRB
SCLK
••••
tSSTRB
••• •
PD0 CLOCKED IN
Figure 8. External-Clock-Mode SSTRB Detailed Timing
Internal Clock
In internal clock mode, the MAX1245 generates its own
conversion clock internally. This frees the µP from the
burden of running the SAR conversion clock and allows
the conversion results to be read back at the processor’s convenience, at any clock rate from zero to
1.5MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB will be low for a maximum of 7.5µs (SHDN =
FLOAT), during which time SCLK should remain low for
best noise performance.
12
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1245 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
MAX1245
CS
SCLK
1
2
3
4
5
SEL2 SEL1 SEL0 UNI/
BIP
DIN
7
8
SGL/ PD1
DIF
PD0
6
9
10
11
12
18
19
20
21
22
23
24
START
SSTRB
tCONV
B11
MSB
DOUT
A/D STATE
CONVERSION
7.5μs MAX
(SCLK = 1.5MHz) (SHDN = FLOAT)
ACQUISITION
2.0μs
IDLE
B10
B9
B2
B1
B0
LSB
FILLED WITH
ZEROS
IDLE
Figure 9. Internal Clock Mode Timing
CS • • •
tCONV
tSCK
tCSH
tCSS
SSTRB • • •
tSSTRB
SCLK • • •
tDO
PD0 CLOCK IN
DOUT • • •
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provided that the minimum acquisition time, tACQ, is kept
above 2.0µs.
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after VDD is applied.
Data Framing
If CS is toggled before the current conversion is complete, then the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated,
and a new one is started.
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
OR
The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto the DOUT pin.
______________________________________________________________________________________
13
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
The fastest the MAX1245 can run is 15 clocks per conversion with CS held low between conversions. Figure 11a
shows the serial-interface timing necessary to perform a
conversion every 15 SCLK cycles in external clock mode.
If CS is low and SCLK is continuous, guarantee a start bit
by first clocking in 16 zeros.
Most microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX1245. Figure 11b shows the serial-interface timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT shifts out zeros.
Power-Down
The MAX1245’s automatic power-down mode can save
considerable power when operating at speeds below
the maximum sampling rate. Figure 13 shows the average supply current as a function of the sampling rate.
You can save power by placing the converter in a lowcurrent shutdown state between conversions.
Select power-down via bits 1 and 0 of the DIN control
byte with SHDN high (Tables 1 and 4). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of the control byte (Table 5).
Power-down mode turns off all chip functions that draw
quiescent current, reducing IDD typically to 1.2µA.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1245 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have stabilized, the internal reset time is 10µs, and no conversions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 4, PD1 and PD0
CS
1
8
1
8
1
SCLK
S
DIN
S
CONTROL BYTE 0
CONTROL BYTE 1
CONTROL BYTE 2
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DOUT
S
CONVERSION RESULT 1
CONVERSION RESULT 0
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
•••
SCLK
•••
DIN
DOUT
S
S
CONTROL BYTE 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
•••
CONTROL BYTE 1
B11 B10 B9 B8
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
14
______________________________________________________________________________________
•••
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
MAX1245
CLOCK
MODE
EXTERNAL
EXTERNAL
SHDN
SETS SOFTWARE
POWER-DOWN
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
DOUT
SETS EXTERNAL
CLOCK MODE
S X X X X X 0 0
S X X X X X 1 1
VALID
DATA
12 DATA BITS
12 DATA BITS
HARDWARE
POWERDOWN
POWERED UP
POWERED UP
MODE
INVALID
DATA
SOFTWARE
POWER-DOWN
POWERED UP
Figure 12a. Timing Diagram Power-Down Modes, External Clock
CLOCK
MODE
DIN
INTERNAL
SETS
POWER-DOWN
SETS INTERNAL
CLOCK MODE
S X X X X X 1 0
S X X X X X 0 0
DOUT
S
DATA VALID
DATA VALID
CONVERSION
SSTRB
CONVERSION
SOFTWARE
POWER-DOWN
POWERED UP
MODE
POWERED UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Table 4. Software Power-Down and
Clock Mode
Table 5. Hard-Wired Power-Down and
Internal Clock Frequency
External Clock
SHDN
STATE
DEVICE
MODE
INTERNAL CLOCK
FREQUENCY
Internal Clock
1
Enabled
225kHz
1
Unassigned
Floating
Enabled
1.5MHz
0
Power-Down
0
Power-Down
N/A
PD1
PD0
DEVICE MODE
1
1
1
0
0
0
______________________________________________________________________________________
15
Table 6. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Zero Scale
VREF + COM
COM
also specify the clock mode. When software shutdown is
asserted, the ADC continues to operate in the last specified clock mode until the conversion is complete. Then the
ADC powers down into a low quiescent-current state. In
internal clock mode, the interface remains active and conversion results can be clocked out after the MAX1245 has
entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit, and
powers up the MAX1245. Following the start bit, the data
input word or control byte also determines clock mode
and power-down states. For example, if the DIN word
contains PD1 = 1, the chip remains powered up. If PD0 =
PD1 = 0, a power-down resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike the software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. SHDN also controls the clock
frequency in internal clock mode. Letting SHDN float sets
the internal clock frequency to 1.5MHz. When returning
to normal operation with SHDN floating, there is a tRC
delay of approximately 2MΩ x C L , where C L is the
capacitive loading on the SHDN pin. Pulling SHDN high
sets the internal clock frequency to 225kHz. This feature
eases the settling-time requirement for the reference
voltage.
External Reference
An external reference is required for the MAX1245. The
reference voltage range is 1V to VDD.
At VREF, the input impedance is a minimum of 18kΩ for
DC currents. During a conversion, the reference must
be able to deliver up to 250µA DC load current and
have an output impedance of 10Ω or less. If the reference has higher output impedance or is noisy, bypass
it close to the VREF pin with a 0.1µF capacitor.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes using a 2.048V reference.
The external reference must have a temperature coefficient
of 4ppm/°C or less to achieve accuracy to within 1LSB over
the commercial temperature range of 0°C to +70°C.
16
Positive
Full Scale
VREF/2
+ COM
Zero
Scale
Negative
Full Scale
-VREF/2
+ COM
COM
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
1000
MAX1245-13
Full Scale
VDD = VREF = 2.5V
CODE = 101010100000
RL = ∞
100
IDD (μA)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
10
8 CHANNELS
1
1 CHANNEL
0.1
0.1
1
10
100
1k
10k
100k
CONVERSIONS PER CHANNEL PER SECOND (Hz)
Figure 13. Average Supply Current vs. Conversion Rate
Figure 14 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 15 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 500µV (2.048V /
4096) for unipolar operation and 1LSB = 500µV
[(2.048V / 2 - -2.048V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 16 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at AGND, separate from the logic ground. Connect all other analog
grounds and DGND to the star ground. No other digital
system ground should be connected to this ground.
The ground return to the power supply for the star
______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
MAX1245
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
FS =
011 . . . 110
ZS = COM
11 . . . 110
11 . . . 101
-VREF
+ COM
2
VREF
1LSB =
4096
-FS =
000 . . . 010
000 . . . 001
FS = VREF + COM
ZS = COM
VREF
1LSB =
4096
00 . . . 011
00 . . . 010
VREF
+ COM
2
011 . . . 111
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
00 . . . 001
100 . . . 000
00 . . . 000
0
(COM)
1
2
3
FS
COM
(≤VREF/2)
- FS
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
INPUT VOLTAGE (LSBs)
Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
ground should be low impedance and as short as possible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 4.7µF
capacitors close to pin 20 of the MAX1245. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +2.5V power supply is very noisy, a 10Ω resistor
can be connected as a lowpass filter (Figure 16).
+FS - 1LSB
Figure 15. Bipolar Transfer Function, Full Scale (FS) = VREF /
2 + COM, Zero Scale (ZS) = COM
SUPPLIES
+2.5V
+2.5V
GND
+2.5V
DGND
R* = 10Ω
VDD
AGND
COM DGND
MAX1245
DIGITAL
CIRCUITRY
* OPTIONAL
Figure 16. Power-Supply Grounding Connection
______________________________________________________________________________________
17
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
+2.5V +3V
0.1μF
ANALOG
INPUTS
4.7μF
(POWER SUPPLIES)
1
CH0
VDD 20
2
CH1
SCLK 19
3
CH2
CS 18
PCS0
4
CH3 MAX1245
DIN 17
MOSI
5
CH4
SSTRB 16
6
CH5
DOUT 15
7
CH6
DGND 14
8
CH7
AGND 13
9
COM
VDD 12
10 SHDN
VREF 11
SCK
MC683XX
MISO
(GND)
0.1μF
+2.048V
CLOCK CONNECTIONS NOT SHOWN
Figure 17. MAX1245 QSPI Connections
High-Speed Digital Interfacing with QSPI
The MAX1245 can interface with QSPI using the circuit in
Figure 17 (fSCLK = 1.5MHz, CPOL = 0, CPHA = 0). This
QSPI circuit can be programmed to do a conversion on
each of the eight channels. The result is stored in memory
without taxing the CPU, since QSPI incorporates its own
micro-sequencer.
Because the maximum external clock frequency is
1.5MHz, the MAX1245 is QSPI compatible up to 1.5MHz.
18
______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
CS
XF
SCLK
CLKX
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX1245’s SCLK input.
2) The MAX1245’s CS pin is driven low by the TMS320’s
XF_ I/O port, to enable data to be clocked into the
MAX1245’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1245 to initiate a conversion and place the
device into external clock mode. Refer to Table 1 to
select the proper XXXXX bit values for your specific
application.
4) The MAX1245’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the
MAX1245.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
MAX1245
TMS320LC3x-to-MAX1245 Interface
Figure 18 shows an application circuit to interface the
MAX1245 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 19.
Use the following steps to initiate a conversion in the
MAX1245 and to read the results:
TMS320LC3x
MAX1245
CLKR
DX
DIN
DR
DOUT
FSR
SSTRB
Figure 18. MAX1245-to-TMS320 Serial Interface
6) Pull CS high to disable the MAX1245 until the next
conversion is initiated.
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
DOUT
MSB
B10
B1
LSB
HIGH
IMPEDANCE
Figure 19. TMS320 Serial-Interface Timing Diagram
______________________________________________________________________________________
19
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Chip Information
TRANSISTOR COUNT: 2554
20
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 PDIP
A20-1
21-0056
20 SSOP
P20-4
21-0043
______________________________________________________________________________________
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
REVISION
NUMBER
REVISION
DATE
0
6/96
1
11/09
DESCRIPTION
PAGES
CHANGED
Initial release.
—
Removed the dice package from the Ordering Information table.
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1245
Revision History
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