Rohm BD9845FV-E2 Single/dual-output high-frequency step-down switching regulator(controller type) Datasheet

Large Current External FET Controller Type Switching Regulators
Single/Dual-output
High-frequency Step-down
Switching Regulator(Controller type)
BD9845FV
No.11028EDT08
●Overview
BD9845FV is an IC containing a circuit of switching regulator controller by pulse width modulation system.
This circuit can be used for step-down DC/DC converter operation.
In addition, the package is designed compact, and is optimum for compact power supply for many kinds of equipment.
●Feature
1) High voltage resistance input (Vcc=35V)
2) FET driver circuit is contained (step-down circuit 1 output).
3) Error amplifier reference voltage (1.0V1%) and REG output circuit (2.5V) are contained.
4) Overcurrent detection circuit is contained.
5) Soft start and pause period can be adjusted.
6) Three modes of standby, master, and slave can be switched. (iccs = 0 uA typ in standby mode.)
7) ON/OFF control is enabled independently for each channel. (DT terminal)
●Application
LCD, PDP, PC, AV, Printer, DVD, Projector TV, Fax, Copy machine, Measuring instrument, etc.
●Absolute maximum rating
Item
Symbol
Rating
Unit
Supply voltage
Vcc
36
V
Permissible loss
Pd
500*1
mW
OUT terminal voltage resistance
OUT
Vcc-7V to Vcc
V
C5V terminal voltage resistance
C5V
Vcc-7V to Vcc
V
Operation temperature range
Topr
-40 to +85
°C
Tstg
-55 to +150
°C
Tjmax
150
°C
Storage temperature range
Joint temperature
*1 When glass epoxy board 70.0 mm  70.0 mm  1.6 mm is installed onboard. Reduced by 4.0 mW/C above Ta=25C.
●Operating condition (Ta=25C)
Item
Symbol
Range
Unit
Supply voltage
Vcc
3.6 to 35
V
Output terminal voltage
OUT
C5V – Vcc
V
Timing capacity
CCT
47 to 3000
pF
Oscillation frequency
Fosc
100 to 1500
kHz
STB input voltage
VSTB
0 to Vcc
V
SEL input voltage
VSELTB
0 to Vcc
V
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1/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Electric characteristics (Ta=25C, VCC=6V unless otherwise specified)
Standard value
Item
Symbol
Min.
Typ.
Max.
[VREF output unit]
Output voltage
VREF
2.450
2.500 2.550
Input stability
Line reg.
-
1
10
Load stability
Load reg.
-
2
10
Current capacity
IOMAX
2
13
-
[Triangular wave oscillator]
Oscillation frequency
FOSC
95
106
117
Frequency fluctuation
FDV
-
0
1
[Soft start unit]
SS source current
ISSSO
1.4
2
2.6
SS sink current
ISSSI
5
12
-
[Pause period adjusting circuit]
DT input bias current
IDT
-
0.1
1
DT sink current
IDTSI
1
3.3
-
[Low input malfunction preventing circuit]
Threshold voltage
VUTH
3.0
3.2
3.4
Hysteresis
VUHYS
-
0.15
0.25
[Error amplifier]
Non-inverting input reference voltage
VINV
0.99
1
1.01
Reference voltage supply fluctuation
dVinv
-
1
6
INV input bias current
IIB
-
0
1
Open gain
AV
65
85
-
Max output voltage
VFBH
2.30
-
VREF
Min output voltage
VFBL
-
0.6
1.3
Output sink current
IFBSI
0.5
1.5
-
Output source current
IFBSO
50
105
-
[PWM comparator]
Vt0
1.4
1.5
1.6
Input threshold voltage(fosc=100kHz)
Vt100
1.9
2
2.1
[Output unit]
Output ON resistance H
RONH
-
4.0
10
Output ON resistance L
RONL
-
3.3
10
C5V clamp voltage
VCLMP
4.5
5
5.5
[Overcurrent protection circuit]
Overcurrent detection threshold voltage
VOCPTH
0.04
0.05
0.06
OCP-input bias current
IOCP-
0.1
10
Overcurrent detection delay time
tdocpth
-
200
400
Overcurrent detection minimum
tdocpre
0.8
1.6
-
retention time
[Standby changeover unit]
STB flow-in current
ISTB
55
100
Standby mode setting range
VSTBL
0
0.5
Active (master) mode setting range
VSTBH
3.0
VCC
SEL flow-in current
ISEL
15
30
Master mode setting range
VSELL
0
0.5
Slave mode setting range
VSELH
2.0
VCC
[Device overall]
Standby current
ICCS
-
0
1
Average power consumption
ICCA
1
2.4
4
Unit
Condition
V
mV
mV
mA
IO=0.1 mA
Vcc=3.6 V→35 V
IO=0.1 mA→2 mA
VREF=(typ.)×0.95
kHz
%
CCP=1800 pF
Vcc=3.6 V→35 V
µA
mA
SS=0.5 V
SS=0.5 V
µA
mA
DT=1.75 V
DT=1.75 V, (OCP+)-(OCP-)=0.5 V
V
V
Vcc start detection
V
mV
µA
dB
V
V
mA
µA
INV=FB
Vcc=3.6 V→35 V
INV=1 V
FB=1.25 V, INV=1.5 V
FB=1.25 V, INV=0.5 V
V
V
On duty 0%
On duty 100%
Ω
Ω
V
RONH=(VCC -OUT)/ Iout, Iout=0.1 A
RONL=(OUT-C5 V)/ Iout, Iout=0.1 A
VCLMP= VCC-C5V , VCC >7 V
V
µA
ns
Voltage between(OCP+) and (OCP-)
OCP+= VCC, OCP-= VCC-0.5 V
OCP-= VCC→VCC-0.2 V
ms
OCP-= VCC-0.2 V→VCC
µA
V
V
µA
V
V
STB=6V
µA
mA
STB=0 V
INV=0 V, FB=H, DT=1.75 V
SEL=2.5V
* Radiation resistance design is not applied.
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2/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Reference data
Current: ICCA(mA)
8
7
6
5
4
3
Circuit
2
VCC=6V
0
0
25
50
75
100
7
6
5
Ta=25°C
4
3
2
1
5
Ambient Temperature: Ta(°C)
2.515
Reference Voltage: VREF(V)
2.520
2.515
2.510
Reference Voltage: VREF(V)
10
15
Ta=25°C
2.500
2.495
2.490
2.485
2.480
2.510
25
30
35
10
15
20
25
30
35
2.490
2.485
0.5 1
1.5 2
2.5 3
Loop Gain :Closed [ dB ]
3.2
3.1
3
2.9
2.8
2.7
2.6
25
50
75
100
-90
Phase
-135
20
-180
Gain
-20
125
2.495
2.490
2.485
2.480
Fig.7 UVLO threshold temperature
characteristics
1K
100K
Fr equency [Hz]
1M
50
75
100
125
1.6
1.4
1.2
1.0
0.8
0.6
VCC=6V
0.4
Ta=25℃
0.2
0.0
0
10M
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
ErrAmp Input Voltage: VINV(V)
Fig.8 Error amplifier I/O
characteristics
Fig.9 Error amplifier input current
3.0
1.006
1.004
VCC=6V
1.002
1
0.998
0.996
0.994
0.992
0.99
140
Ta=25°C
Ta=85°C
120
FB Sinkt Current: IFBSI(mA)
FB Source Current: IFBSO(µA)
ErrAmp Reference Voltage: VINV(V)
25
2.0
-225
10K
0
Fig.6 VREF temperature
characteristics
1.01
1.008
-50
-25
Ambient Temperature: Ta(°C)
-270
100
125
1.8
60
Ambient Temperature: Ta(°C)
100
2.500
-50
-45
Phase
0
75
VCC=6V
2.505
0
Gain
40
50
2.510
3.5 4 4.5 5
100
80
25
2.515
Fig.5 VREF current capability
3.3
0
2.520
Reference Output Current: IREF(mA)
3.4
0
-25
Fig.3 Circuit current temperature
characteristics in operation
2.495
0
3.5
-25
1
Ambient Temperature: Ta(°C)
VCC=6V
2.500
40
Fig.4 VREF supply voltage
characteristics
2.5
-50
2
-50
2.480
5
VCC=6V
3
40
Ta=25°C
2.505
Supply Voltage: VCC(V)
UVLO Threshold: VUTH(V)
20
Fig.2 Circuit current in
operation
2.520
0
4
Supply Voltage: VCC(V)
Fig.1 Standby current temperature
characteristics
2.505
5
0
0
0
125
6
Reference Output Voltage: VREF (V)
-25
-50
8
7
ErrAmp Input Current: IIB(µA)
1
8
Phase Shift [ deg ]
Standby Current: ICCS(uA)
9
Circuit Current: ICCA(mA)
10
100
80
Ta=-40°C
60
VCC=6.0V
40
20
0
25
50
75
100
125
0
1
2
3
4
Ambient Temperature: Ta(°C)
ErrAmp Output Voltage: VFB(V)
Fig.10 Error amplifier reference voltage
temperature characteristics
Fig.11 FB output source current
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Ta=85°C
2.0
Ta=25°C
1.5
1.0
Ta=-40°C
0.5
0.0
VCC=6.0V
-0.5
0
-25
2.5
3/15
0
0.5
1
1.5
2
ErrAmp Output Voltage: VFB(V)
Fig.12 FB output sink current
2011.08 - Rev.D
Technical Note
BD9845FV
35
3.5
30
3.0
VCC=6.0V
2.5
2.0
1.5
1.0
0.5
5
Ta=-40°C
Ta=25°C
25
Ta=85°C
20
15
10
VCC=6.0V
5
0.0
0
0.4
0.6
0.8
1
1.2
1.4
1.6
0
0.5
SS Voltage: VSS(V)
DT Input Current: IDT(µA)
CCP=1800pF
Frequency: FOSC(kHz)
2
110
100
VCC=6V
90
0
25
50
7
7
6
6
5
4
3
2
VCC=6.0V
Ta=25°C
1
75
100
-25
2
0.5
1
Output Duty Cycle:Duty(%)
25
50
75
100
125
Ta=-40°C
Ta=25°C
4
Ta=85°C
3
2
VCC=6.0V
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
DT Input Voltage: VDT(V)
Fig.18 DT sink current
40
100
90
80
70
60
50
40
30
20
10
0
2.2
0
5
Fig.17 DT bias current
VCC=6.0V
Ta=25°C
1.8
0
-50
DT Input Voltage: VDT(V)
Fig.16 Oscillation frequency
temperature characteristics
1.6
1
0
0
125
Ambient Temperature: Ta(°C)
100
90
80
70
60
50
40
30
20
10
0
2
Fig.15 SS source current
temperature characteristics
0
80
-25
VCC=6.0V
3
Ambient Temperature: Ta(°C)
Fig.14 SS sink current
120
1.4
1.5
4
SS Voltage: VSS(V)
Fig.13 SS source current
-50
1
Dt SInk Current: IDT(mA)
0.2
VCC=6.0V
Ta=25°C
IDS(mA)
0
Output Duty Cycle: Duty(%)
SS Source Current: ISSso(uA)
4.0
SS Sink Current: ISSsi(mA)
SS Source Current: ISSso(µA)
●Reference data
35
Ta=-40°C
30
Ta=25°C
25
Ta=85°C
VCC=6.0V
Ta=25°C
20
15
10
5
1.4
1.6
DT Input Voltage: VDT(V)
1.8
2
0
2.2
VCC
-0.05
VCC
DT Input Voltage: VDT(V)
VCC
-0.10
VCC
-0.15
VCC
-0.20
VOUT(V)
Fig.20 Output Duty-VDT
characteristics (1.5MHz)
Fig.19 Output Duty-VDT
characteristics (100kHz)
500
25
Ta=25°C
20
15
10
5
VCC=35V
400
Ta=85
Ta=25
300
Ta=-40℃
250
200
150
VCC=6.0V
100
50
0
C5V
70
450
350
Ta=85°C
ISTB(uA)
IDS(mA)
30
Ta=-40°C
OCP Threshold: Vocpth(mV)
40
35
Fig.21 Output ON resistance H
(RONH)
C5V
-0.05
C5V
-0.10
C5V
-0.15
C5V
-0.20
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60
VCC=6V
55
50
45
40
35
30
-50
0
0
5
10
VOUT(V)
Fig.22 Output ON resistance L
(RONH)
65
15
20
25
30
35
40
-25
0
25
50
75
100
125
Ambient Temperature: Ta(°C)
VSTB(V)
Fig.23 STB flow-in current
4/15
Fig.24 Overcurrent detection
voltage temperature characteristics
2011.08 - Rev.D
Technical Note
BD9845FV
●Reference data
5.5
4.5
5.4
4.0
5.3
3.0
2.5
2.0
1.5
5.0
4.9
4.8
0.5
4.6
0.0
4.5
100
150
200
250
IC5V(mA)
Fig.25 C5V saturation voltage
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8
5.1
4.7
50
9
VCC=6.0V
Ta=25°C
5.2
1.0
0
10
VCC-VC5V(V)
VCC=5.0V
Ta=25°C
3.5
VC5V(V)
VCC-VC5V(V)
5.0
7
6
5
4
Ta=25°C
3
2
1
0
0
5
10
15
20
25
30
35
IC5V(mA)
Fig.26 C5V load regulation
5/15
40
0
5
10
15
20
25
30
35
40
Supply Voltage: VCC(V)
Fig.27 C5V line regulation
2011.08 - Rev.D
Technical Note
BD9845FV
●Block diagram/Pin layout
VCC
SEL
STB
OCP+
OCP-
VCC
VCC
+
VREF
-
MASTER
/SLAVE
STB
REG
(2.5V)
VREF
VCC
OCP
+
OCP
C5V
-
REG
(VCC-5V)
50mV±10mV
C5V
C5V
DT
DTOFF
FB
DT
+
DTLow
1.25V
VREF
2μA
VCC
1V±10mV
+
+ PWM
-
+
+ ERR
-
SS
SSOFF
LS
DRV
OUT
C5V
INV
PROTECTION LOGIC
OSC
DTLow
SSOFF
200μA
+
200μA
OCP
1.5V
TSD
DTOFF
Hold time
(1.6msec)
2.0V
TSD
UVLO
TSD
VCC
Hold time
(0.2msec)
MASTER
/SLAVE
VREF
2V
1.5V
C5V
CT
3.2V
2.2V
UVLO
GND
Fig.28 Block diagram
DT
Terminal
number
Terminal
name
CT
SS
1
VREF
2
CT
3
GND
GROUND
4
STB
Standby mode setting terminal
STB
C5V
OUT
SSOP-B14
VREF
GND
VCC
INV
FB
SEL
OCPOCP+
Fig.29 Pin layout
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UVLO
3V
Function
Reference voltage (2.5V) output terminal
Timing capacity external terminal
5
C5V
Output L side voltage (Vcc-5V)
6
OUT
Output
7
Vcc
Power terminal
8
OCP+
Output Overcurrent detector + Input terminal
9
OCP-
Output Overcurrent detector - Input terminal
10
SEL
11
FB
Output Error amplifier output terminal
12
INV
Output
Error amplifier - input terminal
Soft start time setting terminal
Master/Slave mode setting terminal
13
SS
Output
14
DT
Output Dead time setting terminal
6/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Operation description of each block and function
1) REG (reference voltage unit)
As for REG (2.5V), reference voltage (2.5V) stabilized better than supply voltage input to VCC terminal is supplied as an
operation voltage of IC internal circuit, as well as output outside through VREF terminal. Insert a capacitor of 1uF to VREF
terminal.
As for REG (VCC-5V), voltage of VCC-5V is supplied as power supply (LDO) of driver circuit (DRV) of OUT terminal, as
well as output outside through C5V terminal. Insert a capacitor of 1uF to VCC terminal of C5V terminal.
2) ERR Amp (error amplifier)
In step-down application, inverting input INV of
error amplifier detects output voltage by sending
back feedback current from final output stage (on
load side) of switching regulator. R1 and R2
connected to this input terminal are resistor for
setting output voltage. Non-inverting input of
amplifier is a reference input of error amplifier
itself by adding reference voltage (1.0V) inside IC.
Rf and Cf connected between FB, which is output
from error amplifier, and INV are for feedback of
error amplifier, and allows setting of loop gain.
FB is connected to PWM Comp and supplied as
non-inverting input.
Setting of output voltage (Vo) is as follows:
Vo
=
R1+R2
R2
Vo
1V
R1
ErrAmp
12
Rf
R2
INV
Cf
11
FB
Fig.30
 1.0V
3) OSC (triangular wave oscillating unit)
Generates triangular wave for inputting to PWM Comp.
First, timing capacitor CCT connected between CT terminal and GND is charged by constant current (200 uA) generated
inside IC. When CT voltage reaches 2.0 V typ, the comparator is switched, and then CCT is discharged by constant current
(200 µA). Then, when CT voltage reaches 1.5V, the comparator is switched again, and CCT is charged again. This
repetition generates triangular wave.
Oscillation frequency is determined by externally mounted CCT through theoretical formula below:
Fosc ≒ ICT/(2・CCT・ΔVosc)
ICT : CT sink/source current 200 uA typ
ΔVosc : Triangular wave amplifying voltage=(Vt0-Vt100)=0.50 V typ.
External input voltage range
VCT : 1.4 V < VCT < 2.3 V
Standard external CCT range
CCT : MIN.47 pF – MAX.3000 pF
10000
Oscillation frequency (kHz)
Here, error from theoretical formula is caused by delay of
internal circuit at a high frequency. See the graph in Fig 31 for
setting.
This triangular wave can be taken out through CT terminal. It is
also possible to input the oscillator externally by switching to
slave mode described later. Waveform input here in principle
must be triangular wave of Vpeak = (1.5V  2.0V) equivalent to
internal oscillation circuit.
1000
100
Ta=25℃
10
10
100
1000
10000
CT timing capacity (pF)
Fig.31
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7/15
2011.08 - Rev.D
Technical Note
BD9845FV
4) Soft start (soft start function)
It is possible to provide SS terminal (13pin) with soft start function by
connecting CSS as shown on the right.
Soft start time TSS is shown by the formula below:
Tss
=
Css・
Css : SS terminal connection capacity
Vinv : Error amplifier reference voltage
(1V typ)
Issso : SS source current (2uA typ)
Vinv
Issso
VREF
2uA
SS
Css
13
1Vtyp.
INV
12
(Ex) When Css = 0.01 uF
ErrAmp
Fig.32
-6
Tss =
=
0.01×10 ×1
1
2×10-6
VREF
R1
5 [msec]
In order to function soft start, time must be set longer enough than
start time of power supply and STB.
It is also possible to provide function of soft start by connecting the
resistor (R1/R2) and capacitor (CDT) to DT terminal (14pin) as shown
on the right.
14
DT
R2
C DT
Fig.33
5) PWM Comp - DEAD TIME (Pause period adjusting circuit - dead time)
Dead time can be set by applying voltage dividing resistance between VREF and GND to DT terminal.
PWM Comp compares the input dead time voltage (DT terminal voltage) and error voltage from Err Amp (FB terminal
voltage) with triangular wave, and turns off and on the output. When dead time voltage < error voltage, duty of output is
determined by dead time voltage. (When dead time setting is not used, pull up DT terminal to VREF terminal with resistor
approx 10 k ohms.)
Dead time voltage VDT in Fig 32 is shown by the formula below:
2.4
R2
R1+R2
2.2
Relation between VDT and Duty [See the graph on the right.]
Duty 100%
Duty 0%
min
typ
max
min
typ
max
When f = 100kHz
1.9
2.0
2.1
1.4
1.5
1.6
When f = 1.5MHz
1.95
2.1
2.25
1.35
1.5
1.65
[Unit : V]
Be careful when oscillation frequency is high, upper/lower limit of triangular
wave (Vt100/Vt0) is shifted by delay time of comparator to directions
expanding amplitude.
Vt100
2
VDT[V]
VDT = VREF・
1.8
1.6
Vt0
1.4
1.2
1
100
1000
10000
fosc[KHz]
6) OCP Comp (overcurrent detection circuit)
This function provides protection by forcibly turning off the output when
abnormal overcurrent flows due to shorting of output, etc. When voltage
between terminal OCP+(8pin)/OCP-(9pin) monitoring the current with
sense resistor exceeds overcurrent detection voltage (50 mV typ), it is
determined as overcurrent condition, and switching operation is stopped
immediately by setting OUT to "H" and DT,SS (and FB) to "L".
It is automatically recovered when voltage between terminal OCP+/OCPis below overcurrent detection voltage.
In addition, although hysteresis, etc. are not set here, minimum detection
retention time (1.6ms typ) is set for suppressing the heating of FET, etc.
(See the timing chart.)
When the overcurrent detection circuit is not used, short-circuit both
terminal OCP+/OCP- to VCC pin.
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8/15
Fig.34
Direction
of current VIN
OCP+
8
Sense
resistor
OCP-
9
OCP Comp
50mVtyp.
Fig.35
2011.08 - Rev.D
Technical Note
BD9845FV
7) STB /SEL(Standby/Master/Slave function)
Standby mode and normal mode can be switched by STB terminal (4pin).
1. When STB<0.5V, standby mode is set.
Out put stop (OUT=H) and REG also stops. Circuit current is also Isc = 0 uA here.
2. When STB>3.0V, normal operation mode is set.
All circuits operate. Use the controller normally in this range.
Master mode and slave mode can be switched by SEL terminal (10pin).
1. When SEL<0.5V, master mode is set.
All circuits operate.
2.
When SEL>0.5V, slave mode is set.
Operation status is set , but OSC block alone is stopped, CT terminal is High-Z here, and triangular wave is not
output.(PWM circuit and protection circuit perform the same operation as usual.) Therefore, if the controller is used in
this more without using master IC, triangular wave is not emitted, operation is unstable, and normal output cannot be
obtained. Be careful.
1.E-07
Cout_max
OUT terminal permissible capacity [F]
8) OUT (Output: External FET gate drive)
OUT terminal (6pin) is capable of directly driving the gate of
external (PchMOS) FET. Amplitude of output is restricted
between Vcc and C5V (Vcc-5V), and is not restricted by
voltage resistance of gate by input voltage, which allows
broad selection of FET.
However, for precaution when selecting FET, there is a
restriction that input capacity of gate is determined by
current capability of C5V and permissible loss of IC,
therefore refer to the permissible range in the graph on the
right when determining FET.
Cout_max
(Vcc=10V)
Cout_max
(Vcc=20V)
Cout_max
(Vcc=30V)
1.E-08
1.E-09
Fig.35 OUT 端子外付け容量許容範囲
Per m is s ible r ange
Area below each line under each condition
1.E-10
100
1000
10000
Switching f requency [kHz]
Fig.36
9) Protection (other protection functions)
This IC is equipped with low input malfunction prevention circuit (UVLO) and abnormal temperature protection circuit
(TSD) in addition to overcurrent detection circuit (OCP).
Low input malfunction prevention circuit is for preventing unstable output when input voltage is low.
Three positions of Vcc (3.2V), VREF(2.35V), and C5V(Vcc-3V) are monitored, and output is made only when all are
canceled. (See the timing chart.)
Abnormal temperature protection circuit is for protecting IC chip from destruction for preventing runaway when abnormal
heating is caused on IC exceeding rated temperature. (It does not operate normally.)
Apply a design with full margin allowed for heating in consideration of permissible loss.
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9/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Timing chart
◎Starting characteristics (UVLO cancel) and standby operation
VCC
(1)
UVLO (Vcc) is canceled when Vcc>3.2V.
①Vcc>3.2VでUVLO(Vcc)解除
STB
1.8Vtyp.
VREF起動電圧
0.9Vtyp.
VREF停止電圧
VREF
(2)
②VREF>2.2VでUVLO(VREF)解除
UVLO (VREF) is canceled when VREF>2.2V.
SS
UVLO (TSD) Minimum retention time (0.2 ms)
☆UVLO(TSD)最小保持時間(0.2msec)
1V
Set
SS by external capacity.
SSは外付け容量によって設定します。
Although
SS is notated by the same time axis in the figure for showing the image,
図中ではイメージをつかんで頂く為同じ時間軸で表記しておりますが、
actually
set sufficiently longer time in comparison with the cycle of triangular wave.
実際は三角波の周期に比べ十分に長い時間を設定します。
■UVLOは、
UVLO voltage [unit: V]
①Vcc②VREF③C5V全てが通常状態となった後、☆最小保持時間後に解除、
UVLO
①Vcc②VREF③C5VのいずれかでUVLOを検出した場合には、ただちに出力を停止。
UVLO保護状態
UVLO
DT
FB
CT
CT:
Pull-up to VREF during UVLO period
CT :UVLO期間中はVREFにプルアップ
DT:
Pull-down during UVLO
DT:UVLO期間中はプルダウン
Item
Min
Typ
Max
Threshold voltage (VCC)
3.0
3.2
3.4
-
0.15
0.25
2.0
2.2
2.4
-
3.0
3.4
Hysteresis
OUT
C5V When UVLO (Vcc , and VREF) is
UVLO(Vcc,VREF)とも解除になると
canceled, (Vcc - 5V) Reg is started.
(Vcc-5V)Regが起動
Vcc
Threshold voltage (VREF)
FB:UVLO期間中はプルダウン
FB:
Pull-down during UVLO
Threshold voltage (C5V)
OUT
C5V
Vcc-5V
(3)
UVLO (C5V) is canceled when C5V<Vcc - 3V.
③C5V<Vcc-3VでUVLO(C5V)解除
◎Overcurrent detection (When output is shorted: Overcurrent detection and cancel are repeated at a specified time interval.)
OCP-
Delay
time in detection
検出時の遅延時間
OCP+
OCP-
OCP+
tdocpth
Vcc
Vocpth
過電流検出 detection
Overcurrent
Overcurrent 過電流検出
detection
FB
DT
FB
CT
過電流検出 detection
Overcurrent
検出状態を保持する最小時間
Minimum
time retaining detection condition
tdocpre 1.6mS
tdocpre 1.6mS
DT
SS
DT→"L”
SS→"L”
(FB→"L”)
Open
DT (FB) and SS.
DT(FB)、SSを開放
OUT
C5V
OUT
Vcc
Vcc-5V
C5V
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© 2011 ROHM Co., Ltd. All rights reserved.
10/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Example of application circuit
Vin
STB
VCC
VCC
VREF
VCC
VREF
VREF
VCC-5V
CT
C5V
TSD
UVLO
OSC
5VREG
INV
VCC
VREF
+ ERR
+
SS
+ PWM
+
VCC
OCP2
FB
Vo
OUT
DRV
(Step-down)
VCC-5V
-
OCP
+
DT
VCC-5V
OCP+
OCP-
GND
Fig.37
1) Setting of output unit coil (L) and capacitor (Co)
Set the coil and capacitor as follows in step-down application:
<Setting of L-value>
When load current gets heavy, the current flowing through the coil gets continuous, and the relation below is established:
Vin: Input voltage
L
=
Tsw
IL

(Vin-Vo)×Vo
Tsw: 1/(switching frequency)
Vin
Delta IL: Ripple current of coil
Normally set Delta IL below 30% of the maximum output current (Iomax).
When L-value is made greater, ripple current (Delta IL) becomes smaller. In general, the greater the L-value is, the smaller
the permissible current of coil gets, and when the current exceeds permissible current, the coil is saturated and L-value
changes. Contact the coil manufacturer and check permissible current.
<Setting of output capacitor Co>
Select an output capacitor Co by ESR (equivalent serial resistance) property of capacitor.
Output ripple voltage (Delta Vo) is almost ESR of output capacitor, therefore,
Vo ≒
IL×ESR
ESR: Equivalent serial resistance of output capacitor Co
The relation above is established.
Ripple component by output capacitor is small enough to be neglected in comparison with ripple component by ESR in
many cases. As for Co value, it is recommended to use a sufficiently large capacitor with a capacity that satisfies ESR
condition.
<Switching element>
Determine a switching element by peak current. Peak current Isw <peak> flowing through the switching element is equal
to peak current flowing through the coil, therefore the equation below is established.
Isw (peak) = Io + IL/2
Select a switching element of permissible current having a sufficient margin over peak current calculated by the equation.
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11/15
2011.08 - Rev.D
Technical Note
BD9845FV
2) Example of overcurrent protection circuit
Insert a sense resistor between the source and VIN of output
Pch-FET for detecting overcurrent as shown in the figure.
Refer to the formula below for determining a sense resistor and
select permissible loss ensuring a margin.
VIN
OCP+
R1
C4
8
Vocpth
Iocp
Vocpth : Overcurrent detection voltage (50 mV typ)
Iocp
: Overcurrent detection setting current
Rsense =
C1
Vocpth=50mV
OCP comp
C3
R2
OCP-
Sense
センス抵抗
resistor
9
C2
Iocp is a peak current Isw (peak) here, and the amperage for
output load is an overcurrent setting amperage minus ripple
current component (Delta IL/2), etc. (See the formula on P10.)
There is a time delay approx 200ns from detection until stop of
output is made (pulse of approx 100 ns causes delay time but
detection is made), and an error may be caused from the value
above.
In addition, input to overcurrent detection unit is such a
sensitive circuit, and wrong detection by noise may be possible.
When wrong detection occurs, try to eliminate noise by the
resistor R1 and R2 or capacitance C1, C2, C3, and C4 shown
above.
OUT
6
Fig.38
VREF
3) Example of output ON/OFF control circuit
When stopping the whole circuit, set STB terminal to
"Low (STB<0.5V) to stop switching and reduce power
consumption of IC to 0 microA (typ).
Also when switching ON and OFF for each channel,
control is fixed to OFF by setting DT terminal of
desired channel to "Low (DT<1.25V)". This control is
independent for each channel, and when DT="L", SS
terminal and FB terminal are also discharged, and soft
start is enabled in restarting.
D
T
To OUT for each Ch
14
Each Ch
control signal
DTcomp
1.25Vtyp.
SS
13
Digital transistor, etc.
Fig.39
4) Example of master/slave (sync multi-ch output) operation circuit
This IC is set to slave mode by setting the input of STB terminal at 2.5V0.1V, and multi-channel output is enabled with
frequency synchronized. (Fig.40) However, CT terminal has high impedance in slave mode status, and triangular wave is
generated by CT waveform of master mode IC. Therefore the example of master slave circuit below is recommended
when starting and stopping in order to avoid malfunction by start/stop timing of master IC and slave IC. As for output, it is
recommended to control ON/OFF reliably with DT terminal.
Also, oscillation frequency is determined by capacitor (CCT)
マスタ
CT
CT
Master STB
connected to CT. When the slave IC is large in number as
Master IC
STB信号
Common
Slave
IC
共通
スレブIC
マスタIC
×N
well as oscillation frequency is high, parasitic capacity by
STB
STB
board wiring in contact with CT cannot be ignored, and preset
Input
a signal of high voltage
マスタと同期した
frequency may be drifted. Be careful.
2.5V
synchronized with master.
High電圧2.5Vの信号を入力
Example of master/slave circuit configuration is shown below.
If any other configuration is to be applied, inform our
Fig.40
personnel in charge.
CT
CT
CCT
Master IC
SEL
0.1uF
Stand-by
ON/OFF
STB
Slave IC
SEL
VREF
VREF
0.1uF
10kΩ
STB
DT
Ch
ON/OFF
control
10kΩ
DT
Ch
ON/OFF
control
DTC114Y
DTC114Y
Fig 41. Example of master/slave
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© 2011 ROHM Co., Ltd. All rights reserved.
12/15
2011.08 - Rev.D
Technical Note
BD9845FV
5) About board layout
In order to make full use of IC performance, fully investigate the items below in addition to general precautions.
・ Each output of OCP+/OCP- is such a sensitive circuit. When wiring is routed around, it is easily subjected to noise.
Try to make the wiring as short as possible.
・ Switching of large current is likely to generate noise. Try to make the large current route (VIN, Rsense, FET, L, Di,
and Cout) as thick and short as possible, and try to apply one-point grounding for GND. OUT terminal is also a
switching line, and it must be wired along a distance as short as possible. (When multi-layer board is used, shielding
by intermediate layer also seems to be effective.)
・ CCT and CVREF are reference of all, and must be wired along the shortest distance to GND of IC stabilized to be
protected against external influence.
・ Also be careful not to allow common impedance to sense family GND.
6) PIN processing of channel unused
VREF
VREF
VCC VCC
VREF DT
SS
INV
FB
14
13
12
11
1
OCP- OCP+ VCC OUT
9
8
7
6
Fig.43
When only one channel is used, process unused channels as shown above.
●I/O equivalent circuit diagram
2pin(CT)
VREF
VREF
VREF
VREF
14pin (DT)
VREF
VREF
CT
13pin (SS)
VREF
VREF
DT
VREF
VCC
SS
VREF
12pin (INV)
VREF
11pin (FB)
VREF
VREF
9pin (OCP-)
VREF
FB
INV
5pin (C5V)
6pin (OUT)
VCC
VCC
VCC
C5V
C5V
OCP-
8pin (OCP+)
VCC
VCC
VCC
VCC
VCC
VCC
VCC
OCP+
OUT
C5V
C5V
4pin (STB)
10pin (SEL)
VCC
C5V
C5V
1pin (VREF)
VCC
VCC
C5V
3pin (GND) , 7pin (VCC)
VCC
VCC
STB
VREF
SEL
GND
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13/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Notes for use
1) About maximum absolute rating
When the maximum absolute rating of application voltage or operation voltage range is exceeded, it may lead to
deterioration or rupture. It is impossible to forecast rupture in short mode or open mode. When a special mode is expected
exceeding the maximum absolute rating, try to take a physical safety measure such as a fuse.
2) GND potential
Ensure that the potential of GND terminal is the minimum in any operation condition. Also ensure that no terminal except
GND terminal has a voltage below GND voltage including actual transient phenomenon.
3) Thermal design
Allow a sufficient margin in thermal design in consideration of permissible loss (Pd) in actual use condition.
4) Shorting between terminals and wrong attachment
When attaching an IC to a set board, pay full attention to the direction of IC and dislocation. Wrong attachment may cause
rupture of IC. In addition, when shorting is caused by foreign substance placed between outputs or between output and
power supply-GND, rupture is also possible.
5) Operation in intense magnetic field
Use in intense magnetic field may result in malfunction. Be careful.
6) Inspection on set board
In inspection on set board, when a capacitor is connected to a terminal with low impedance, stress may be applied to IC,
therefore be sure to discharge electricity in each process. Apply grounding to assembling process for a measure against
static electricity, and take enough care in transport and storage. When connecting a jig in inspection process, be sure to
turn off power before detaching IC.
7) About IC terminal input
+
This IC is a monolithic IC, and contains P isolation and P board for separating elements between each element. This
P-layer and N-layer of each element form P-N junction, and many kinds of parasitic elements are constituted. (See Fig 43.)
For example, when resistor and transistor are connected with a terminal as shown below.
○P-N junction operates as a parasitic diode when
GND>(Terminal A) for resistor, and when GND>(Terminal B) for transistor (NPN).
○In addition, when GND>(Terminal B) for transistor (NPN),
parasitic NPN transistor is operated by N-layer of some other elements in the vicinity of parasitic diode mentioned above.
Parasitic element is inevitably generated by potential because of IC structure. Operation of parasitic element causes
interference with circuit operation, and may lead to malfunction, and also may cause rupture. Therefore when applying a
voltage lower than GND (P board) to I/O terminal, pay full attention to usage so that parasitic elements do not operate.
ト ラ ン ジスタ ((NPN)
NPN)
Transistor
((Terminal
端子B) B)
C
~
~
( 端子A A)
)
(Terminal
B
~
~
抵抗
Resistor
E
GND
N
P
P+
P+
N
N
N
P board
基板
P
P
P+
P+
N
N
N
PPboard
基板
Parasitic
寄生素子element
Parasitic element
寄生素子
GND
GND
( 端子B
(Terminal
B) )
~
~
(Terminal
A)
( 端子A)
C
~
~
寄生素子
Parasitic element
B
E
GND
Another
element
in
近接する
他の素子
the vicinity
GND
Parasitic
寄生素子element
Fig.44
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14/15
2011.08 - Rev.D
Technical Note
BD9845FV
●Ordering part number
B
D
9
Part No.
8
4
5
F
Part No.
9845
V
-
Package
FV : SSOP-B14
E
2
Packaging and forming specification
E2: Embossed tape and reel
(SSOP-B14)
SSOP-B14
<Tape and Reel information>
5.0 ± 0.2
8
0.3Min.
4.4 ± 0.2
6.4 ± 0.3
14
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
7
0.10
1.15 ± 0.1
0.15 ± 0.1
0.65
0.1
0.22 ± 0.1
1pin
(Unit : mm)
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© 2011 ROHM Co., Ltd. All rights reserved.
Reel
15/15
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.08 - Rev.D
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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R1120A
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