AD AD9640-80EBZ 1.8v dual analog-to-digital converter Datasheet

14-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9640
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
SDIO/ SCLK/
DCS DFS CSB
FD(0:3)A
FD BITS/THRESHOLD
DETECT
DRVDD
SPI
PROGRAMMING DATA
VIN+A
SHA
ADC
VIN–A
SIGNAL
MONITOR
VREF
D13A
D0A
CLK+
CLK–
CML
DIVIDE
1 TO 8
REF
SELECT
DCO
GENERATION
DUTY CYCLE
STABILIZER
RBIAS
VIN–B
SHA
ADC
VIN+B
SIGNAL MONITOR
DATA
MULTICHIP
SYNC
AGND
SYNC
FD BITS/THRESHOLD
DETECT
FD(0:3)B
DCOA
DCOB
D13B
D0B
SIGNAL MONITOR
INTERFACE
SMI
SMI
SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
06547-001
SENSE
CMOS
OUTPUT BUFFER
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
output supply
Integer 1 to 8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
CMOS
OUTPUT BUFFER
FEATURES
Figure 1.
PRODUCT HIGHLIGHTS
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
1.
2.
3.
4.
5.
6.
7.
Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
A standard serial port interface that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and voltage reference mode.
Pin compatibility with the AD9627, AD9627-11, and the
AD9600 for a simple migration from 14 bits to 12 bits, 11
bits, or 10 bits.
Rev. B
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AD9640* PRODUCT PAGE QUICK LINKS
Last Content Update: 03/25/2017
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DOCUMENTATION
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Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
EVALUATION KITS
• AD9640 Evaluation Board
• AN-1234: Interfacing the ADL5534 Dual IF Gain Block to
the AD9640 High Speed ADC
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9640: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analogto-Digital Converter Data Sheet
Product Highlight
• Leading Inside Advertorials: Data Converter Function Can
Help Solve Cost and Size Design Challenges in 3G and 4G
Wireless Infrastructure
TOOLS AND SIMULATIONS
• Visual Analog
• AD9640 IBIS Models
• AD9627/AD9640 S-Parameters
REFERENCE MATERIALS
DISCUSSIONS
Technical Articles
View all AD9640 EngineerZone Discussions.
• Improve The Design Of Your Passive Wideband ADC
Front-End Network
SAMPLE AND BUY
• Matching An ADC To A Transformer
Visit the product page to see pricing options.
• MS-2210: Designing Power Supplies for High Speed ADC
TECHNICAL SUPPORT
DESIGN RESOURCES
• AD9640 Material Declaration
• PCN-PDN Information
Submit a technical question or find your regional support
number.
• Quality And Reliability
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AD9640
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations ...................................................... 28
Applications ....................................................................................... 1
Power Dissipation and Standby Mode .................................... 30
Functional Block Diagram .............................................................. 1
Digital Outputs ........................................................................... 31
Product Highlights ........................................................................... 1
Timing ......................................................................................... 31
Revision History ............................................................................... 3
ADC Overrange and Gain Control .............................................. 32
General Description ......................................................................... 4
Fast Detect Overview ................................................................. 32
Specifications..................................................................................... 5
ADC Fast Magnitude ................................................................. 32
ADC DC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105......................................................................... 5
ADC Overrange (OR)................................................................ 33
ADC DC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150......................................................................... 6
ADC AC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105......................................................................... 7
Gain Switching ............................................................................ 33
Signal Monitor ................................................................................ 35
Peak Detector Mode................................................................... 35
RMS/MS Magnitude Mode ......................................................... 35
Threshold Crossing Mode ......................................................... 36
Additional Control Bits ............................................................. 36
DC Correction ............................................................................ 36
ADC AC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ 150 ......................................................................... 8
Built-In Self-Test (BIST) and Output Test .................................. 38
Digital Specifications ................................................................... 9
Built-In Self-Test (BIST) ............................................................ 38
Switching Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105 ..................................................................... 10
Output Test Modes ..................................................................... 38
Channel/Chip Synchronization .................................................... 39
Switching Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150 ..................................................................... 11
Configuration Using the SPI ..................................................... 40
Signal Monitor SPORT Output ................................................ 37
Serial Port Interface (SPI) .............................................................. 40
Hardware Interface..................................................................... 40
Timing Specifications ................................................................ 12
Configuration Without the SPI ................................................ 41
Absolute Maximum Ratings.......................................................... 14
SPI Accessible Features .............................................................. 41
Thermal Characteristics ............................................................ 14
Memory Map .................................................................................. 42
ESD Caution ................................................................................ 14
Reading the Memory Map Table .............................................. 42
Pin Configurations and Function Descriptions ......................... 15
External Memory Map .............................................................. 43
Equivalent Circuits ......................................................................... 19
Memory Map Register Description ......................................... 46
Typical Performance Characteristics ........................................... 20
Applications Information .............................................................. 49
Theory of Operation ...................................................................... 25
Design Guidelines ...................................................................... 49
ADC Architecture ...................................................................... 25
Outline Dimensions ....................................................................... 50
Analog Input Considerations.................................................... 25
Ordering Guide .......................................................................... 51
Voltage Reference ....................................................................... 27
Rev. B | Page 2 of 52
AD9640
REVISION HISTORY
12/09—Rev. A to Rev. B
Added CP-64-6 Package .................................................... Universal
Changes to Ordering Guide ...........................................................51
6/09—Rev. 0 to Rev. A
Changes to Applications Section and Product
Highlights Section ............................................................................. 1
Changes to General Description Section ....................................... 3
Changes to Specifications Section................................................... 4
Changes to Figure 2.........................................................................11
Changes to Figure 3.........................................................................12
Changes to Pin Configurations and Functional
Descriptions Section .......................................................................12
Changes to Figure 11, Figure 12, Figure 14 ................................. 18
Change to Table 15 .......................................................................... 30
Changes to ADC Overrange and Gain Control Section ............ 31
Changes to Signal Monitor Section .............................................. 34
Changes to Table 25 ........................................................................ 42
Changes to Signal Monitor Period (Register 0x113 to
Register 0x115) Section .................................................................. 47
Added LVDS Operation Section ................................................... 48
Added Exposed Pad Notation to Outline Dimensions .............. 49
6/07—Revision 0: Initial Version
Rev. B | Page 3 of 52
AD9640
GENERAL DESCRIPTION
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-todigital converter (ADC). The AD9640 is designed to support
communications applications where low cost, small size, and
versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9640 has several functions that simplify the automatic
gain control (AGC) function in the system receiver. The fast detect
feature allows fast overrange detection by outputting four bits of
input level information with very short latency.
In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect
bits of the ADC with very low latency. If the input signal level
exceeds the programmable threshold, the fine upper threshold
indicator goes high. Because this threshold is set from the four
MSBs, the user can quickly turn down the system gain to avoid an
overrange condition.
The second AGC-related function is the signal monitor. This
block allows the user to monitor the composite magnitude of
the incoming signal, which aids in setting the gain to optimize
the dynamic range of the overall system.
The ADC output data can be routed directly to the two external
14-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a
3-bit SPI-compatible serial interface.
The AD9640 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
Rev. B | Page 4 of 52
AD9640
SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
AD9640ABCPZ80/AD9640BCPZ-80
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
Supply Current
IAVDD1, 3
IDVDD1, 3
IDRVDD1 (3.3 V CMOS)
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power 4
Power-Down Power
Temperature
Full
Min
14
Typ
Max
AD9640ABCPZ105/AD9640BCPZ-105
Min
14
Typ
Max
Unit
Bits
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
±0.3
±0.6
±0.2
±3.0
±0.9
±0.4
±5.0
±2.0
Guaranteed
±0.3
±0.6
±0.2
±3.0
±0.9
±0.4
±5.0
±2.0
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
±0.3
±0.1
±0.4
±0.1
% FSR
% FSR
Full
Full
±15
±95
Full
Full
±2
7
25°C
1.3
1.3
LSB rms
Full
Full
Full
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
Full
1.7
1.7
1.7
1.8
3.3
1.8
Full
Full
Full
Full
Full
233
26
27
12
54
Full
Full
Full
Full
Full
452
487
550
52
2.5
1
±0.6
±0.5
±0.7
±0.5
±15
±95
±15
1.9
3.6
1.9
277
492
6
±2
7
1.7
1.7
1.7
1.8
3.3
1.8
310
34
35
18
55
603
645
730
68
2.5
ppm/°C
ppm/°C
±15
1.9
3.6
1.9
371
657
6
mV
mV
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3
The maximum limit applies to the combination of IAVDD and IDVDD currents.
4
Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).
2
Rev. B | Page 5 of 52
AD9640
ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
AD9640ABCPZ-125/
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
Supply Current
IAVDD1, 3
IDVDD1, 3
IDRVDD1 (3.3 V CMOS)
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power 4
Power-Down Power
Temperature
Full
AD9640BCPZ-125
Min
Typ
Max
14
Full
Full
Full
Full
25°C
Full
25°C
AD9640ABCPZ-150/
Min
14
Guaranteed
±0.3
±0.6
±0.2
±3.0
±0.9
±0.4
±5.0
±2
Unit
Bits
Guaranteed
±0.3
±0.6
±0.2
±3.0
−0.95/+1.5
−0.4/+0.6
±5.0
±2
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.4
±0.2
% FSR
% FSR
25°C
25°C
±0.4
±0.1
Full
Full
±15
±95
Full
Full
±2
7
25°C
1.3
1.3
LSB rms
Full
Full
Full
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
Full
1.7
1.7
1.7
1.8
3.3
1.8
Full
Full
Full
Full
385
42
44
22
56
Full
Full
Full
Full
Full
750
810
910
77
2.5
1
±0.7
±0.6
AD9640BCPZ-150
Typ
Max
±0.7
±0.6
±15
±95
±15
1.9
3.6
1.9
470
846
6
±3
7
1.7
1.7
1.7
1.8
3.3
1.8
419
50
53
27
57
820
895
1000
77
2.5
ppm/°C
ppm/°C
±15
1.9
3.6
1.9
517
938
6
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
The maximum limit applies to the combination of IAVDD and IDVDD currents.
4
Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).
2
3
Rev. B | Page 6 of 52
mV
mV
V
V
V
mA
mA
mA
mA
mW
mW
mW
mW
mW
AD9640
ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 3.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS)
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS)
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9640ABCPZ-80/
AD9640ABCPZ-105/
AD9640BCPZ-80
Min
Typ
Max
AD9640BCPZ-105
Min
Typ
Max
72.5
72.1
72.3
71.9
70.5
dB
dB
dB
dB
dB
70.2
71.6
71.0
71.3
70.3
72.2
71.6
72.0
71.6
Unit
71.1
70.4
70.9
70.0
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
11.9
11.8
11.7
11.6
11.8
11.8
11.7
11.5
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−87
−85
−87
−85
−84
−83
−84
−83
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
87
85
87
85
69
69.5
−75
75
−74
dBc
dBc
dBc
dBc
dBc
74
84
83
84
83
25°C
25°C
Full
25°C
25°C
−93
−89
−93
−89
−89
−89
−89
−89
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
85
82
−95
650
85
82
−95
650
dBc
dBc
dB
MHz
−82
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 7 of 52
−81
AD9640
ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 4.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS)
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS)
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9640ABCPZ-125
AD9640ABCPZ-150/
AD9640BCPZ-125
Min
Typ
Max
AD9640BCPZ-150
Min
Typ
Max
72.1
71.8
71.9
71.6
70.2
dB
dB
dB
dB
dB
69.5
71.4
70.8
70.9
70.0
71.8
71.4
71.6
71.0
Unit
71.0
70.3
70.5
69.9
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
11.8
11.7
11.7
11.6
11.8
11.8
11.6
11.5
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−86.5
−85
−86.5
−84
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
69.5
67.5
−74
−73
−84
−83
−83.5
−77
86.5
85
86.5
84
74
dBc
dBc
dBc
dBc
dBc
73
84
83
83.5
77
25°C
25°C
Full
25°C
25°C
−92
−89
−92
−90
−89
−89
−90
−90
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
85
82
−95
650
85
82
−95
650
dBc
dBc
dB
MHz
−80
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 8 of 52
−80
AD9640
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 5.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD + 1.6
AGND − 0.3
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
Max
CMOS
1.2
AGND − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Rev. B | Page 9 of 52
Typ
AVDD + 1.6
3.6
0.8
+10
+10
4
10
12
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
3.6
0.6
−134
+10
V
V
μA
μA
kΩ
pF
26
2
26
2
26
5
26
5
Unit
AD9640
Parameter
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Temperature
Min
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
Full
Full
Full
Full
250
1.15
150
1.15
Typ
350
1.25
200
1.25
Max
Unit
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
450
1.35
280
1.35
mV
V
mV
V
Pull up.
Pull down.
SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND
AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 6.
AD9640ABCPZ-80
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled 1
DCS Disabled1
CLK Period—Divide by 1 Mode (tCLK)
CLK Pulse Width High
Divide by 1 Mode, DCS Enabled
Divide by 1 Mode, DCS Disabled
Divide by 2 Mode, DCS Enabled
Divide by 3 Through 8, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Temp
Min
AD9640BCPZ-80
Typ
Max
Full
AD9640ABCPZ-105/
Min
AD9640BCPZ-105
Typ
Max
625
Full
Full
Full
20
10
12.5
Full
Full
Full
Full
3.75
5.63
1.6
0.8
Full
Full
Full
Full
Unit
625
MHz
105
105
MSPS
MSPS
ns
80
80
20
10
9.5
6.25
6.25
8.75
6.88
2.85
4.28
1.6
0.8
4.75
4.75
6.65
5.23
ns
ns
ns
ns
2.2
3.8
4.5
5.0
6.25
5.75
6.4
6.8
2.2
3.8
4.5
5.0
5.25
4.25
6.4
6.8
ns
ns
ns
ns
Full
Full
2.4
4.0
5.2
5.6
6.9
7.3
2.4
4.0
5.2
5.6
6.9
7.3
ns
ns
Full
Full
3.0
5.4
3.7
7.0
4.4
8.4
3.0
5.2
3.7
6.4
4.4
7.6
ns
ns
Rev. B | Page 10 of 52
AD9640
AD9640ABCPZ-80
Parameter
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
1
2
3
Temp
Full
AD9640ABCPZ-105/
AD9640BCPZ-80
Typ
Max
12
12/12.5
Min
Full
Full
Full
Full
Min
1.0
0.1
350
2
AD9640BCPZ-105
Typ
Max
12
12/12.5
1.0
0.1
350
2
Unit
Cycles
Cycles
ns
ps rms
μs
Cycles
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND
AD9640BCPZ-150
AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 7.
AD9640ABCPZ-125/
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled 1
DCS Disabled1
CLK Period—Divide by 1 Mode (tCLK)
CLK Pulse Width High
Divide by 1 Mode, DCS Enabled
Divide by 1 Mode, DCS Disabled
Divide by 2 Mode, DCS Enabled
Divide by 3 Through 8, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
1
2
3
Temperature
Min
AD9640BCPZ-125
Typ
Max
Full
AD9640ABCPZ-150/
Min
AD9640BCPZ-150
Typ
Max
625
Full
Full
Full
20
10
8
Full
Full
Full
Full
2.4
3.6
1.6
0.8
Full
Full
Full
Full
Unit
625
MHz
150
150
MSPS
MSPS
ns
125
125
20
10
6.66
4
4
5.6
4.4
2.0
3.0
1.6
0.8
3.33
3.33
4.66
3.66
ns
ns
ns
ns
2.2
3.8
4.5
5.0
4.5
3.5
6.4
6.8
2.2
3.8
4.5
5.0
3.83
2.83
6.4
6.8
ns
ns
ns
ns
Full
Full
2.4
4.0
5.2
5.6
6.9
7.3
2.4
4.0
5.2
5.6
6.9
7.3
ns
ns
Full
Full
Full
3.0
5.0
3.8
6.2
12
12/12.5
4.5
7.4
3.0
4.8
3.8
5.9
12
12/12.5
4.5
7.3
ns
ns
Cycles
Cycles
Full
Full
Full
Full
1.0
0.1
350
3
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 11 of 52
1.0
0.1
350
3
ns
ps rms
μs
Cycles
AD9640
TIMING SPECIFICATIONS
Table 8.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSCLKSDO
tSSCLKSDFS
Conditions
Min
Typ
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Max
0.24
0.40
Unit
ns
ns
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
3.2
−0.4
−0.4
4.5
0
0
6.2
+0.4
+0.4
Timing Diagrams
N+2
N+1
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
tCLK
CLK+
CLK–
CH A/B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
CH A/B FAST
DETECT
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
tS
tH
tDCO
tCLK
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0)
Rev. B | Page 12 of 52
06547-021
tPD
ns
ns
ns
AD9640
N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6
N+7
tCLK
CLK+
CLK–
tPD
CH A/CH B DATA
A
CH A/CH B FAST
DETECT
A
B
N – 13
B
N–7
A
B
N – 12
A
B
N–6
A
B
N – 11
A
B
N–5
A
B
N – 10
A
B
N–4
A
B
N–9
A
B
N–3
A
B
N–8
A
B
N–2
tDCO
A
B
N–7
A
B
N–1
A
B
A
N–6
A
B
B
N–5
A
N
B
N+1
A
N–4
A
N+2
tCLK
06547-089
DCO+
DCO–
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5)
CLK+
tHSYNC
06547-072
tSSYNC
SYNC
Figure 4. SYNC Input Timing Requirements
CLK+
CLK–
tCSSCLK
SMI SCLK
tSSCLKSDFS
tSSCLKSDO
SMI SDO
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode)
Rev. B | Page 13 of 52
DATA
06547-082
SMI SDFS
AD9640
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 9.
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
D0A/D0B through D13A/D13B to
DRGND
FD0A/FD0B through FD3A/FD3B to
DRGND
DCOA/DCOB to DRGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
−0.3 V to DRVDD + 0.3 V
ESD CAUTION
Table 10. Thermal Resistance
Package
Type
64-lead LFCSP
9 mm × 9 mm
Airflow
Velocity
(m/s)
0
1.0
2.0
θJA1, 2
18.8
16.5
15.8
θJC1, 3
0.6
θJB1, 4
6.0
Unit
°C/W
°C/W
°C/W
1
JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 14 of 52
AD9640
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9640
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
06547-002
D5A
D6A
D7A
DRGND
DRVDD
D8A
D9A
DVDD
D10A
D11A
D12A
D13A (MSB)
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B (MSB)
DCOB
DCOA
D0A (LSB)
D1A
D2A
D3A
D4A
Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View)
Table 11. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND,
Exposed Pad
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
The exposed thermal pad on the bottom of the package provides the analog ground
for the part. This exposed pad must be connected to ground for proper operation.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Rev. B | Page 15 of 52
AD9640
Pin No.
Mnemonic
ADC Fast Detect Outputs
29
FD0A
30
FD1A
31
FD2A
32
FD3A
53
FD0B
54
FD1B
55
FD2B
56
FD3B
Digital Inputs
52
SYNC
Digital Outputs
12
D0A (LSB)
13
D1A
14
D2A
15
D3A
16
D4A
17
D5A
18
D6A
19
D7A
22
D8A
23
D9A
25
D10A
26
D11A
27
D12A
28
D13A (MSB)
58
D0B (LSB)
59
D1B
60
D2B
61
D3B
62
D4B
63
D5B
2
D6B
3
D7B
4
D8B
5
D9B
6
D10B
7
D11B
8
D12B
9
D13B (MSB)
11
DCOA
10
DCOB
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Serial Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
Type
Description
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator. See Table 18 for details.
Channel A Fast Detect Indicator. See Table 18 for details.
Channel A Fast Detect Indicator. See Table 18 for details.
Channel A Fast Detect Indicator. See Table 18 for details.
Channel B Fast Detect Indicator. See Table 18 for details.
Channel B Fast Detect Indicator. See Table 18 for details.
Channel B Fast Detect Indicator. See Table 18 for details.
Channel B Fast Detect Indicator. See Table 18 for details.
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
Rev. B | Page 16 of 52
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D0+ (LSB)
D0– (LSB)
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD9640
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9640
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
06547-003
D7+
D8–
D8+
DRGND
DRVDD
D9–
D9+
DVDD
D10–
D10+
D11–
D11+
D12–
D12+
D13– (MSB)
D13+ (MSB)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
Figure 7. Pin Configuration, LFCSP LVDS (Top View)
Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46 AVDD
0
AGND,
Exposed Pad
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
54
FD0+
53
FD0−
56
FD1+
55
FD1−
59
FD2+
58
FD2−
61
FD3+
60
FD3−
Type
Function
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
The exposed thermal pad on the bottom of the package provides the analog ground for the
part. This exposed pad must be connected to ground for proper operation.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details.
Rev. B | Page 17 of 52
AD9640
Pin No.
Mnemonic
Digital Inputs
52
SYNC
Digital Outputs
63
D0+ (LSB)
62
D0− (LSB)
3
D1+
2
D1−
5
D2+
4
D2−
7
D3+
6
D3−
9
D4+
8
D4−
13
D5+
12
D5−
15
D6+
14
D6−
17
D7+
16
D7−
19
D8+
18
D8−
23
D9+
22
D9−
26
D10+
25
D10−
28
D11+
27
D11−
30
D12+
29
D12−
32
D13+ (MSB)
31
D13− (MSB)
11
DCO+
10
DCO−
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Ports
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
Type
Function
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6 —True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
Rev. B | Page 18 of 52
AD9640
EQUIVALENT CIRCUITS
DVDD
1kΩ
SCLK/DFS
VIN
06547-011
06547-004
26kΩ
Figure 8. Equivalent Analog Input Circuit
Figure 12. Equivalent SCLK/DFS Input Circuit
AVDD
1kΩ
1.2V
10kΩ
SENSE
10kΩ
CLK+
06547-005
06547-009
CLK–
Figure 13. Equivalent SENSE Circuit
Figure 9. Equivalent Clock Input Circuit
DRVDD
DVDD
26kΩ
DVDD
1kΩ
06547-081
06547-010
CSB
DRGND
Figure 10. Digital Output
Figure 14. Equivalent CSB Input Circuit
DRVDD
AVDD
DVDD
26kΩ
DVDD
1kΩ
VREF
SDIO/DCS
6kΩ
06547-096
06547-007
DRVDD
Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit
Figure 15. Equivalent VREF Circuit
Rev. B | Page 19 of 52
AD9640
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled, 1 V internal reference;
2 V p-p differential input; VIN = −1.0 dBFS; and 64k sample; TA = 25°C, unless otherwise noted.
0
0
150MSPS
2.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS)
ENOB = 11.8 BITS
SFDR = 86dBc
–20
AMPLITUDE (dBFS)
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
06547-050
–100
–40
–120
0
10
20
30
40
50
60
06547-053
AMPLITUDE (dBFS)
–20
150MSPS
140.3MHz @ –1dBFS
SNR = 70.9dBc (71.9dBFS)
ENOB = 11.6 BITS
SFDR = 85.1dBc
–120
0
70
10
20
FREQUENCY (MHz)
Figure 16. AD9640-150 Single-Tone FFT with fIN = 2.3 MHz
50
60
70
0
150MSPS
30.3MHz @ –1dBFS
SNR = 71.7dBc (72.7dBFS)
ENOB = 11.8 BITS
SFDR = 89.9dBc
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
150MSPS
200.3MHz @ –1dBFS
SNR = 70dBc (71dBFS)
ENOB = 11.5 BITS
SFDR = 80dBc
–20
AMPLITUDE (dBFS)
–20
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
06547-051
–100
–40
–120
0
10
20
30
40
50
60
06547-054
AMPLITUDE (dBFS)
40
Figure 19. AD9640-150 Single-Tone FFT with fIN = 140.3 MHz
0
–120
0
70
10
20
FREQUENCY (MHz)
30
40
50
60
70
FREQUENCY (MHz)
Figure 17. AD9640-150 Single-Tone FFT with fIN = 30.3 MHz
Figure 20. AD9640-150 Single-Tone FFT with fIN = 200.3 MHz
0
0
150MSPS
70MHz @ –1dBFS
SNR = 71.5dBc (72.5dBFS)
ENOB = 11.7 BITS
SFDR = 84dBc
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
150MSPS
337MHz @ –1dBFS
SNR = 68dBc (69dBFS)
ENOB = 11 BITS
SFDR = 72.4dB
–20
AMPLITUDE (dBFS)
–20
–40
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–100
–120
0
10
20
30
40
50
60
06547-085
–100
06547-052
AMPLITUDE (dBFS)
30
FREQUENCY (MHz)
–120
0
70
FREQUENCY (MHz)
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 18. AD9640-150 Single-Tone FFT with fIN = 70 MHz
Figure 21. AD9640-150 Single-Tone FFT with fIN = 337 MHz
Rev. B | Page 20 of 52
AD9640
0
0
150MSPS
440MHz @ –1dBFS
SNR = 65dBc (66dBFS)
ENOB = 10.4 BITS
SFDR = 70.0dB
–20
AMPLITUDE (dBFS)
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
06547-086
–100
–40
–120
0
10
20
30
40
50
60
06547-093
AMPLITUDE (dBFS)
–20
125MSPS
70MHz @ –1dBFS
SNR = 71.8dBc (72.8dBFS)
ENOB = 11.7 BITS
SFDR = 85dBc
–120
0
70
10
20
FREQUENCY (MHz)
Figure 22. AD9640-150 Single-Tone FFT with fIN = 440 MHz
40
50
60
Figure 25. AD9640-125 Single-Tone FFT with fIN = 70 MHz
0
0
125 MSPS
2.3MHz @ –1dBFS
SNR = 72.3dBc (73.3dBFS)
ENOB = 11.8 BITS
SFDR = 88.4dBc
125 MSPS
140MHz @ –1dBFS
SNR = 71.4dBc (72.4dBFS)
ENOB = 11.7 BITS
SFDR = 87.1dBc
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
30
FREQUENCY (MHz)
–40
–60
SECOND HARMONIC
–80
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
THIRD HARMONIC
–100
–120
0
10
20
30
40
50
06547-059
06547-057
–100
–120
60
0
10
20
FREQUENCY (MHz)
Figure 23. AD9640-125 Single-Tone FFT with fIN = 2.3 MHz
40
50
60
Figure 26. AD9640-125 Single-Tone FFT with fIN = 140 MHz
0
0
125 MSPS
30.3MHz @ –1dBFS
SNR = 72.1dBc (73.1dBFS)
ENOB = 11.8 BITS
SFDR = 89.1dBc
–40
THIRD HARMONIC
–60
SECOND HARMONIC
–80
125 MSPS
200MHz @ –1dBFS
SNR = 70.8dBc (71.8dBFS)
ENOB = 11.6 BITS
SFDR = 80.5dBc
–20
AMPLITUDE (dBFS)
–20
–40
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–120
0
10
20
30
40
50
06547-060
–100
–100
06547-058
AMPLITUDE (dBFS)
30
FREQUENCY (MHz)
–120
0
60
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. AD9640-125 Single-Tone FFT with fIN = 30.3 MHz
Figure 27. AD9640-125 Single-Tone FFT with fIN = 200 MHz
Rev. B | Page 21 of 52
AD9640
120
95
SFDR = +25°C
85
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
–70
–60
–50
–40
–30
–20
75
SFDR = +85°C
SNR = –40°C
65
06547-061
–80
SFDR = –40°C
70
85dB REFERENCE LINE
0
–90
80
SNR = +25°C
SNR = +85°C
60
0
0
–10
50
100
INPUT AMPLITUDE (dBFS)
06547-088
80
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
90
SFDR (dBFS)
100
150
200
250
300
350
400
450
INPUT FREQUENCY (MHz)
Figure 31. AD9640-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 1 V p-p Full Scale
Figure 28. AD9640-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.3 MHz
0.8
120
SFDR (dBFS)
0.6
80
GAIN/OFFSET ERROR (%FSR)
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
OFFSET
0.4
0.2
0
–0.2
–0.4
–0.6
GAIN
–80
–70
–60
–50
–40
–30
–20
–0.8
–1.0
–40
0
–10
06547-098
0
–90
06547-062
85dB REFERENCE LINE
–20
0
40
60
80
Figure 32. AD9640 Gain and Offset vs. Temperature
Figure 29. AD9640-150 Single-Tone SFDR vs. Input Amplitude with
fIN = 98.12 MHz
0
95
90
–20
SNR/SFDR (dBc AND dBFS)
SFDR = +25°C
85
SFDR = –40°C
80
SNR = –40°C
SFDR = +85°C
75
70
SNR = +25°C
65
SNR = +85°C
60
0
50
100
150
200
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
06547-087
SNR/SFDR (dBc)
20
TEMPERATURE (°C)
INPUT AMPLITUDE (dBFS)
250
300
350
400
IMD3 (dBFS)
–120
–90
450
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 30. AD9640-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
06547-063
SNR/SFDR (dBc AND dBFS)
100
Figure 33. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
Rev. B | Page 22 of 52
AD9640
0
0
–20
SFDR (dBc)
AMPLITUDE (dBFS)
–40
–60
IMD3 (dBc)
IMD3 (dBFS)
–80
–40
–60
–80
SFDR (dBFS)
–100
–120
–90
06547-064
–100
–78
–66
–54
–42
–30
–120
–6
–18
06547-066
SNR/SFDR (dBc AND dBFS)
–20
150 MSPS
169.1MHz @–7dBFS
172.1MHz @–7dBFS
SFDR = 83.8dBc (90.8dBFS)
0
10
20
INPUT AMPLITUDE (dBFS)
Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
50
60
70
0
NPR = 64.7dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–60
–80
–100
06547-102
–100
–40
–120
0
15.36
30.72
46.08
06547-100
AMPLITUDE (dBFS)
40
Figure 37. AD9640-150 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
0
–120
15.625
0
61.44
FREQUENCY (MHz)
31.25
46.875
62.5
FREQUENCY (MHz)
Figure 35. AD9640-125, Two 64 k WCDMA Carriers
with fIN = 170 MHz, fS = 122.88 MSPS
Figure 38. AD9640 Noise Power Ratio (NPR)
0
100
150 MSPS
29.1MHz @–7dBFS
32.1MHz @–7dBFS
SFDR = 86.1dBc (93dBFS)
–20
95
SFDR—SIDE A
–40
SNR/SFDR (dBc)
AMPLITUDE (dBFS)
30
FREQUENCY (MHz)
–60
–80
90
85
SFDR—SIDE B
80
SNR—SIDE B
SNR—SIDE A
–120
0
10
20
30
40
50
60
06547-067
75
06547-065
–100
70
70
0
FREQUENCY (MHz)
25
50
75
100
125
150
CLOCK FREQUENCY (Msps)
Figure 36. AD9640-150 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
Figure 39. AD9640-125 Single-Tone SNR/SFDR vs. Clock Frequency (fS)
with fIN = 2.3 MHz
Rev. B | Page 23 of 52
AD9640
10
100
1.3 LSB rms
95
SFDR DCS ON
90
SNR/SFDR (dBc)
NUMBER OF HITS (1M)
8
6
4
85
SFDR DCS OFF
80
SNR DCS ON
75
70
2
N–4 N–3 N–2
N–1
N
N+1 N+2 N+3
OUTPUT CODE
N+4
60
20
06547-079
0
Figure 43. AD9640 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz
2.0
90
SFDR
1.5
1.0
85
SNR/SFDR (dBc)
0.5
0
–0.5
–1.0
80
75
SNR
06547-068
–1.5
–2.0
0
2048
4096
6144
8192
70
0.5
10,240 12,288 14,336 16,384
OUTPUT CODE
0.4
0.3
0.2
0.1
0
–0.1
–0.2
06547-069
–0.3
0
2048
4096
6144
8192
0.8
0.9
1.0
1.1
1.2
1.3
Figure 44. AD9640 SNR/SFDR vs. Input Common Mode Voltage (VCM)
with fIN = 30 MHz
0.5
–0.5
0.7
INPUT COMMON-MODE VOLTAGE (V)
Figure 41. AD9640 INL with fIN = 10.3 MHz
–0.4.
0.6
06547-091
INL ERROR (LSB)
80
60
DUTY CYCLE (%)
Figure 40. AD9640 Grounded Input Histogram
DNL ERROR (LSB)
40
06547-090
SNR DCS OFF
65
10,240 12,288 14,336 16,384
OUTPUT CODE
Figure 42. AD9640 DNL with fIN = 10.3 MHz
Rev. B | Page 24 of 52
AD9640
THEORY OF OPERATION
The AD9640 dual ADC design can be used for diversity reception
of signals, where the ADCs are operating identically on the same
carrier but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can sample
any fS/2 frequency segment from dc to 200 MHz using appropriate
low-pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 450 MHz analog input is
permitted but occurs at the expense of increased ADC distortion.
In nondiversity applications, the AD9640 can be used as a baseband receiver, where one ADC is used for I input data and the
other is used for Q input data.
Synchronizaton capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9640 are accomplished
using a 3-bit SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, they limit the input bandwidth.
See the AN-742 Application Note, Frequency Domain Response
of Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article, “Transformer-Coupled
Front-End for Wideband A/D Converters” for more information
on this subject.
S
ADC ARCHITECTURE
CH
The AD9640 architecture consists of a dual front-end sampleand-hold amplifier (SHA), followed by a pipelined, switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample, and the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out error correction, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers go
into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9640 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 45). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within ½ of a clock cycle.
S
CS
VIN+
CPIN, PAR
S
H
CS
VIN–
S
06547-024
CH
CPIN, PAR
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by the buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9640 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.55 × AVDD
is recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 44). An on-board common-mode voltage reference
is included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9640
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC.
Rev. B | Page 25 of 52
AD9640
The output common-mode voltage of the AD8138 is easily set
with the CML pin of the AD9640 (see Figure 46), and the driver
can be configured in a Sallen-Key filter topology to provide
band limiting of the input signal.
An alternative to using a transformer coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential
driver. An example is shown in Figure 50. See the AD8352 data
sheet for more information.
499Ω
VIN+
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 13 displays recommended values to
set the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
AVDD
499Ω
R
CML
VIN–
06547-025
523Ω
AD9640
C
AD8138
499Ω
Table 13. Example RC Network
Figure 46. Differential Input Configuration Using the AD8138
R
2V p-p
C
AD9640
R
A single-ended input can provide adequate performance in cost
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 48 details a typical
single-ended input configuration.
CML
06547-026
VIN–
0.1µF
Figure 47. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
10µF
R
49.9Ω
1V p-p
0.1µF
0.1µF
AD9640
C
1kΩ
10µF
VIN+
1kΩ
AVDD
R
VIN–
1kΩ
Figure 48. Single-Ended Input Configuration
0.1µF
0.1µF
AVDD
1kΩ
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9640. For applications where
SNR is a key parameter, differential double balun coupling is the
recommended input configuration (see Figure 49 for an example).
R
VIN+
2V p-p
25Ω
PA
S
S
P
AD9640
C
25Ω
0.1µF
0.1µF
R
VIN–
CML
Figure 49. Differential Double Balun Input Configuration
VCC
0.1µF
0Ω
ANALOG INPUT
16
0.1µF
8, 13
1
11
0.1µF
RD
RG
3
200Ω
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
2
CD
C Differential (pF)
15
5
5
Open
Single-Ended Input Configuration
VIN+
49.9Ω
R Series
(Ω Each)
33
33
15
15
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 47. To bias the
analog input, the CML voltage can be connected to the center
tap of the transformer’s secondary winding.
06547-028
0.1µF
06547-071
R
49.9Ω
C
0.1µF
200Ω
R
AD9640
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. B | Page 26 of 52
06547-070
1V p-p
AD9640
VOLTAGE REFERENCE
VIN+A/VIN+B
VIN–A/VIN–B
A stable and accurate voltage reference is built into the AD9640.
The input range can be adjusted by varying the reference voltage
applied to the AD9640, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the next few sections. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
ADC
CORE
VREF
1.0µF
0.1µF
R2
SELECT
LOGIC
SENSE
Internal Reference Connection
AD9640
06547-031
0.5V
R1
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9640 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 53 shows
how the internal reference voltage is affected by loading.
0
VREF = 0.5V
R2 ⎞
VREF = 0.5 × ⎛⎜1 +
⎟
R1 ⎠
⎝
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+A/VIN+B
VIN–A/VIN–B
ADC
CORE
–0.25
VREF = 1V
–0.50
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
LOAD CURRENT (mA)
VREF
1.0µF
2.0
06547-080
REFERENCE VOLTAGE ERROR (%)
A comparator within the AD9640 detects the potential at the
SENSE pin and configures the reference into four possible
modes, which are summarized in Table 14. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 51), setting VREF to 1 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected external to
the chip, as shown in Figure 52, the switch again sets to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
Figure 53. VREF Accuracy vs. Load
0.1µF
External Reference Operation
SELECT
LOGIC
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the
internal reference in 1 V mode.
SENSE
AD9640
06547-030
0.5V
Figure 51. Internal Reference Configuration
Table 14. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R2 ⎞ (see Figure 52)
⎛
0 .5 × ⎜ 1 +
⎟
R1 ⎠
⎝
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF
2.0
Rev. B | Page 27 of 52
AD9640
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9640, while preserving
the fast rise and fall times of the signal that are critical to a low
jitter performance.
2.0
1.5
1.0
0
MINI-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
0.1µF
–0.5
CLOCK
INPUT
–1.0
CLK+
ADC
AD9640
100Ω
50Ω
0.1µF
CLK–
–1.5
–2.5
–40
–20
0
20
40
60
06547-035
–2.0
SCHOTTKY
DIODES:
HSMS2822
0.1µF
06547-099
REFERENCE VOLTAGE ERROR (mV)
2.5
Figure 56. Transformer Coupled Differential Clock (Up to 200 MHz)
80
TEMPERATURE (°C)
Figure 54. Typical VREF Drift
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9640 sample clock inputs
CLK+, and CLK− should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
1nF
0.1µF
CLOCK
INPUT
CLK+
ADC
AD9640
50Ω
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
AVDD
0.1µF
0.1µF
CLOCK
INPUT
CLK+
1.2V
0.1µF
CLOCK
INPUT
2pF
0.1µF
ADC
AD9640
CLK–
50kΩ
50kΩ
240Ω
240Ω
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
06547-034
2pF
100Ω
06547-036
CLK–
AD951x
PECL DRIVER
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9640 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, the jitter of the clock source is of the
most concern, as described in the Jitter Considerations section.
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9640 (at clock rates to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer. The RF balun
configuration is recommended for clock frequencies between
125 MHz and 625 MHz, and the RF transformer is recommended
for clock frequencies from 10 MHz to 200MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9640 to approximately 0.8 V p-p
differential.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
0.1µF
CLOCK
INPUT
AD951x
LVDS DRIVER
100Ω
0.1µF
ADC
AD9640
CLK–
50kΩ
50kΩ
06547-037
CLK+
06547-101
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1 V.
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and
the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
Rev. B | Page 28 of 52
AD9640
CLK+ can be directly driven from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages up to 3.6 V, making the selection of
the drive logic voltage very flexible.
VCC
0.1µF
1kΩ
CLOCK
INPUT
OPTIONAL
0.1µF
100Ω
AD951x
CMOS DRIVER
CLK+
ADC
AD9640
1kΩ
50Ω1
CLK–
150Ω
39kΩ
06547-038
0.1µF
RESISTOR IS OPTIONAL
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that needs to be considered where the clock
rate can change dynamically. This requires a wait time of 1.5 μs
to 5 μs after a dynamic clock frequency increase or decrease before
the DCS loop is relocked to the input signal. During the time
period the loop is not locked, the DCS loop is bypassed, and
internal device timing is dependent on the duty cycle of the input
clock signal. In such applications, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNRLF) at a given input frequency (fINPUT) due
to jitter (tJRMS) can be calculated by
VCC
50Ω1
1kΩ
AD951x
CMOS DRIVER
1kΩ
0.1µF
CLK+
ADC
AD9640
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ]
06547-039
CLK–
150Ω RESISTOR IS OPTIONAL
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 62.
75
The AD9640 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
MEASURED
PERFORMANCE
65
SNR (dBc)
The AD9640 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
0.05ps
70
0.20ps
60
0.5ps
55
1.0ps
50
1.50ps
2.00ps
45
40
Clock Duty Cycle
2.50ps
3.00ps
1
10
100
1000
INPUT FREQUENCY (MHz)
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
06547-041
0.1µF
CLOCK
INPUT
OPTIONAL 0.1µF
100Ω
Figure 62. SNR vs. Input Frequency and Jitter
The AD9640 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9640. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 43.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9640.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock
signal with digital noise. Low jitter, crystal-controlled oscillators
make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
See the AN-501 Application Note and AN-756 Application
Note for more information about jitter performance as it
relates to ADCs.
Rev. B | Page 29 of 52
AD9640
IAVDD
0.5
0.3
TOTAL POWER
0.5
0.2
IDRVDD
0.25
0
25
50
75
100
125
0
150
0.5
TOTAL POWER
0.5
0.2
IDRVDD
0.25
0.1
IDVDD
0
0
25
50
75
100
SUPPLY CURRENT (A)
0.3
0.75
0
125
ENCODE FREQUENCY (MHz)
Figure 64. AD9640-125 Power and Current vs. Clock Frequency
06547-075
TOTAL POWER (W)
0.4
IAVDD
25
0
50
75
100
ENCODE FREQUENCY (MHz)
Figure 65. AD9640-105 Power and Current vs. Clock Frequency
0.75
0.3
IAVDD
0.5
0.2
TOTAL POWER
0.1
0.25
IDRVDD
IDVDD
0
0
20
40
60
0
80
ENCODE FREQUENCY (MHz)
ENCODE FREQUENCY (MHz)
1.0
0
0
Figure 66. AD9640-80 Power and Current vs. Clock Frequency
Figure 63. AD9640-150 Power and Current vs. Clock Frequency
1.25
IDRVDD
IDVDD
0.1
IDVDD
0
SUPPLY CURRENT (A)
0.75
0.4
06547-076
TOTAL POWER (W)
1.0
0.1
0.25
TOTAL POWER (W)
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken with the same operating conditions as the Typical
Performance Characteristics, with a 5 pF load on each output
driver.
SUPPLY CURRENT (A)
where N is the number of output bits (30 in the case of the AD9640
with the FD bits disabled). This maximum current occurs when
every output bit switches on every clock cycle, that is, a fullscale square wave at the Nyquist frequency of fCLK/2. In practice,
the DRVDD current is established by the average number of
output bits switching, which is determined by the sample rate
and the characteristics of the analog input signal.
0.2
SUPPLY CURRENT (A)
IDRVDD = VDRVDD × CLOAD × fCLK × N
TOTAL POWER
0.5
06547-074
TOTAL POWER (W)
The maximum DRVDD current (IDRVDD) can be calculated as
IAVDD
0.3
0.75
06547-073
As shown in Figure 63, the power dissipated by the AD9640
is proportional to its sample rate. In CMOS output mode,
the digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
1.25
0.4
1
POWER DISSIPATION AND STANDBY MODE
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9640 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9640 to its normal operational mode. Note that PDWN is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
Rev. B | Page 30 of 52
AD9640
DIGITAL OUTPUTS
Digital Output Enable Function (OEB)
The AD9640 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families by matching DRVDD to the
digital supply of the interfaced logic. The AD9640 can also be
configured for LVDS outputs using a DRVDD supply voltage
of 1.8 V.
The AD9640 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the SMI SDO/OEB
pin or through the SPI interface. If the SMI SDO/OEB pin is low,
the output data drivers are enabled. If the SMI SDO/OEB pin is
high, the output data drivers are placed in a high impedance state.
This OEB function is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital supplies (DRVDD)
and should not exceed that supply voltage.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 15).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 15. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
When using the SPI interface, the data and fast detect outputs
of each channel can be independently three-stated by using the
output enable bar bit in Register 0x14.
TIMING
The AD9640 provides latched data with a pipeline delay of
twelve clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9640.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9640 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9640 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the DCO clock
polarity has been changed via the SPI. See Figure 2 and Figure 3
for a graphical timing description.
Table 16. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. B | Page 31 of 52
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OVR
1
0
0
0
1
AD9640
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
Using the SPI port, the user can provide a threshold above which
an overrange output is active. As long as the signal is below that
threshold, the output should remain low. The fast detect outputs
can also be programmed via the SPI port so that one of the pins
functions as a traditional overrange pin for customers who
currently use this feature. In this mode, all 14 bits of the converter
are examined in the traditional manner, and the output is high for
the condition normally defined as overflow. In either mode, the
magnitude of the data is considered in the calculation of the
condition (but the sign of the data is not considered). The threshold
detection responds identically to positive and negative signals
outside the desired range (magnitude).
FAST DETECT OVERVIEW
The AD9640 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations.
Each ADC has four fast detect (FD) output pins that are used
to output information about the current state of the ADC input
level. The function of these pins is programmable via the fast detect
mode select bits and the fast detect enable bit in Register 0x104,
allowing range information to be output from several points in
the internal datapath. These output pins can also be set up to
indicate the presence of overrange or underrange conditions,
according to programmable threshold levels. Table 17 shows the
six configurations available for the fast detect pins.
Table 17. Fast Detect Mode Select Bits Settings
Fast Detect
Mode Select Bits
(Register 0x104[3:1])
000
001
010
011
100
101
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD3
FD2
FD1
FD0
ADC fast magnitude
(see Table 18)
OR
ADC fast magnitude
(see Table 19)
OR
F_LT
ADC fast magnitude
(see Table 20)
C_UT F_LT
ADC fast magnitude
(see Table 20)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
1
The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode
configuration and FD0+/FD0− to FD3+/FD3− for the LVDS mode configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from
an early converter stage with a latency of only two clock cycles
(when in CMOS output mode). Using the fast detect output pins
in this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 18.
Table 18. ADC Fast Magnitude Nominal Levels with Fast Detect
Mode Select Bits = 000
ADC Fast
Magnitude on
FD[3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. B | Page 32 of 52
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to −0.56
−0.56 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to FS
−1.16 to 0
AD9640
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock cycles.
Table 19 shows the corresponding ADC input levels when the
fast detect mode select bits are set to 0b001 (that is, when ADC fast
magnitude is presented on the FD[3:1] pins).
Table 19. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 001
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to 0
ADC Fast Magnitude
on FD[3:1] Pins
000
001
010
011
100
101
110
111
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[3:2]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 20.
Table 20. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 010 or 011
ADC Fast
Magnitude on
FD[2:1] Pins
00
01
10
11
Nominal Input
Magnitude
Below FS (dB)
<−14.5
−14.5 to −7
−7 to −3.25
−3.25 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −12.04
−18.07 to −6.02
−8.52 to −2.5
−4.08 to 0
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). The
coarse upper threshold output is output two clock cycles after the
level is exceeded at the input and, therefore, provides a fast indication of the input signal level. The coarse upper threshold levels
are listed in Table 21. This indicator remains asserted for a
minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 21. Coarse Upper Threshold Levels
Coarse Upper Threshold
Register 0x105[2:0]
000
001
010
011
100
101
110
111
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
<−24
−24
−14.5
−10
−7
−5
−3.25
−1.8
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal magnitude at the output of the ADC. This comparison is subject to the
ADC clock latency but is accurate in terms of the converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS = 20 log(Threshold Magnitude/213)
ADC OVERRANGE (OR)
Fine Lower Threshold (F_LT)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
The fine lower threshold indicator is asserted if the input
magnitude is less than the value programmed in the fine lower
threshold register located at Register 0x108 and Register 0x109.
The fine lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to ADC clock latency but is accurate
in terms of the converter resolution. The fine lower threshold
magnitude is defined by the following equation:
GAIN SWITCHING
The AD9640 includes circuitry that is useful in applications either
where large dynamic ranges exist or where gain ranging converters
are employed. This circuitry allows digital thresholds to be set
such that an upper threshold and a lower threshold can be
programmed. Fast detect mode select bit = 010 through fast
detect mode select bit = 101 support various combinations of the
gain switching options.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
dBFS = 20 log(Threshold Magnitude/213)
The operation of the fine upper threshold indicators and fine
lower threshold indicators is shown in Figure 67.
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in conjunction
with the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
Rev. B | Page 33 of 52
AD9640
similarly, corresponds to the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. The dwell time is set by the 16-bit dwell time
value located at Address 0x10A and Address 0x10B and is set in
units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine upper threshold magnitude is
defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement
gain output is shown in Figure 67.
FINE UPPER THRESHOLD
FINE LOWER THRESHOLD
06547-097
F_UT
F_LT
Figure 67. Threshold Settings for F_UT and F_LT
Rev. B | Page 34 of 52
AD9640
SIGNAL MONITOR
The signal monitor result values can be obtained from the part by
reading back internal registers at Address 0x116 to Address 0x11B,
using the SPI port or the signal monitor SPORT output. The output
contents of the SPI-accessible signal monitor registers are set via
the two signal monitor mode bits of the signal monitor control
register. Both ADC channels must be configured for the same
signal monitor mode (Address 0x112). Separate SPI-accessible,
20-bit signal monitor result (SMR) registers are provided for each
ADC channel. Any combination of the signal monitor functions
can also be output to the user via the serial SPORT interface.
These outputs are enabled using the peak detector output enable
bit, the rms/ms magnitude output enable bit, and the threshold
crossing output enable bit in the signal monitor SPORT control
register.
For each signal monitor measurement, a programmable signal
monitor period register (SMPR) controls the duration of the
measurement. This period of time is programmed as the number
of input clock cycles in a 24-bit signal monitor period register
located at Address 0x113, Address 0x114, and Address 0x115.
This register can be programmed with a period from 128 samples
to 16.78 (224) million samples.
Because the dc offset of the ADC can be significantly larger
than the signal of interest (affecting the results from the signal
monitor), a dc correction circuit is included as part of the signal
monitor block to null the dc offset before measuring the power.
PEAK DETECTOR MODE
The magnitude of the input port signal is monitored over a
programmable time period (determined by the SMPR) to give
the peak value detected. This function is enabled by programming
a Logic 1 in the signal monitor mode bits of the signal monitor
control register or by setting the peak detector output enable bit
in the signal monitor SPORT control register. The 24-bit SMPR
must be programmed before activating this mode.
After enabling this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the value in the internal
peak level holding register (not accessible to the user), and the
greater of the two is updated as the current peak level. The initial
value of the peak level holding register is set to the current ADC
input signal magnitude. This comparison continues until the
monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding register
(not accessible to the user), which can be read through the SPI port
or output through the SPORT serial interface. The monitor period
timer is reloaded with the value in the SMPR, and the countdown is
restarted. In addition, the magnitude of the first input sample is
updated in the peak level holding register, and the comparison and
update procedure, as explained previously, continues.
Figure 68 is a block diagram of the peak detector logic. The SMR
register contains the absolute magnitude of the peak detected by
the peak detector logic.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
CLEAR
MAGNITUDE
STORAGE
REGISTER
LOAD
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
LOAD
COMPARE
A>B
06547-044
The signal monitor block provides additional information
about the signal being digitized by the ADC. The signal monitor
computes the rms input magnitude, the peak magnitude,
and/or the number of samples by which the magnitude exceeds
a particular threshold. Together, these functions can be used to
gain insight into the signal characteristics and to estimate the
peak/average ratio or even the shape of the complementary cumulative distribution function (CCDF) curve of the input signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
Figure 68. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
In this mode, the root-mean-square (rms) or mean-square (ms)
magnitude of the input port signal is integrated (by adding an
accumulator) over a programmable period of time (determined by
the SMPR) to give the rms or ms magnitude of the input signal.
This mode is set by programming Logic 0 in the signal monitor
mode bits of the signal monitor control register or by setting the
rms/ms magnitude output enable bit in the signal monitor SPORT
control register. The 24-bit SMPR, representing the period over
which integration is performed, must be programmed before activating this mode.
After enabling the rms/ms magnitude mode, the value in the SMPR
is loaded into a monitor period timer, and the countdown is started
immediately. Each input sample is converted to floating-point
format and squared. It is then converted to 11-bit, fixed-point
format and added to the contents of the 24-bit accumulator.
The integration continues until the monitor period timer reaches
a count of 1.
When the monitor period timer reaches a count of 1, the square
root of the value in the accumulator is taken and transferred,
after some formatting, to the signal monitor holding register, which
can be read through the SPI port or output through the SPORT
serial port. The monitor period timer is reloaded with the value
in the SMPR, and the countdown is restarted. In addition, the
first input sample signal power is updated in the accumulator,
and the accumulation continues with the subsequent input
samples.
Rev. B | Page 35 of 52
AD9640
Figure 69 illustrates the rms magnitude monitoring logic.
DOWN
COUNTER
IS COUNT = 1?
LOAD
CLEAR
ACCUMULATOR
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
LOAD
06547-092
FROM
INPUT
PORTS
Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitor result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in dBFS
from the MAG value in the register. Note that if the signal monitor
period (SMP) is a power of 2, the second term in the equation
becomes 0.
MAG
SMP
RMS Magnitude = 20 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log2 (SMP )] ⎤⎥
2
2
⎝
⎠
⎣
⎦
For ms magnitude mode, the value in the SMR is a 20-bit fixedpoint number. The following equation can be used to determine
the ms magnitude in dBFS from the MAG value in the register.
Note that if the SMP is a power of 2, the second term in the
equation becomes 0.
MAG
SMP
MS Magnitude = 10 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log2 (SMP )] ⎤⎥
2
2
⎝
⎠
⎣
⎦
The monitor period timer is reloaded with the value in the SMPR
register, and the countdown is restarted. The internal count
register is also cleared to a value of 0. Figure 70 illustrates the
threshold crossing logic. The value in the SMR register is the
number of samples that have a magnitude greater than the
threshold register.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
FROM
MEMORY
MAP
CLEAR
A COMPARE
A>B
COMPARE
A>B
TO
LOAD
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
B
UPPER
THRESHOLD
REGISTER
06547-046
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register, which can be read through the SPI port or output
through the SPORT serial port.
Figure 70. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register.
They are the signal monitor enable bit and the complex power
calculation mode enable bit.
Signal Monitor Enable Bit
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable time
period (given by the SMPR) to count the number of times it
crosses a certain programmable threshold value. This mode is set
by programming Logic 1x (where x is a don’t care bit) in the
signal monitor mode bits of the signal monitor control register
or by setting the threshold crossing output enable bit in the
signal monitor SPORT control register. Before activating this
mode, the user needs to program the 24-bit SMPR and the
13-bit upper threshold register for each individual input port.
The same upper threshold register is used for both signal monitoring and gain control (see the ADC Overrange and Gain
Control section).
After entering this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the upper threshold
register (programmed previously) on each input clock cycle.
If the input signal has a magnitude greater than the upper
threshold register, the internal count register is incremented by 1.
The initial value of the internal count register is set to 0. This
comparison and incrementing of the internal count register
continues until the monitor period timer reaches a count of 1.
The signal monitor enable bit, Bit 0 of Register 0x112, enables
operation of the signal monitor block. If the signal monitor
function is not needed in a particular application, this bit should
be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing
the I data and Channel B is digitizing the Q data for a complex
input signal (or vice versa). In this mode, the power reported is
equal to the following:
I 2 + Q2
This result is presented in the Signal Monitor DC Value Channel A
register if the signal monitor mode bits are set to 00. The Signal
Monitor DC Value Channel B register continues to compute the
Channel B value.
DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
Rev. B | Page 36 of 52
AD9640
DC Correction Bandwidth
SIGNAL MONITOR SPORT OUTPUT
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing Bits[5:2] of the signal
monitor dc correction control register, located at Address 0x10C.
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
f
DC _ Corr _ BW = 2− k − 14 × CLK
2× π
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and
SMI SDO (SPORT data output). The SPORT is the master and
drives all three SPORT output pins on the chip.
where:
k is the 4 bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
fCLK is the ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and in Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a 14-bit
value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
SMI SCLK
The data output and frame sync are driven on the positive edge of
the SMI SCLK. The SMI SCLK has three possible baud rates: 1/2,
1/4, or 1/8 the ADC clock rate, based on the SPORT controls. The
SMI SCLK can also be gated off when not sending any data, based
on the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI
SCLK when it is not needed can reduce any coupling errors back
into the signal path, if these prove to be a problem in the system.
Doing so, however, has the disadvantage of spreading the frequency
content of the clock. If desired, the SMI SCLK can be left running
to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data
is sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more rms/ms magnitude,
peak level, and threshold crossing values from each datapath in
the stated order. If enabled, the data is sent, rms first, followed by
peak and threshold, as shown in Figure 71.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction
value can be added to the output data signal path by setting Bit 1
of Register 0x10C.
GATED, BASED ON CONTROL
SMI SCLK
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
PK CH A
16 CYCLES
THR CH A
MSB
16 CYCLES
RMS/MS CH B LSB
20 CYCLES
PK CH B
16 CYCLES
THR CH B
RMS/MS CH A
06547-094
SMI SDO
16 CYCLES
Figure 71. Signal Monitor SPORT Output Timing (RMS/MS, Peak, and Threshold Enabled)
GATED, BASED ON CONTROL
SMI SCLK
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
THR CH A
16 CYCLES
MSB
RMS/MS CH B LSB
20 CYCLES
THR CH B
16 CYCLES
Figure 72. Signal Monitor SPORT Output Timing (RMS/MS and Threshold Enabled)
Rev. B | Page 37 of 52
RMS/MS CH A
06547-095
SMI SDO
AD9640
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9640 includes built-in test features to enable verification
of the integrity of each channel as well as to facilitate board level
debugging. A built-in self-test (BIST) feature is included that
verifies the integrity of the digital data path of the AD9640.
Various output test options are also provided to place predictable
values on the outputs of the AD9640.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9640 signal path. When enabled, the test runs from an internal
PN source through the digital data path starting at the ADC
block output. The BIST sequence runs for 512 cycles and stops.
The BIST signature value for Channel A or Channel B is placed
in Register 0x024 and Register 0x025. If one channel is chosen,
its BIST signature is written to the two registers. If both channels
are chosen, the results from the A channel are placed in the
BIST signature register.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or started from the beginning,
based on the value programmed in Register 0x00E, Bit 2. The
BIST signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 25. When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital backend blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Rev. B | Page 38 of 52
AD9640
CHANNEL/CHIP SYNCHRONIZATION
The AD9640 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful to guarantee synchronized
sample clocks across multiple ADCs. The signal monitor block
can also be synchronized using the SYNC input allowing properties
of the input signal to be measured during a specific time period.
The input clock divider can be enabled to synchronize on a single
occurrence of the sync signal or on every occurrence. The signal
monitor block is synchronized on every SYNC input signal.
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 8. The SYNC input should be driven using a singleended CMOS-type signal.
Rev. B | Page 39 of 52
AD9640
SERIAL PORT INTERFACE (SPI)
The AD9640 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This gives the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields, which are documented in the Memory Map section. For
detailed operational information, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
There are three pins that define the SPI of this ADC. They are
the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see
Table 22). The SCLK/DFS (a serial clock) is used to synchronize
the read and write data presented from and to the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB (chip select bar) is an active-low control
that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is an input and output depending on the
instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active-low control that gates the read
and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 73
and Table 8.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB may stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in high impedance mode. This mode
turns on any SPI pin secondary functions.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB first mode or LSB first mode. MSB
first is the default on power-up and can be changed via the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 22 comprise the physical interface
between the user’s programming device and the serial port of
the AD9640. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is utilized
for other devices, it may be necessary to provide buffers between
this bus and the AD9640 to keep these signals from transitioning
at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Digital Outputs section describes the strappable
functions supported on the AD9640.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits. All data is composed of 8-bit words.
The first bit of the first byte in a multibyte serial data transfer frame
indicates whether a read command or a write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
Rev. B | Page 40 of 52
AD9640
CONFIGURATION WITHOUT THE SPI
SPI ACCESSIBLE FEATURES
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone, CMOScompatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
A brief description of general features accessible via the SPI
follows. These features are described in detail in the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. The
AD9640 part-specific features are described in detail following
Table 25, the external memory map register table.
Table 23. Mode Selection
Clock
Offset
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
Pin
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
AGND (default)
Feature Name
Modes
Configuration
Duty cycle stabilizer enabled.
Duty cycle stabilizer disabled.
Twos complement enabled.
Offset binary enabled.
Outputs in high impedance.
Outputs enabled.
Chip in power-down or
standby.
Normal operation.
tHIGH
tDS
tS
Table 24. Features Accessible Using the SPI
tDH
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows user to set either power-down mode or
standby mode.
Allows user to access the DCS via the SPI.
Allows user to digitally adjust the converter
offset.
Allows user to set test modes to have known
data on output bits.
Allows user to set up outputs.
Allows user to set the output clock polarity.
Allows user to vary the DCO delay.
Allows user to set the reference voltage.
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
06547-049
SDIO DON’T CARE
DON’T CARE
Figure 73. Serial Port Interface Timing Diagram
Rev. B | Page 41 of 52
AD9640
MEMORY MAP
READING THE MEMORY MAP TABLE
Logic Levels
Each row in the memory map table has eight bit locations. The
memory map is roughly divided into four sections: chip configuration and ID register map (Address 0x00 to Address 0x02); ADC
setup, control, and test (Address 0x08 to Address 0x25); the
channel index and transfer register map (Address 0x05 to
Address 0xFF); and digital feature control (Address 0x100 to
Address 0x11B).
An explanation of logic level terminology follows:
Starting from the right hand column, the memory map register
in Table 25 documents the default hex value for each hex address
shown. The column with the heading Bit 7 (MSB) is the start
of the default hex value given. For example, Address 0x18, VREF
select, has a hex default value of 0xC0. This means Bit 7 = 1,
Bit 6 = 1, and the remaining bits are 0s. This setting is the default
reference selection setting. The default value uses a 2.0 V peakto-peak reference. For more information on this function and
others, see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled by
Register 0x00 to Register 0xFF. The remaining registers, from
Register 0x100 to Register 0x11B, are documented in the Memory
Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 25
are currently not supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
•
•
“Bit is set” is synonymous with “Bit is set to Logic 1” or
“Writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “Bit is set to Logic 0” or
“Writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel.
In these cases, channel address locations are internally duplicated
for each channel. These registers are designated in the parameter
name column of Table 25 as local registers. These local registers
can be accessed by setting the appropriate Channel A or Channel B
bits in Register 0x05. If both bits are set, the subsequent write
affects the registers of both channels. In a read cycle, only
Channel A or Channel B should be set to read one of the two
registers. If both bits are set during an SPI read cycle, the part
returns the value for Channel A. Registers designated as global
in the parameter name column of Table 25 affect the entire part
or the channel features where independent settings are not
allowed between the channels. The settings in Register 0x05
do not affect the global registers.
Default Values
Coming out of reset, critical registers are loaded with default
values. The default values for the registers are given in the
memory map register table, Table 25.
Rev. B | Page 42 of 52
AD9640
EXTERNAL MEMORY MAP
Table 25. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI Port
Configuration
(Global)
0x01
Chip ID
(Global)
0x02
Chip Grade
(Global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
8-bit Chip ID[7:0]
(AD9640 = 0x11)
(default)
Open
Open
Speed grade ID
00 = 150 MSPS
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Open
Open
Open
Open
Default
Value
(Hex)
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
0x11
Read
only
Read
only
Channel Index and Transfer Registers
0x05
Channel Index
Open
Open
Open
Open
Open
Open
Data
Channel B
(default)
Data
Channel A
(default)
0x03
0xFF
Device Update
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions
0x08
Power Modes
Open
Open
Open
Open
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
0x00
0x09
Global Clock
(Global)
Open
Open
External
powerdown pin
function
(global)
0 = pdwn
1 = stndby
Open
Open
Open
Open
Open
0x01
0x0B
Clock Divide
(Global)
Open
Open
Open
Open
Open
0x0D
Test Mode
(Local)
Open
Open
Reset PN
long gen
Reset
PNshort
gen
Open
Rev. B | Page 43 of 52
Duty cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checker board
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Speed grade
ID used to
differentiate
devices
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active
0x00
When set,
the test data
is placed on
the output
pins in place of
normal data
AD9640
Addr
(Hex)
0x0E
0x10
0x14
Register
Name
BIST Enable
(Local)
Offset Adjust
(Local)
Output Mode
Bit 7
(MSB)
Open
Bit 6
Open
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS:
1 V to 1.8 V
CMOS or
reduced:
LVDS
(global)
Invert DCO
clock
Output type
0 = CMOS
1 = LVDS
(global)
Open
Output
enable bar
(local)
Open
Open
Open
Open
Open
0x16
Clock Phase
Control
(Global)
0x17
DCO Output
Delay (Global)
Open
0x18
VREF Select
(Global)
Reference voltage selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Bit 5
Open
Bit 4
Open
Open
Open
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open
Open
Open
Open
Open
Open
Open
Open
Open
Clock
divider next
sync only
Clock
divider
sync
enable
Fast Detect Mode Select[2:0]
Fine Upper Threshold[7:0]
Open
Fine Upper Threshold[12:8]
Fine Lower Threshold[7:0]
Open
Open
Open
Configures the
outputs and
the format of
the data
0x00
Allows
selection of
clock delays
into the input
clock divider
0x00
0xC0
Read only
0x104
Open
0x00
0x00
Open
0x109
Output
invert
(local)
BIST signature[15:8]
Open
Open
0x00
Read only
Open
0x108
Open
Default
Notes/
Comments
0x00
SM sync
enable
0x107
Bit 1
Open
Default
Value
(Hex)
0x00
BIST signature[7:0]
BIST Signature
LSB (Local)
0x25
BIST Signature
MSB (Local)
Digital Feature Control
0x100
Sync Control
(Global)
0x106
Bit 2
Reset BIST
sequence
Offset adjust in LSBs from +31 to −32
(twos complement format)
0x24
Fast Detect
Control (Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Bit 3
Open
Bit 0
(LSB)
BIST enable
Fine Lower Threshold[12:8]
Rev. B | Page 44 of 52
Master
sync
enable
0x00
Fast detect
enable
0x00
0x00
0x00
0x00
0x00
AD9640
Addr
(Hex)
0x10C
Register
Name
Signal Monitor
DC Correction
Control
(Global)
0x10D
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
0x10E
0x10F
0x110
0x111
0x112
Signal Monitor
Control
(Global)
0x113
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor
Result
Channel A
Register 2
(Global)
Signal Monitor
Result
Channel B
Register 0
(Global)
0x114
0x115
0x116
0x117
0x118
0x119
Bit 7
(MSB)
Open
Bit 6
DC
correction
freeze
Bit 5
Bit 4
Bit 3
Bit 2
DC Correction Bandwidth[3:0]
Bit 1
DC
correction
for signal
path
enable
Bit 0
(LSB)
DC
correction
for SM
enable
Default
Value
(Hex)
0x00
DC Value Channel A[7:0]
Open
Open
Read only
DC Value Channel A[13:8]
Read only
DC Value Channel B[7:0]
Open
Open
Open
RMS/MS
magnitude
output
enable
Peak
power
output
enable
Complex
power
calculation
mode
enable
Open
Open
Open
Open
Read only
DC Value Channel B[13:8]
Open
Threshold
crossing
output
enable
SPORT SMI
SPORT
CLK divide
SMI SCLK
sleep
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
Open
Signal monitor mode
MS
mode
00 = RMS/MS Magnitude
0=
01 = peak power
rms
1x = threshold count
1 = ms
Signal Monitor Period[7:0]
Default
Notes/
Comments
Read only
Signal
monitor
SPORT
output
enable
0x04
Signal
monitor
enable
0x00
0x40
In ADC clock
cycles
Signal Monitor Period[15:8]
0x00
In ADC clock
cycles
Signal Monitor Period[23:16]
0x00
In ADC clock
cycles
Signal Monitor Result Channel A[7:0]
Read only
Signal Monitor Result Channel A[15:8]
Read only
Open
Signal Monitor Value Channel A[19:16]
Signal Monitor Result Channel B[7:0]
Rev. B | Page 45 of 52
Read only
Read only
AD9640
Addr
(Hex)
0x11A
0x11B
Register
Name
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor
Result
Channel B
Register 2
(Global)
Bit 7
(MSB)
Bit 6
Bit 5
Open
Open
Open
Bit 4
Bit 3
Bit 2
Signal Monitor Result Channel B[15:8]
Open
MEMORY MAP REGISTER DESCRIPTION
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external SYNC input to
the signal monitor block. The sync signal is passed when Bit 7
is high and Bit 0 is high. This is continuous sync mode.
Bits[6:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the sync enable bit (Address 0x100[0]) is high and the clock
divider sync enable (Address 0x100[1]) is high, Bit 2 allows the
clock divider to sync to the first sync pulse it receives and ignore
the rest. Address 0x100[1] resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 1
Bit 0
(LSB)
Signal Monitor Result Channel B[19:16]
Default
Value
(Hex)
Default
Notes/
Comments
Read only
Read only
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block
and, if the ADC magnitude exceeds this threshold value, the
F_UT flag is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
These registers provide a fine lower limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block
and, if the ADC magnitude is less than this threshold value, the
F_LT flag is set.
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is no longer updated
to the signal monitoring block. It holds the last dc value it
calculated.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[5:2]—DC Correction Bandwidth
Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output bits according
to Table 17.
These bits set the averaging time of the signal monitor dc correction function. It is a 4-bit word that sets the bandwidth of the
correction block (see Table 26).
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect bits. When the fast detect
outputs are disabled, the outputs go into a high impedance state.
In LVDS mode, when the outputs are interleaved, the outputs go
high-Z only if both channels are turned off (power-down/standby/
output disabled). If only one channel is turned off (power-down/
standby/output disabled), the fast detect outputs repeat the data
of the active channel.
Rev. B | Page 46 of 52
AD9640
Bit 5—Peak Power Output Enable
Table 26. DC Correction Bandwidth
DC Correction Control Register 0x10C[5:2]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bandwidth (Hz)
1218.56
609.28
304.64
152.32
76.16
38.08
19.04
9.52
4.76
2.38
1.19
0.60
0.30
0.15
0.15
0.15
Bit 1—DC Correction for Signal Path Enable
Setting Bit 1 high causes the output of the dc measurement
block to be summed with the data in the signal path to remove
the dc offset from the signal path.
Bit 0—DC Correction for SM Enable
Bit 0 enables the dc correction function in the signal monitoring
block. The dc correction is an averaging function that can be
used by the signal monitor to remove dc offset in the signal.
Removing this dc from the measurement allows a more accurate
reading.
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10D, Bits[7:0]—Channel A DC Value[7:0]
Register 0x10E, Bits[7:0]—Channel A DC Value[13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x10F Bits[7:0]—Channel B DC Value[7:0]
Register 0x110 Bits[7:0]—Channel B DC Value[13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Bit 5 enables the 13-bit peak measurement as output on
the SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 13-bit threshold measurement as output on
the SPORT.
Bits[3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio
from the input clock. A value of 0x01 sets divide by 2 (default),
a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1— SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
Bit 0—Signal Monitor SPORT Output Enable
When set, Bit 0 enables the SPORT output of the signal monitor
to begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
This mode assumes I data is present on one channel and Q data
is present on the opposite channel. The result reported is the
complex power, measured as
I 2 + Q2
Bits[6:4]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits[2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for data output
to Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1 to
0x00 selects rms/ms power output; setting these bits to 0x01
selects peak power output; and setting 0x10 or 0x11 selects
threshold crossing output.
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits[7:0]—Signal Monitor Period[7:0]
Register 0x114, Bits[7:0]—Signal Monitor Period[15:8]
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]
Bit 6—RMS/MS Magnitude Output Enable
These bits enable the 20-bit rms or ms magnitude measurement
as output on the SPORT.
This 24-bit value sets the number of clock cycles over which the
signal monitor performs its operation. Although this register
defaults to 64 (0x40), the minimum value for this register is 128
(0x80) cycles – writing values less than 128 can cause inaccurate
results.
Rev. B | Page 47 of 52
AD9640
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x116, Bits[7:0]—Signal Monitor Result
Channel A[7:0]
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x119, Bits[7:0]— Signal Monitor Result
Channel B[7:0]
Register 0x117, Bits[7:0]—Signal Monitor Result
Channel A[15:8]
Register 0x11A, Bits[7:0]—Signal Monitor Result
Channel B[15:8]
Register 0x118, Bits[7:4]—Reserved
Register 0x11B, Bits[7:4]—Reserved
Register 0x118, Bits[3:0]—Signal Monitor Result
Channel A[19:16]
Register 0x11B, Bits[3:0]—Signal Monitor Result
Channel B[19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel A. The content is dependent on the
settings in Register 0x112[2:1].
This 20-bit value contains the result calculated by the signal
monitoring block for Channel B. The content is dependent on
the settings in Register 0x112[2:1].
Rev. B | Page 48 of 52
AD9640
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9640 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9640, it is recommended
that two separate 1.8 V supplies be used: one supply should be
used for analog (AVDD) and digital (DVDD), and a separate
supply should be used for the digital outputs (DRVDD). The
AVDD and DVDD supplies, while derived from the same
source, should be isolated with a ferrite bead or filter choke
and separate decoupling capacitors. The user can employ
several different decoupling capacitors to cover both high
and low frequencies. These should be located close to the
point of entry at the PC board level and close to the part’s
pins with minimal trace length.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. These vias should be filled or
plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the two during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and PCB. See the evaluation
board for a PCB layout example. For detailed information about
packaging and PCB layout of chip scale packages, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 47.
A single PCB ground plane should be sufficient when using the
AD9640. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
RBIAS
LVDS Operation
Reference Decoupling
The AD9640 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed
using the SPI configuration registers after power-up. When the
AD9640 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current may be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9640, but it should be taken into account when considering the maximum DRVDD current for the part.
The VREF pin should be externally decoupled to ground with a
low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic, low
ESR capacitor.
To avoid this additional DRVDD current, the AD9640 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed into LVDS mode via the SPI port, the OEB
pin can be taken low to enable the outputs.
The AD9640 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9640 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask), copper plane on the PCB should mate to the
AD9640 exposed paddle, Pin 0.
Rev. B | Page 49 of 52
AD9640
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
7.25
7.10 SQ
6.95
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
080108-C
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 74. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
PIN 1
INDICATOR
48
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
7.65
7.50 SQ
7.35
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 75. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
Rev. B | Page 50 of 52
041509-A
TOP VIEW
AD9640
ORDERING GUIDE
Model
AD9640ABCPZ-150 1, 2
AD9640ABCPZ-1251, 2
AD9640ABCPZ-1051, 2
AD9640ABCPZ-801, 2
AD9640ABCPZRL7-801, 2
AD9640BCPZ-1501
AD9640BCPZ-1251
AD9640BCPZ-1051
AD9640BCPZ-801
AD9640-150EBZ1
AD9640-125EBZ1
AD9640-105EBZ1
AD9640-80EBZ1
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Recommended for use in new designs; reference PCN 09_0156.
Rev. B | Page 51 of 52
Package Option
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-3
CP-64-3
CP-64-3
CP-64-3
AD9640
NOTES
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06547-0-12/09(B)
Rev. B | Page 52 of 52
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