ON NLSX3013FCT1G 8-bit 100 mb/s configurable dual-supply level translator Datasheet

NLSX3013
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3013 is a 8−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O VCC− and I/O
VL−ports are designed to track two different power supply rails, VCC
and VL respectively. The VCC supply rail is configurable from 1.3 V
to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC
− 0.4) V. This allows lower voltage logic signals on the VL side to be
translated into higher voltage logic signals on the VCC side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both VCC and VL. The EN signal is designed to track
VL.
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MARKING DIAGRAM
for NLSX3013FCT1G
3013F
AYWW
G
for NLSX3013BFCT1G
A1
20 PIN FLIP−CHIP
3013B
CASE 766AK
AYWW
G
A
Y
WW
G
Features
• Wide High−Side VCC Operating Range: 1.3 V to 4.5 V
•
•
•
•
•
•
Wide Low−Side VL Operating Range: 0.9 V to (VCC − 0.4) V
High−Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.8 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Powerup Sequencing
Small packaging: 2.03 mm x 2.54 mm 20 Pin Flip−Chip
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
• PC and Laptops
• ESD Protection for All Pins: Human Body Model (HBM) > 6000 V
= Assembly Location
= Year
= Work Week
= Pb−Free Package
LOGIC DIAGRAM
EN
VL
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
I/O VL5
I/O VCC5
I/O VL6
I/O VCC6
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 3
1
Publication Order Number:
NLSX3013/D
NLSX3013
P
One−Shot
VL
+1.8V
VCC
+3.6V
VL
+1.8 V System
VCC
NLSX3013
N
One−Shot
+3.6 V System
I/O VL
I/O1
I/On
GND EN
I/O VL1
I/O VCC1
I/O1
I/O VLn I/O VCCn
EN
GND
I/On
I/O VCC
P
One−Shot
GND
N
One−Shot
Figure 1. Typical Application Circuit
Figure 2. Simplified Functional Diagram (1 I/O Line)
(EN = 1)
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
EN
Operating Mode
VCC
VCC Input Voltage
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
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2
NLSX3013
1
2
3
4
5
I/O VL2
I/O VL4
VL
EN
I/O VL6
B
I/O VL1
I/O VL3
I/O VL5
I/O VL7
I/O VL8
C
I/O VCC1
I/O VCC3
I/O VCC5
I/O VCC7
I/O VCC8
I/O VCC2
I/O VCC4
VCC
GND
I/O VCC6
A
D
Figure 3. 20 Flip−Chip (2.54 mm x 2.03 mm)
(Top View)
PIN ASSIGNMENT
Pin
Name
Description
A1
I/O VL2
I/O Port 2, Referenced to VL
A2
I/O VL4
I/O Port 4, Referenced to VL
A3
VL
VL Input Voltage
A4
EN
Output Enable
A5
I/O VL6
I/O Port 6, Referenced to VL
B1
I/O VL1
I/O Port 1, Referenced to VL
B2
I/O VL3
I/O Port 3, Referenced to VL
B3
I/O VL5
I/O Port 5, Referenced to VL
B4
I/O VL7
I/O Port 7, Referenced to VL
B5
I/O VL8
I/O Port 8, Referenced to VL
C1
I/O VCC1
I/O Port 1, Referenced to VCC
C2
I/O VCC3
I/O Port 3, Referenced to VCC
C3
I/O VCC5
I/O Port 5, Referenced to VCC
C4
I/O VCC7
I/O Port 7, Referenced to VCC
C5
I/O VCC8
I/O Port 8, Referenced to VCC
D1
I/O VCC2
I/O Port 2, Referenced to VCC
D2
I/O VCC4
I/O Port 4, Referenced to VCC
D3
VCC
VCC Input Voltage
D4
GND
Ground
D5
I/O VCC6
I/O Port 6, Referenced to VCC
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3
NLSX3013
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
VCC Supply Voltage
−0.5 to +5.5
V
VL
VL Supply Voltage
−0.5 to +5.5
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to (VCC + 0.3)
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to (VL + 0.3)
V
VEN
Enable Control Pin DC Input Voltage
−0.5 to +5.5
V
IIK
Input Diode Clamp Current
−50
VI < GND
mA
IOK
Output Diode Clamp Current
−50
VO < GND
mA
ICC
DC Supply Current Through VCC
$100
mA
IL
DC Supply Current Through VL
$100
mA
IGND
DC Ground Current Through Ground Pin
$100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VL
Parameter
Max
Unit
VCC Supply Voltage
1.3
4.5
V
VL Supply Voltage
0.9
VCC − 0.4
V
GND
4.5
V
GND
GND
4.5
4.5
V
−40
+85
°C
0
10
ns
VEN
Enable Control Pin Voltage
VIO
Bus Input/Output Voltage
TA
Operating Temperature Range
DI/DV
Min
I/O VCC
I/O VL
Input Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
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4
NLSX3013
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
Test Conditions
(Note 1)
Parameter
VCC (V)
(Note 2)
VL (V)
(Note 3)
Min
Typ
(Note 4)
Max
Unit
VIHC
I/O VCC Input HIGH
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 *
VCC
−
−
V
VILC
I/O VCC Input LOW
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 *
VCC
V
VIHL
I/O VL Input HIGH
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VILL
I/O VL Input LOW
Voltage
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
VIH
Control Pin Input HIGH
Voltage
TA = +25°C
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VIL
Control Pin Input LOW
Voltage
TA = +25°C
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
VOHC
I/O VCC Output HIGH
Voltage
I/O VCC Source Current =
20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 *
VCC
−
−
V
VOLC
I/O VCC Output LOW
Voltage
I/O VCC Sink Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 *
VCC
V
VOHL
I/O VL Output HIGH
Voltage
I/O VL Source Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
0.8 * VL
−
−
V
VOLL
I/O VL Output LOW
Voltage
I/O VL Sink Current = 20 mA
1.3 to 4.5
0.9 to (VCC – 0.4)
−
−
0.2 * VL
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
POWER CONSUMPTION
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
−405C to +855C
Min
Typ
Max
Unit
IQ−VCC
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VCC
I/O VCCn = VCC or I/O VLn = VL and Io = 0
−
−
1.0
mA
IQ−VL
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VL
I/O VCCn = VCC or I/O VLn = VL and Io = 0
−
−
1.0
mA
−
−
2.0
Symbol
Parameter
EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = (VCC −
0.2 V) and Io = 0
ITS−VCC
ITS−VL
IOZ
IEN
< (VCC – 0.2)
VCC Tristate Output
Mode Supply
Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
−
−
1.0
mA
VL Tristate Output
Mode Supply
Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
−
−
0.2
mA
−
−
2.0
I/O Tristate Output
Mode Leakage
Current
EN = 0 V
−
−
0.15
−
−
2.0
Output Enable Pin
Input Current
−
−
−
1.0
EN = 0 V
VCC − 0.2
1.3 to 3.6 0.9 to (VCC – 0.4)
EN = 0 V
VCC – 0.2
1.3 to 3.6 0.9 to (VCC – 0.4)
mA
mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
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5
NLSX3013
TIMING CHARACTERISTICS
−405C to +855C
Symbol
Parameter
Test Conditions
(Note 8)
VCC (V)
(Note 9)
VL (V)
(Note 10)
Min
Typ
(Note 11)
Max
Unit
tR−VCC
I/O VCC Rise Time
(Output = I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.7
2.4
ns
tF−VCC
I/O VCC Falltime
(Output = I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.5
1.0
ns
tR−VL
I/O VL Risetime
(Output = I/O_VL)
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
1.0
3.8
ns
tF−VL
I/O VL Falltime
(Output = I/O_VL)
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.6
1.2
ns
ZO−VCC
I/O VCC One−Shot
Output Impedance
1.3 to 4.5
0.9 to (VCC – 0.4)
30
W
ZO−VL
I/O VL One−Shot
Output Impedance
1.3 to 4.5
0.9 to (VCC – 0.4)
30
W
tPD_VL−VCC Propagation Delay
(Output = I/O_VCC,
tPHL, tPLH)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
4.5
9.3
ns
tPD_VCC−VL Propagation Delay
(Output = I/O_VL,
tPHL, tPLH)
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
3.0
6.5
ns
Channel−to−Channel
Skew (Output =
I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.2
0.3
nS
tSK_VCC−VL Channel−to−Channel
Skew
(Output = I/O_VL)
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
0.2
0.3
nS
(Output = I/O_VCC,
CIOVCC = 15 pF)
(Output = I/O_VL,
CIOVL = 15 pF)
1.3 to 4.5
0.9 to (VCC – 0.4)
110
> 2.2
> 1.8
140
tSK VL−VCC
Maximum Data Rate
Mb/s
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
10. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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NLSX3013
ENABLE / DISABLE TIME MEASUREMENTS
−405C to +855C
tEN−VL
Unit
0.9 to (VCC – 0.4)
130
180
ns
1.3 to 4.5
0.9 to (VCC – 0.4)
100
150
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
95
185
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
70
110
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
175
250
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
150
190
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
180
250
ns
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC – 0.4)
160
220
ns
VL (V)
(Note 14)
Turn−On Enable Time (Output =
I/O_VCC, tpZH)
CIOVCC = 15 pF
1.3 to 4.5
Turn−On Enable Time (Output =
I/O_VCC, tpZL)
CIOVL = 15 pF
Turn−On Enable Time (Output =
I/O_VL, tpZH)
Turn−On Enable Time (Output =
I/O_VL, tpZL)
tDIS−VCC Turn−Off Disable Time (Output =
I/O_VCC, tpHZ)
Propagation Delay (Output =
I/O_VCC, tPLZ)
tDIS−VL
Max
VCC (V)
(Note 13)
Parameter
tEN−VCC
Typ
(Note 15)
Test Conditions
(Note 12)
Symbol
Turn−Off Disable Time (Output =
I/O_VL, tpHZ)
Propagation Delay (Output = I/O_VL,
tPLZ)
Min
12. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
13. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
14. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
15. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 °C. All units are production tested at TA = +25 °C. Limits over the operating
temperature range are guaranteed by design.
NLSX3013
VL
VCC
NLSX3013
VL
EN
I/O VL
EN
I/O VL
I/O VCC
Source
VCC
I/O VCC
CIOVL
CIOVCC
Source
tRISE/FALL v
3 ns
I/O VL
90%
50%
10%
tPD_VL−VCC
I/O VCC
tRISE/FALL v 3 ns
I/O VCC
90%
50%
10%
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 4. Driving I/O VL Test Circuit and Timing
tR−VL
Figure 5. Driving I/O VCC Test Circuit and Timing
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NLSX3013
VCC
2xVCC
OPEN
R1
PULSE
GENERATOR
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
EN
VCC
90%
50%
10%
GND
GND
tPZL
tPHL
90%
50%
10%
tR
VL
50%
Output
Output
HIGH
IMPEDANCE
50%
tPZH
tF
tPLZ
tPHZ
10%
VOL
90%
VOH
50%
Figure 7. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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8
HIGH
IMPEDANCE
NLSX3013
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
Enable Input (EN)
The NLSX3013 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX3013 consists of four bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high−to−low and low−to−high transitions.
The NLSX3013 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has Over−Voltage
Tolerant (OVT) protection.
Uni−Directional versus Bi−Directional Translation
The NLSX3013 can function as a non−inverting
uni−directional translator. One advantage of using the
translator as a uni−directional device is that each I/O pin
can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Input Driver Requirements
Auto sense translators such as the NLSX3013 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent to in the opposite direction.
For proper operation, the input driver to the auto sense
translator should be capable of driving 20 mA of peak
output current with an output impedance less than 25 W.
The bi−directional configuration of the translator results in
both input stages being active for a very short time period.
Although the peak current from the input signal circuit is
relatively large, the average current is small and consistent
with a standard CMOS input stage.
Power Supply Guidelines
During normal operation, supply voltage VL should be
less than or equal to VCC. The sequencing of the power
supplies will not damage the device during the power up
operation.
The enable pin should be used to enter the low current
tri−state mode, rather than setting either the VL or VCC
supplies to 0 V. The NLSX3013 will not be damaged if
either VL or VCC is equal to 0 V while the other supply
voltage is at a nominal operating value; however, the
operation of the translator cannot be guaranteed during
single supply operation.
For optimal performance, 0.01 to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the power supply voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
Output Load Requirements
The NLSX3013 is designed to drive CMOS inputs.
Resistive pullup or pulldown loads of less than 50 kW
should not be used with this device. The NLSX3373 or
NLSX3378 open−drain auto sense translators are alternate
translator options for an application such as the I2C bus that
requires pullup resistors.
ORDERING INFORMATION
Device
NLSX3013FCT1G
NLSX3013BFCT1G
Package
Shipping†
20 Pin Flip−Chip
(Pb−Free)
3000 / Tape & Reel
20 Pin Flip−Chip
(Backside Laminate Coating)
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NLSX3013
PACKAGE DIMENSIONS
20 PIN FLIP−CHIP CSP, 2.54x2.03, 0.5P
CASE 766AK
ISSUE A
ÎÎ
PIN A1
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
D
E
2X
DIM
A
A1
A2
b
D
D1
E
E1
e
0.10 C
0.10 C
2X
TOP VIEW
A1
0.10 C
A2
A
0.05 C
20X
C
SIDE VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
PACKAGE
OUTLINE
20X
0.25
D1
20X
0.05 C A B
0.03 C
A1
e
b
MILLIMETERS
MIN
MAX
0.66
--0.21
0.27
0.33
0.39
0.29
0.34
2.54 BSC
2.00 BSC
2.03 BSC
1.50 BSC
0.50 BSC
0.50
PITCH
D
C
E1
B
0.50
PITCH
A
1
2
3
4
5
e/2
DIMENSION: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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