ICST ICS950218 Programmable timing control hub tm for p4 tm Datasheet

ICS950218
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
•
3 - Pairs of differential CPU clocks (differential current
mode)
•
3 - 3V66 @ 3.3V
•
10 - PCI @ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
2 - REF @ 3.3V, 14.318MHz
•
1 - 48_66MHz selectable @ 3.3V fixed
•
1 - 24_48MHz selectable @ 3.3V
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
Pin Configuration
Bit2
Bit7
Bit6
Bit5
Bit4
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
0
102.00
68.00
34.00
0
1
105.00
70.00
35.00
1
0
108.00
72.00
36.00
0
1
1
111.00
74.00
37.00
0
1
0
0
114.00
76.00
0
1
0
1
117.00
78.00
39.00
0
0
1
1
0
120.00
80.00
40.00
0
0
1
1
1
123.00
82.00
41.00
0
1
0
0
0
126.00
72.00
36.00
0
1
0
0
1
130.00
74.30
37.10
0
1
0
1
0
136.00
68.00
34.00
0
1
0
1
1
140.00
70.00
35.00
0
1
1
0
0
144.00
72.00
36.00
0
1
1
0
1
148.00
74.00
37.00
0
1
1
1
0
152.00
76.00
38.00
0
1
1
1
1
156.00
78.00
39.00
1
0
0
0
0
160.00
80.00
40.00
1
0
0
0
1
164.00
82.00
41.00
1
0
0
1
0
166.60
66.60
33.30
1
0
0
1
1
170.00
68.00
34.00
1
0
1
0
0
175.00
70.00
35.00
1
0
1
0
1
180.00
72.00
36.00
1
0
1
1
0
185.00
74.00
37.00
1
0
1
1
1
190.00
76.00
38.00
1
1
0
0
0
66.80
66.80
33.40
1
1
0
0
1
100.20
66.80
33.40
1
1
0
1
0
133.60
66.80
33.40
1
1
0
1
1
200.40
66.80
33.40
1
1
1
0
0
66.60
66.60
33.30
1
1
1
0
1
100.00
66.60
33.30
1
1
1
1
0
200.00
66.60
33.30
1
1
1
1
1
133.33
66.60
33.30
0466B—03/17/04
38.00
*MULTISEL1/REF1
VDDREF
X1
X2
GND
*FS2/PCICLK0
*FS3/PCICLK1
** SEL48_24#/PCICLK2
VDDPCI
*FS4/PCICLK3
PCICLK4
PCICLK5
GND
PCICLK6
PCICLK7
PCICLK8
PCICLK9
VDDPCI
Vtt_PWRGD#
RESET#
GND
1
*FS0/48MHz
*FS1/24_48MHz
AVDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS950218
Frequency Table
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/MULTSEL0*
GND
VDDCPU
CPUCLKT2
CPUCLKC2
GND
PD#
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
I REF
AVDD
GND
VDD3V66
3V66_0
3V66_1
GND
3V66_2
3V66_48MHz/SEL66_48#*
SCLK
SDATA
48-Pin 300-mil SSOP
1 This output has 2X drive
* Internal Pull-up resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
ICS950218
Integrated
Circuit
Systems, Inc.
General Description
The ICS950218 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950218 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Block Diagram
PLL2
X1
X2
48MHz
24_48MHz
/2
XTAL
OSC
REF (1:0)
3V66_48MHz
3V66
DIVDER
PLL1
Spread
Spectrum
PD#
MULTSEL(1:0)
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
CPU
DIVDER
3
3
PCI
DIVDER
10
3V66
DIVDER
4
Control
Logic
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (9:0)
3V66 (2:0)
RESET#
Config.
I REF
Reg.
0466B—03/17/04
2
ICS950218
Integrated
Circuit
Systems, Inc.
Pin Description
PIN NUMBER
PIN NAME
MULTSEL1
TYPE
IN
DESCRIPTION
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
1
2, 9, 18, 24,
32, 39, 46
REF1
OUT
VDD
PWR
3
X1
IN
4
X2
OUT
GND
PWR
FS2
IN
5, 13, 21, 29,
36, 43, 47
3.3V, 14.318MHz reference clock output.
3 . 3 V p ow e r s u p p l y
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF)
Ground pins for 3.3V supply
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
6
PCICLK0
FS3
OUT
IN
3.3V PCI clock output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
7
PCICLK1
SEL 48_24#
OUT
IN
8
PCICLK2
FS4
OUT
IN
3.3V PCI clock output
This selects the frequency for the 24.48 MHz output. High = 48MHz,
L ow = 2 4 M H z
3.3V PCI clock output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
10
PCICLK3
17, 16, 15, 14, 12, 11 PCICLK (9:4)
OUT
3.3V PCI clock output
OUT
3.3V PCI clock outputs
19
Vtt_PWRGD#
20
RESET#
OUT
3V66 (2:0)
OUT
28, 30, 31
22
23
FS0
48MHz
FS1
24_48MHz
IN
IN
OUT
IN
OUT
This 5V tolerant LVTTL input is a level sensitive strobe used to determine when FS
(4:0) and MULTISEL inputs are valid and are ready to be sampled
(active low)
Real time system reset signal for frequency value or watchdog timmer timeout.
This signal is active low.
3.3V Fixed 66MHz clock outputs for HUB
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Selectable 24 or 48MHz output.
25
SDATA
I/O
Data pin for I2C circuitr y 5V tolerant
26
SCLK
IN
Clock pin for I2C circuitr y 5V tolerant
SEL66_48#
IN
This selects the frequency for the 3V6_48 MHz output High = 66MHz,
Low=48MHz
27
3V66_48MHz
OUT
33
GND
PWR
Ground for CORE PLL
34
AVDD
PWR
Power for CORE PLL 3.3V nominal
35
I REF
OUT
42
PD#
44, 40, 37
45, 41, 38
48
IN
CPUCLKC (2:0)
OUT
CPUCLKT (2:0)
OUT
MULTSEL0
REF0
IN
OUT
Selectable 66 or 48MHz output
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropr iate current.
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
3.3V, 14.318MHz reference clock output.
0466B—03/17/04
3
ICS950218
Integrated
Circuit
Systems, Inc.
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Condition
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
CPUCLK Swing Select Functions
MULTSEL0
MULTSEL1
Board Target
Trace/Term Z
Reference R,
Iref=
Vdd/(3*Rr)
Output
Current
Voh @ Z,
Iref=2.32mA
0
0
60 ohms
Rr = 475 1%
Iref = 2.32mA
Ioh = 5*Iref
0.71V @ 60
0
0
50 ohms
Rr = 4 7 5 1 %
Iref = 2.32mA
Ioh = 5*Iref
0.59V @ 50
0
1
60 ohms
Rr = 475 1%
Iref = 2.32mA
Ioh = 6*Iref
0.85V /2 60
0
1
50 ohms
Rr = 4 7 5 1 %
Iref = 2.32mA
Ioh = 6*Iref
0.71V @ 50
1
0
60 ohms
Rr = 475 1%
Iref = 2.32mA
Ioh = 4*Iref
0.56V @ 60
1
0
50 ohms
Rr = 475 1%
Iref = 2.32mA
Ioh = 4*Iref
0.47V @ 50
1
1
60 ohms
Rr = 4 7 5 1 %
Iref = 2.32mA
Ioh = 7*Iref
0.99V @ 60
1
1
50 ohms
Rr = 475 1%
Iref = 2.32mA
Ioh = 7*Iref
0.82V @ 50
0
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0.75V @ 30
0
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0.62V @ 20
0
1
30 (DC equiv)
Rr = 2 2 1 1 %
Iref = 5mA
Ioh = 6*Iref
0.90V @ 30
0
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 6*Iref
0.75V @ 20
1
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
0.60 @ 20
1
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
0.5V @ 20
1
1
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
1.05V @ 30
1
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
0.84V @ 20
0466B—03/17/04
4
ICS950218
Integrated
Circuit
Systems, Inc.
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
0466B—03/17/04
5
Not acknowledge
stoP bit
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Bit
Bit2 Bit7 Bit6 Bit5
Bit4
FS4 FS3 FS2 FS1 FS0
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
PWD
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010101-
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
0
0
0
0
102.00
68.00
34.00
0
0
0
1
105.00
70.00
35.00
0
0
1
0
108.00
72.00
36.00
0
0
1
1
111.00
74.00
37.00
0
1
0
0
114.00
76.00
38.00
0
1
0
1
117.00
78.00
39.00
0
1
1
0
120.00
80.00
40.00
0
1
1
1
123.00
82.00
41.00
1
0
0
0
126.00
72.00
36.00
1
0
0
1
130.00
74.30
37.10
1
0
1
0
136.00
68.00
34.00
1
0
1
1
140.00
70.00
35.00
1
1
0
0
144.00
72.00
36.00
1
1
0
1
148.00
74.00
37.00
1
1
1
0
152.00
76.00
38.00
1
1
1
1
156.00
78.00
39.00
0
0
0
0
160.00
80.00
40.00
0
0
0
1
164.00
82.00
41.00
0
0
1
0
166.60
66.60
33.30
0
0
1
1
170.00
68.00
34.00
0
1
0
0
175.00
70.00
35.00
0
1
0
1
180.00
72.00
36.00
0
1
1
0
185.00
74.00
37.00
0
1
1
1
190.00
76.00
38.00
1
0
0
0
66.80
66.80
33.40
1
0
0
1
100.20
66.80
33.40
1
0
1
0
133.60
66.80
33.40
1
0
1
1
200.40
66.80
33.40
1
1
0
0
66.60
66.60
33.30
1
1
0
1
100.00
66.60
33.30
1
1
1
0
200.00
66.60
33.30
1
1
1
1
133.33
66.60
33.30
Frequency is selected by hardware select, latched inputs
Frequency is selected by Bit 2,7:4
Normal
Spread spectrum enable
Watch dog safe frequency will be selected by latch inputs
Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Spread %
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
+/-0.25% Center spread
0 to -0.5% Down spread
0 to -0.5% Down spread
0 to -0.5% Down spread
0 to -0.5% Down spread
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0466B—03/17/04
6
Note 1
0
0
0
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
45,44
38,37
41,40
-
PWD
1
1
1
X
X
X
X
X
Description
CPUT/C2
CPUT/C1
CPUT/C0
FS4 Read
FS3 Read
FS2 Read
FS1 Read
FS0 Read
b a ck
b a ck
b a ck
b a ck
b a ck
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
17
16
15
14
12
11
10
PWD
1
1
1
1
1
1
1
1
Description
Reserved
PCICLK_9
PCICLK_8
PCICLK_7
PCICLK_6
PCICLK_5
PCICLK_4
PCICLK_3
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
23
22
8
7
6
PWD
1
1
1
0
0
1
1
1
Description
24_48MHz
48MHz
Reset gear shift detect 1 = Enable, 0 = Disable
0 = Sel 48_24# by hardware;1 = I2C
Sel 48_24#, 0 = 24MHz, 1 = 48MHz
PCICLK_2
PCICLK_1
PCICLK_0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
31
30
48
1
27
28
PWD
X
X
1
1
1
1
1
1
Description
MultiSEL0 (read back)
MultiSEL1 (Read back)
3V66_0
3V66_1
REF0
REF1
3V66_48MHz
3V66_2
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0466B—03/17/04
7
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
X
X
X
X
X
X
X
X
PWD
X
X
1
1
0
1
1
0
Description
Sel 48_24# (Read back)
Sel 66_48# (Read back)
(Reserved)
(Reserved)
0 = Sel 66_48# by hardware; 1 = by I2C
Sel 66_48#, 0 = 48MHz, 1 = 66MHz
Async. frequency control bit 1
Async. frequency control bit 0
Asynchronous Frequency Control Table
Byte 5
Bit 1
0
0
1
1
Byte 5
Bit 0
0
1
0
1
3V66 [3:0]
PCI [9:0]
66.01 MHz
75.44 MHz
66.66 MHz
88.01 MHz
33.005 MHZ
37.72 MHz
33.33 MHz
44.005 MHz
Note
From Fix PLL (No spread)
From Fix PLL (No spread)
From main PLL (Default)
From Fix PLL (No spread)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
0
0
1
Device ID values will be based on individual device
0
"28H" in this case.
1
0
0
0
0466B—03/17/04
8
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
0
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
1
8 • 290ms = 2.3 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bit 7
Program
Enable
0
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
SF3
SF2
SF1
SF0
0
0
1
1
1
1
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
0466B—03/17/04
9
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
X
VCO frequency, spreading profile, spreading amount and spread
X
frequency. It is recommended to use ICS software for spread
X
programming. Default power on is latched FS divider.
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUDIV3
CPUDIV2
CPUDIV1
CPUDIV0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
X
X
X
X
X
X
X
X
Description
CPU2 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU(1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
0466B—03/17/04
10
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
PWD
X
X
X
X
X
X
X
X
Description
3V66(3:2) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
3V66(1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 17: Output Divider Control Register
B it
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
N ame
3V66(3:2)_INV
3V66(1:0)_INV
C PU_INV
C PU_INV
PWD
D escription
X
3V66(3:2) Phase Inversi on bi t
X
3V66(1:0) Phase Inversi on bi t
X
C PUC LK_2 Phase Inversi on bi t
X
C PUC LK Phase Inversi on bi t
X
PCI clock divider ratio can be configured via these 4 bits
X
individually. For divider selection table refer to Table 2.
X
Default at power up is latched FS divider.
X
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
Table 1
Div (3:2)
Div (1:0)
Table 2
00
01
10
11
Div (3:2)
Div (1:0)
00
01
10
11
00
/2
/4
/8
/16
00
/4
/8
/16
/32
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/9
/18
/36
/72
Byte 18: Group Skew Control Register
Bit
Name
PWD
Bi t 7
CPU_Skew 1
0
Bi t 6
Bi t 5
Bi t 4
Bi t 3
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
1
0
0
0
Bi t 2
Bi t 1
Bi t 0
CPU_Skew 0
Reserved
Reserved
1
0
0
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
0466B—03/17/04
11
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 19: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PWD
0
1
0
0
0
1
These 4bits control
CPU-3V66(3:2)
These 4 bits control
CPU-3V66(1:0)
0
0
Programming Sequence
0
0
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0ps
150ps
300ps
450ps
600ps
750ps
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1 1 1 1 900ps Reserved
Reserved
Reserved
Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PWD
1
0
0
0
1
0
These 4bits control
CPU-PCI(9:0)
Resreved
0
0
Programming Sequence
0
0
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0ps
150ps
300ps
450ps
600ps
750ps
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1 1 1 1 900ps Reserved
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCICLK_2_Slew 1
PCICLK_2_Slew 1
PCICLK (1:0)_Slew 0
PCICLK (1:0)_Slew 0
3V66 (3:2)_Slew 1
3V66 (3:2)_Slew 1
3V66 (1:0)_Slew 1
3V66 (1:0)_Slew 0
PWD
1
0
1
0
1
0
1
0
Description
PCICLK2 clock slew rate control bits.
01 = strong:11 = normal; 10 = weak
PCICLK(1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (2:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF Slew 1
REF Slew 0
PCI (9:7) Slew 1
PCI (9:7) Slew 0
PCI (6:5) Slew 1
PCI (6:5) Slew 0
PCI (4:3) Slew 1
PCI (4:3) Slew 0
PWD
1
0
1
0
1
0
1
0
Description
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (9:7)) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:5) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (4:3) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0466B—03/17/04
12
ICS950218
Integrated
Circuit
Systems, Inc.
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
Reserved
Reserved
Reserved
48MHz Slew 1
48MHz Slew 0
24_48MHz Slew 1
24_48MHz Slew 0
PWD
Description
X
X
Reserved
1
0
1
48MHz clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
0
1
24_48MHz clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
VIH
Input High Voltage
VIL
Input Low Voltage
VIN = VDD
IIH
Input High Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
VIN = 0 V; Inputs with pull-up resistors
IIL2
CL = 0pF; Select @ 66 MHz
IDD3.3OP1
Operating Supply
IDD3.3OP2
CL = Full load; Select @ 100 MHz
Current
IDD3.3OP3
CL =Full load; Select @ 133 MHz
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
Ttrans
Ts
TSTAB
tPZH,tPZL
tPHZ,tPLZ
IREF=5 mA
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
1
To 1st crossing of target frequency
Transition time
1
From 1st crossing to 1% target frequency
Settling time
1
Clk Stabilization
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
1
Delay
Output disable delay (all outputs)
1
Guaranteed by design, not 100% tested in production.
1
Input Capacitance
MIN
2
VSS - 0.3
-5
-5
-200
0466B—03/17/04
13
27
TYP
90
230
233
100
360
360
38.1
14.32
45
36
1
1
1
MAX
UNITS
VDD + 0.3
V
0.8
V
5
µΑ
7
5
6
45
3
3
3
10
10
mA
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
ICS950218
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
1
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
770
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
5
150
756
-7
350
1150
-300
250
550
mV
1
1
1
12
140
mV
1
300
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
-300
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
332
344
30
30
700
700
125
125
1
mV
Measurement from differential
45
49
55
%
wavefrom
VT = 50%
tsk3
8
100
ps
Skew
Measurement from differential
tjcyc-cyc
Jitter, Cycle to cycle
60
150
ps
wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Duty Cycle
dt3
0466B—03/17/04
14
1
1
1
ICS950218
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Frequency
FO1
66.66
MHz
1
Output Impedance
RDSP1 VO = VDD*(0.5)
12
33
55
Ω
1
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
IOL = 1 mA
0.55
V
Output Low Voltage
VOL
VOH = 1.0 V
-33
Output High Current
IOH1
VOH = 3.135 V
-33
mA
V
=
1.95
V
30
OL
Output Low Current
IOL1
VOL = 0.4 V
38
mA
1
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Rise Time
tr1
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
Duty Cycle
%
VT = 1.5 V
45
55
dt1
Skew
Jitter
1
tsk11
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V 3V66
250
250
ps
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK Mode
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
RDSP11
VOH1
VOL1
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V
OH = 1.0 V
Output High Current
IOH1
VOH = 3.135 V
VOL = 1.95 V
Output Low Current
IOL1
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr11
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf11
VT = 1.5 V
Duty Cycle
dt11
1
VT = 1.5 V
Skew
tsk1
1
VT = 1.5 V
Jitter,cycle to cyc
tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
0466B—03/17/04
15
MIN
TYP
MAX
0.55
UNITS
MHz
Ω
V
V
12
2.4
33
55
-33
mA
38
0.5to 2
0.5 to 2
55
500
500
mA
ns
ns
%
ps
ps
-33
30
0.5
0.5
45
ICS950218
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Frequency
FO1
1
20
Output Impedance
RDSP1 VO = VDD*(0.5)
1
IOH = -1 mA
2.4
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
VOH = 1.0 V
-29
1
Output High Current
IOH
VOH = 3.135 V
VOL = 1.95 V
27
1
Output Low Current
IOL
VOL = 0.4 V
1
VOL = 0.4 V, VOH = 2.4 V
0.5
48DOT Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
0.5
48DOT Fall Time
tf1
1
VOL = 0.4 V, VOH = 2.4 V
1
VCH 48 USB Rise Time tr1
1
VOH = 2.4 V, VOL = 0.4 V
1
VCH 48 USB Fall Time
tf1
1
48 DOT Duty Cycle
VT = 1.5 V
45
dt1
1
VCH 48 USB Duty Cycle dt1
1
48 DOT Jitter
tjcyc-cyc
1
tjcyc-cyc
VCH Jitter
1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
TYP
48
48
45
MAX
0.4
UNITS
MHz
Ω
V
V
-23
mA
29
1
1
2
2
55
mA
ns
ns
ns
ns
%
55
350
350
%
ps
ps
60
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
Output Impedance
RDSP11
VO = VDD*(0.5)
Output High Voltage
VOH1
IOH = -1 mA
1
Output Low Voltage
VOL
IOL = 1 mA
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
Output High Current
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
Output Low Current
IOL
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
VT = 1.5 V
dt1
tjcyc-cyc1
VT = 1.5 V
Jitter
1
Guaranteed by design, not 100% tested in production.
0466B—03/17/04
16
MIN
TYP
20
2.4
48
-29
29
1
1
45
MAX
UNITS
MHz
60
Ω
V
0.4
V
-23
mA
27
mA
2
ns
2
ns
%
55
1000
ps
ICS950218
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
0466B—03/17/04
17
ICS950218
Integrated
Circuit
Systems, Inc.
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66
Tpci
PCICLK_F and PCICLK
Group Skews at Common Transition Edges
GROUP
3V66
SYMBOL
3V66
CONDITIONS
3V66 (5:0) pin to pin skew
PCI_F (2:0) and
PCI
PCI
PCI (6:0) pin to pin skew
S3V66-PCI
3V66 (5:0) leads 33MHz PCI
3V66 to PCI
1
Guaranteed by design, not 100% tested in production.
0466B—03/17/04
18
MIN
0
TYP
MAX
250
UNITS
ps
0
500
ps
1.5
3.5
ns
ICS950218
Integrated
Circuit
Systems, Inc.
c
N
SYMBOL
L
E1
INDEX
AREA
A
A1
b
c
D
E
E1
e
h
L
N
α
E
1 2
h x 45°
D
A
A1
-Ce
N
SEATING
PLANE
b
48
.10 (.004) C
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950218yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0466B—03/17/04
19
MAX
.630
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