Gennum GS9035CCPJ Genlinx ii -tm gs9035c serial digital reclocker Datasheet

*(1/,1; ™,, GS9035C
Serial Digital Reclocker
DATA SHEET
DESCRIPTION
• adjustment-free operation
The GS9035C is a high performance clock and data
recovery IC designed for serial digital data. The GS9035C
receives either single-ended or differential PECL data and
outputs differential PECL clock and retimed data signals.
• auto-rate selection for 4 SMPTE data rates: 143, 177,
270, 360Mb/s
• data rate indication output
The GS9035C can operate in either auto or manual rate
selection mode. In auto mode the GS9035C is ideal for
multi-rate serial data protocols such as SMPTE 259M. In this
mode the GS9035C automatically detects and locks onto
the incoming data signal. For single rate data systems, the
GS9035C can be configured to operate in manual mode. In
both modes, the GS9035C requires only one external
resistor to set the VCO centre frequency and provides
adjustment-free operation.
• serial data output mute when PLL is not locked
• operation independent of SAV/EAV sync signals
• low jitter, low power
• single external VCO resistor for operation with four
input data rates
• large input jitter tolerance: typically 0.50 UI beyond
loop bandwidth at 270Mb/s
• power savings mode (output serial clock disable)
• system friendly: serial clock remains active when data
outputs muted
The GS9035C has dedicated pins to indicate LOCK and
data rate. In addition, an internal muting function forces the
serial data outputs to a static state when input data is not
present or when the PLL is not locked. The serial clock
outputs can also be disabled resulting in a 10% power
savings.
• robust lock detect
APPLICATIONS
The GS9035C is used for Clock and Data recovery, and
Jitter elimination for all high speed serial digital interface
applications involving SMPTE 259M and other data
standards.
The GS9035C is packaged in a 28 pin PLCC and operates
from a single +5 or -5 volt power supply.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS9035CCPJ
28 pin PLCC
0°C to 70°C
GS9035CCTJ
28 pin PLCC Tape
0°C to 70°C
COSC
LOCK
CARRIER DETECT
PHASELOCK
LOGIC
HARMONIC
SDO
FREQUENCY
ACQUISITION
SDO
2
DDI/DDI
CLK_EN
PHASE
DETECTOR
SCO
SCO
2 BIT
COUNTER
DIVISION
SMPTE
AUTO/MAN
CHARGE
PUMP
LF+ LFS LF-
VCO
CBG
DECODER
SSO
SS1
RVCO
BLOCK DIAGRAM
Revision Date: June 2003
Document No. 20582 - 3
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS9035C
FEATURES
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (VS)
5.5V
Input Voltage Range (any input)
VCC + 0.5 to VEE - 0.5V
0°C ≤ TA ≤ 70°C
Operating Temperature Range
Lead Temperature (soldering, 10 sec)
GS9035C
-65°C ≤ TS ≤ 150°C
Storage Temperature Range
260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0°C to 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF.
PARAMETER
CONDITION
MIN
TYPICAL
4.75
CLK_EN = 0
CLK_EN = 1
UNITS
5.00
5.25
V
3
-
90
110
mA
3
-
105
120
mA
3
VEE + (VDIFF/2)
0.4 to 4.6
VCC - (VDIFF/2)
V
200
800
2000
mV
3
High
2.0
-
-
V
3
Low
-
-
0.8
High
2.5
-
-
V
3
Low
-
-
0.8
-
0.25
0.4
V
4.4
4.8
-
V
1
-
0.3
0.4
HIGH, Manual Mode
2
-
-
V
3
LOW, ManualMode
-
-
0.8
Low, VIL = 0V
-
26
55
µA
1
DDI/DDI Common Mode Input
Voltage Range
DDI/DDI Differential Input
Drive
AUTO/MAN, SMPTE
CLK_EN Input Voltage
LOCK Output Low Voltage
ΙOH =
SS[1:0] Output Voltage
HIGH, ΙOH = -180µA,
Auto Mode
500µA
LOW, ΙOL = 600µA,
NOTES
TEST
LEVEL
MAX
Supply Voltage
Supply Current
1
2
3
3
1
Auto Mode
SS[1:0] Input Voltage
CLK_EN Source Current
NOTES
1. TYPICAL - measured on EB-RD35A board.
2. VDIFF is the differential input signal swing.
3. LOCK is an open collector output and requires an
external pull-up resistor.
4. Pins SS[1:0] are outputs in AUTO mode and inputs in
MANUAL mode.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4.
5.
6.
7.
8.
QA sample test.
Calculated result based on Level 1,2, or 3.
Not tested. Guaranteed by design simulations.
Not tested. Based on characterization of nominal parts.
Not tested. Based on existing design/characterization data of similar
product.
9. Indirect Test.
10.Production test at room temperature.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0°C to 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER
CONDITION
MIN
TYPICAL
143
1
MAX
UNITS
-
360
Mb/s
NOTES
TEST
LEVEL
SDI
3
Intrinsic Jitter
270Mb/s
-
185
See Figure 4
ps p-p
2
4
Intrinsic Jitter
(Pathological SDI checkfield)
270Mb/s
-
462
See Figure 5
ps p-p
2
3
360Mb/s
-
308
Input Jitter Tolerance
270Mb/s
0.40
0.50
-
UI
3
9
360Mb/s
0.38
-
-
UI
3
1
tSWITCH < 0.5µs, 270Mb/s
-
1
-
µs
1,4
8
0.5µs < tSWITCH < 10ms
-
1
-
ms
tSWITCH > 10ms
-
4
-
ms
Loop Bandwidth = 4.5MHz at
360Mb/s
-
10
-
ms
1,5
8
SDO MUTE Time
0.5
1
2
µs
6
8
SDO to SCO Synchronization
-200
0
200
ps
8
Psuedorandom (223 - 1)
Lock Time Synchronous Switch
Lock Time Asynchronous Switch
SDO, SCO Output Signal Swing
75Ω DC load
600
800
1000
mV p-p
1
SDO, SCO Rise and Fall Times
20% - 80%
200
300
400
ps
8
NOTES
1. TYPICAL - measured on EB-RD35A board, TA = 25°C.
2. Characterized 6 sigma rms.
3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz).
4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10
switching for component NTSC).
5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate.
6. SDO MUTE Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed.
TEST LEVEL
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test
10.Production test at room temperature.
TEKTRONIX
GIGABERT 1400
CLK
DATA
DI
GENNUM
TEST BOARD
TEKTRONIX
CSA803
CH-1 TRIG
SDO
DI
PATTERN 223-1
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GS9035C
Serial Data Rate
Fig. 1 Jitter Measurement Test Setup
COSC
VEE
CLK_EN
VEE
3
2
1
28
27
VCC3
LOCK
4
26
DDI
5
25
SDO
DDI
6
24
SDO
VEE
7
23
SCO
22
SCO
GS9035C
TOP VIEW
10
20
SS1
19
RSV1
11
12
13
14
15
16
17
18
VCC2
VEE
CBG
SSO
RVCO
21
RVCO_RTN
9
LF-
VCC1
LFS
8
LF+
VEE
AUTO/MAN
GS9035C
SMPTE
PIN CONNECTIONS
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1,7,8,11,27
VEE
I
Most negative power supply connection.
2
COSC
I
Timing control capacitor for internal system clock.
3
LOCK
O
Lock indication. When HIGH, the GS9035C is locked. LOCK is an open collector output and
requires an external 10k pullup resistor.
4
SMPTE
I
SMPTE/Other rate select.
5, 6
DDI/DDI
I
Digital data input (Differential ECL/PECL).
9
VCC1
I
Most positive power supply connection.
10
AUTO/MAN
I
Auto or Manual mode select. TTL/CMOS compatible input.
12
LF+
I
Loop filter component connection.
13
LFS
I
Loop filter component connection.
14
LF-
I
Loop filter component connection.
15
RVCO_RTN
I
RVCO return.
16
RVCO
I
Frequency setting resistor.
17
CBG
I
Internal bandgap voltage filter capacitor.
18
VCC2
I
Most positive power supply connection.
19
RSV1
I
Reserved Input. Always connect to GND
20 - 21
SS[1:0]
I/O
Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In
auto mode these pins can be left unconnected.
22, 23
SCO/SCO
O
Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω
pullup resistors.
24, 25
SDO/SDO
O
Serial data output. SDO/SDO are differential current mode outputs and require external 75Ω pullup
resistors.
26
VCC3
I
Most positive power supply connection.
28
CLK_EN
I
Clock enable. When HIGH, the serial clock outputs are enabled.
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TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25°C unless otherwise shown.)
1000
Max
GS9035C
JITTER (ps p-p)
800
600
Typical
Min
400
200
Typical Range, Characterized
0
100
200
300
400
SDI DATA RATE (Mb/s)
TA = 0 to 70˚C, VCC = 4.75 to 5.25V for the typical range
23
Fig. 2 Intrinsic Jitter (2 -1 Pattern) 143Mb/s
Fig. 5 Intrinsic Jitter - Pathological SDI Checkfield
0.6
0.5
IJT (UI)
0.4
0.3
0.2
0.1
0
100
200
300
400
DATA RATE (Mb/s)
TA = 0 to 70˚C, VCC = 4.75 to 5.25V
23
Fig. 3 Intrinsic Jitter (2 -1 Pattern) 270Mb/s
Fig. 6 Typical Input Jitter Tolerance (Characterized)
0.600
1000
143Mb/s
0.550
800
177Mb/s
0.500
360Mb/s
IJT (UI)
JITTER (ps)
270Mb/s
0.450
600
Typical Range, Characterized
400
200
0.400
0.350
Max
0.300
Typical
Min
0.250
0.200
0
100
200
300
400
0
10
20
30
40
50
60
70
TEMPERATURE (C˚)
SDI DATA RATE (Mb/s)
TA=0 to 70˚C, VCC=4.75 to 5.25V for the typical range
Fig. 7 Typical IJT vs. Temperature (VCC=5.0V) (Characterized)
Fig. 4 Intrinsic Jitter - Pseudorandom (223 -1)
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DETAILED DESCRIPTION
signal data rate. A single low impedance external resistor,
RVCO, sets the VCO center frequency (see Figure 9). The
low impedance RVCO minimizes thermal noise and reduces
the PLL's sensitivity to PCB noise.
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the ƒL curve. For all other
SMPTE/SS0 combinations, the VCO center frequency
corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL).
DDI
800
700
VCO FREQUENCY (MHz)
SDO
SCO
50%
Fig. 8 Input/Output Clock Signal Timing
The GS9035C reclocker contains four main functional
blocks: the Phase Locked Loop, Auto/Manual Data Rate
Select, Frequency Acquisition, and Logic Circuit.
600
500
400
ƒH
300
200
ƒL
100
SMPTE=1
SSO=1
0
0
200
400
600
800
1000
1200 1400
1600 1800
RVCO (Ω)
1. PHASE LOCKED LOOP (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
DDI/DDI
The recommended RVCO value for auto rate SMPTE 259M
applications is 365Ω.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 360Mb/s. The divider modulus is set
by the AUTO/MAN, SMPTE, and SS[1:0] pin
(see Auto/Manual Data Rate Select section for further
details).
2
PHASE
DETECTOR
INTERNAL
PLL CLOCK
When the input data stream is removed for an excessive
period of time (see AC electrical characteristics table), the
VCO frequency can drift from the previously locked
frequency up to the maximum shown in Table 1.
DIVISION
CHARGE
PUMP
Fig. 10 VCO Frequency vs. RVCO
VCO
TABLE 1: Frequency Drift Range (when PLL loses lock)
LF+
LFS
LF-
RLF CLF1
RVCO
LOOP
FILTER
CLF2
LOSES LOCK FROM
MIN (%)
MAX(%)
143Mb/s lock
-21
21
177Mb/s lock
-12
26
270Mb/s lock
-13
28
360 Mb/s lock
-13
24
Fig. 9 Simplified Diagram of the PLL
1.1 VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 143 and 360Mb/s and has a pull range of
-13 +25% about the center frequency depending on the
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GS9035C
The GS9035C receives either a single-ended or differential
PECL serial data stream at the DDI and DDI inputs. It locks
an internal clock to the incoming data and outputs the
differential PECL retimed data signal and recovered clock
on outputs SDO/SDO and SCO/SCO respectively. The
timing between the input, output, and clock signals is
shown below.
1.2 Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function between the input phase
and output timing pulses maximizing the input jitter
tolerance of the PLL.
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design ensures that the output phase does not drift when
data transitions are sparse. This makes the GS9035C ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.
The average sweep time, tswp, is determined by the loop
filter component, CLF1, and the charge pump current, ΙCP:
tswp =
4 CLF1
3 Ι LF1
[seconds]
1.4 Loop Filter
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9035C increased immunity
to PCB board noise.
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL Design
Guidelines section. Recommended values for SMPTE 259M
applications are shown in the Typical Application Circuit
diagram.
The nominal sweep time is approximately 121µs when
CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω).
An internal system clock determines tsys (see section 7,
Logic Circuit).
3. LOGIC CIRCUIT
The GS9035C is controlled by a finite state logic circuit which
is clocked by an asynchronous system clock. That is, the
system clock is completely independent of the incoming data
rate. The system clock runs at low frequencies, relative to the
incoming data rate, and thus reduces interference to the PLL.
The period of the system clock is set by the COSC capacitor
and is
4
2. FREQUENCY ACQUISITION
tsys = 9.6 x 10 x COSC
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9035C uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control
voltage such that the VCO frequency changes from -10% to
+10% of the center frequency. Figure 11 shows a typical
sweep waveform.
tswp
tsys
VLF
[seconds]
The recommended value for tsys is 450µs (COSC = 4.7nF).
4. AUTO/MANUAL DATA RATE SELECT
The GS9035C can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN).
4.1 Auto Mode (AUTO/MAN = 1)
In auto mode, the GS9035C uses a 2-bit counter to
automatically cycle through four (SMPTE=1) or two
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[1:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
Note that for SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[1:0].
A
Tcycle
Tcycle = tswp + tsys
Fig. 11 Typical Sweep Form
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GS9035C
1.3 Charge Pump
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 2-bit counter.
TABLE 2: Data Rate Indication in Auto Mode
AUTO/MAN = 1 (Auto Mode)
ƒH, ƒL = VCO center frequency as per Figure 10
SMPTE
SS[1:0]
DIVIDER
MODULI
PLL CLOCK
1
00
4
ƒH/4
01
2
ƒL/2
10
2
ƒH/2
1
11
1
ƒL
0
00
4
ƒH/4
0
01
4
ƒH/4
0
10
2
ƒH/2
0
11
2
ƒH/2
5.1 Lock Time
The lock time of the GS9035C depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9035C is changed from one source to another source
which is at a different data rate.
4.2 Manual Mode (AUTO/MAN = 0)
In manual mode, the GS9035C divider moduli is fixed. In
this mode, the SS[1:0] pins are inputs and set the divider
moduli according to Table 3.
TABLE 3: Data Rate Select in Manual Mode
AUTO/MAN = 0 (Manual Mode)
ƒH, ƒL = VCO center frequency as per Figure 10
When input data to the GS9035C is removed, the GS9035C
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9035C begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9035C locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:
TABLE 4: Lock Time Relative to Switching Time
SMPTE
SS[1:0]
DIVIDER
MODULI
PLL CLOCK
1
00
4
ƒH/4
1
01
2
1
10
1
SWITCHING TIME
LOCK TIME
<0.5µs
10µs
ƒL/2
0.5µs - 10ms
2tsys
2
ƒH/2
>10ms
2Tcycle + 2tsys
11
1
ƒL
0
00
4
ƒH/4
0
01
4
ƒH/4
0
10
2
ƒH/2
0
11
2
ƒH/2
5. LOCKING
The GS9035C indicates lock when three conditions are
satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to a harmonic.
The GS9035C defines the presence of input data when at
least one data transition occurs every 1µs.
In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described in section 2, Frequency Acquisition. In
manual mode, the frequency acquisition circuit may have to
sweep over an entire cycle (depending on initial conditions)
to acquire lock resulting in a maximum lock time of 2Tcycle +
2tsys. In auto tune mode, the maximum lock time is 6Tcycle +
2tsys since the frequency acquisition circuit may have to
cycle through 5 possible counter states (depending on
initial conditions) to acquire lock. The nominal value of Tcycle
for the GS9035C operating in a typical SMPTE 259M
application is approximately 1.3ms.
The GS9035C has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
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GS9035C
1
1
The GS9035C assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every tsys/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. (In a harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.)
5.2 DVB-ASI
PHASE
DETECTOR
Design Note: For DVB-ASI applications having significant
instances of few bit transitions or when only K28.5 idle bits
are transmitted, the wide-band PLL in the GS9035C may
lock at 243MHz being the first 27MHz sideband below
270MHz. When normal bit density signals are transmitted,
the PLL will correctly lock onto the proper 270MHz carrier.
Øi
+
KPD
ΙCP
2πKf
-
Øo
Ns
RLF
6. OUTPUT DATA MUTING
CLF2
GS9035C
LOOP
FILTER
CLF1
The GS9035C internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data. The output data muting timing is
shown in Figure 12.
VCO
Fig. 13 PLL Model
9.1 Transfer Function
The transfer function of the PLL is defined as Øo/Øi and can
be approximated as
NO DATA TRANSITIONS
DDI
sC LF1 R LF + 1
Øo
1
------- = ---------------------------------------------------------------- --------------------------------------------------------2
L 
L
Øi

s  C LF1 R LF – ---------- + 1 s C LF2 L + s --------- + 1
R
R
LF
LOCK
LF
Equation 1
SDO
VALID
DATA
OUTPUTS MUTED
where
VALID
DATA
N
L = -------------------DICP K ƒ
Fig. 12 Output Data Muting Timing
7. CLOCK ENABLE
N is the divider modulus
When CLK_EN is high, the GS9035C SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
set to a high Z state and float to VCC. Disabling the clock
outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
SCO/SCO outputs to VCC.
D is the data density (=0.5 for NRZ data)
ΙCP is the charge pump current in Amps
Kƒ is the VCO gain in Hz/V
This response has 1 zero (wZ) and three poles (wP1, wBW,
wP2) where
1
w Z = ----------------------C LF1 R LF
8. STRESSFUL DATA PATTERNS
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of zeros or
ones (low data transition densities for a long period of time).
The GS9035C is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
1
w P1 = --------------------------------------L
C LF1 RLF – --------R LF
R LF
w BW = --------L
1
w P2 = ----------------------C LF2 R LF
9. PLL DESIGN GUIDELINES
The performance of the GS9035C is primarily determined
by the PLL. Thus, it is important that the system designer is
familiar with the basic PLL design equations.
The bode plot for this transfer function is plotted in Figure 14.
A model of the GS9035C PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.
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The second is the zero-pole combination:
0
AMPLITUDE (dB)
s- + 1
-----wZ
sC LF1 R LF + 1
----------------------------------------------------------- = -------------------s
L
---------- + 1
s  C LF1 R LF – ----------- + 1

w P1
RLF 
GS9035C
This causes lift in the transfer function given by
w P1
1
20 LOG ---------- = 20 LOG --------------------wZ
wZ
1 – ----------w BW
WZ
WP1
WBW
WP2
To keep peaking to less than 0.05dB,
FREQUENCY
wZ < 0.0057 wBW
Fig. 14 Bode Plot for PLL Transfer Function
The 3dB bandwidth of the transfer function is approximately
w 3dB
9.3 Selection of Loop Filter Components
Based on the above analysis, select the loop filter
components for a given PLL bandwidth, ƒ3dB, as follows:
w BW
w BW
= ---------------------------------------------------------------------- ≈ -----------2 0.78
w BW ( w BW ⁄ w P2 )
1 – 2 ------------ + --------------------------------w P2
w BW
----------1–2
w P2
1. Calculate
where
ΙCP is the charge pump current and is a function of the
RVCO resistor and is obtained from Figure 15.
9.2 Transfer Function Peaking
There are two causes of peaking in the PLL transfer function
given by Equation 1.
Kƒ = 90MHz/V for VCO frequencies corresponding to
the ƒL curve.
The first is the quadratic
Kƒ = 140MHz/V for VCO frequencies corresponding to
the ƒH curve.
L
s C LF2 L + s --------- + 1
R LF
2
N is the divider modulus.
which has
1
w O = -------------------C LF2 L
(ƒL, ƒH and N can be obtained from Table 2 or Table 3).
C LF2
Q = R LF -----------L
and
2. Choose RLF = 2(3.14) ƒ3dB (0.78)L
3. Choose CLF1 = 174 L / (RLF)2
This response is critically damped for Q = 0.5.
4. Choose CLF2 = L/4(RLF)
Thus, to avoid peaking:
R LF
L=
C LF2 1
------------- < --2
L
2
2N
ΙCPKƒ
or
L
1
----------------------- --------- > 4
R LF CLF2 R LF
Therefore,
wP2 > 4 wBW
However, it is desirable to keep wP2 as low as possible to
reduce the high frequency content on the loop filter.
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350
300
250
200
150
100
50
0
0
200
400
600
800
1000
1200
1400 1600
1800
RVCO (Ω)
Fig. 15 Charge Pump Current vs. RVCO
SPICE NETLIST * GS9035C PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R2 0 1 1g
.END
GS9035C
CHARGE PUMP CURRENT (µA)
400
10. I/O DESCRIPTION
9.4 Spice Simulations
10.1 High Speed Inputs (DDI/DDI)
More detailed analysis of the GS9035C PLL can be done
using SPICE. A SPICE model of the PLL is shown below:
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
PHII
1. Input signal amplitudes are between 200 and 2000mV
G1
IN+
V1
LF
PHIO
E1
2. The common mode input voltage range is as specified
in the DC Characteristics table.
2πKƒ
IN-
Ns
RLF
1
CLF1
R2
Commonly used interface
Figures 17 and 18.
CLF2
NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist.
Fig. 16 SPICE Model of PLL
The model consists of a voltage controlled current source
(G1), the loop filter components (RLF, CLF1, and CLF2), a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.
examples
are
shown
in
Figure 18 illustrates the simplest interface to the GS9035C.
In this example, the driving device generates the PECL
level signals (800mV amplitudes) having a common mode
input range between 0.4 and 4.6V. This scheme is
recommended when the trace lengths are less than 1in. The
value of the resistors and the DC connection (VCC or
Ground), depends on the output driver circuitry of the
previous device.
V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, ΙCP. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2pKƒ/Ns).
The netlist for the model is given below. The .PARAM
statements are used to set values for ΙCP, Kƒ, N, and D. ΙCP
is determined by the RVCO resistor and is obtained from
Figure 15.
VCC or GND
DDI
GS9035C
DDI
VCC or GND
Fig. 17 Simple Interface to the GS9035C
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10.2 High Speed Outputs (SDO/SDO and SCO/SCO)
SDO/SDO and SCO/SCO are current mode outputs that
require external pullup resistors (see Figure 20). To
calculate the output sink current use the following
relationship:
Output Sink Current = Output Signal Swing / Pullup Resistor
A diode can be placed between Vcc and the pullup resis
tors to reduce the common mode voltage by approximately
0.7 volts. When the output traces are longer than 1in,
controlled impedance traces should be used. The pullup
resistors should be placed at the end of the output traces
as they terminate the trace in its characteristic impedance
(75Ω).
VCC
RSOURCE
ZO
DDI
RLOAD
RSOURCE
GS9035C
DDI
ZO
GS9035C
75Ω
75Ω
75Ω
75Ω
SDO
SDO
SCO
SCO
Fig. 18 Recommended Interface for Differential Signals
Figure 19 shows the recommended interface when the
GS9035C is driven single-endedly. In this case, the input
must be AC-coupled and a matching resistor (ZO) must be
used.
VCC
Fig. 20 High Speed Outputs with External Pullups
DDI
ZO
GS9035C
DDI
Fig. 19 Recommended Interface for Single-Ended Driver
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GS9035C
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface for differential signals is shown in Figure 18. In this
case, a parallel resistor (RLOAD) is placed near the
GS9035C inputs to terminate the controlled impedance
trace. The value of RLOAD should be twice the value of the
characteristic impedance of the trace. Both traces should
be in a symmetric arrangement and same physical
transmission line dimensions since common-mode signals
or common-mode noise is not terminated. In addition,
series resistors, RSOURCE, can be placed near the driving
chip to serve as source terminations. They should be equal
to the value of the trace impedance. Assuming 800mV
output swings at the driver, RLOAD =100Ω, RSOURCE =50Ω
and ZO = 50Ω.
TYPICAL APPLICATION CIRCUIT
The figure below shows the GS9035C connected in a
typical auto rate select SMPTE 259M application. Table 5
summarizes the relevant system parameters.
VCC
10k
DDI
27
26
VEE
VEE
28
VCC3
6
1
CLK_EN
DDI
LOCK
5
2
COSC
From
GS9024
3
SMPTE
4
VCC
VCC
4.7n
VCC
VCC
GS9035C
VCC
4 x 75
SDO 25
SDO 24
To
GS90201
7
VEE
8
VEE
VCC
9
VCC1
SSO 21
VCC
10
AUTO/MAN
SS1 20
11
VEE
CLF1
1800
15n
CBG
VCC2
13
RLF
RVCO
12
SCO 22
RVCO_RTN
LFS
LF+
GS9035C
TOP VIEW
LF-
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
Power supply decoupling
capacitors are not shown.
See application note "EB9035A"
for details on PCB artwork.
SCO 23
14
15
16
17
18
RVCO
365
(1%)
0.1µ
}
To LED
Driver
(optional)
RSV1 19
NOTE
1. The 75Ω pullup resistors on SDO/SDO and
SCO/SCO are not required when interfacing
the GS9035C to the GS9020 since the GS9020
has internal 75W resistors.
0.1µ
CLF2
3.3p
VCC
TABLE 5: System Parameters
RVCO = 365Ω, ƒH = 540MHz, ƒL = 360MHz
SMPTE
SS[1:0]
DATA RATE (Mb/s)
LOOP BANDWIDTH
1
00
143
1.2MHz
1
01
177
1.9MHz
1
10
270
3.0MHz
1
11
360
4.5MHz
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PACKAGE DIMENSIONS
12.573 MAX
12.319 MIN
1.219 x 45
1.067
SEATING
PLANE
11.582 MAX
11.430 MIN
12.573 MAX
12.319 MIN
11.582 MAX
11.430 MIN
GS9035C
1.270
MIN 0.508
10.922 MAX
9.906 MIN
3.048 MAX
2.286 MIN
4.572 MAX
4.115 MIN
All dimensions in millimetres.
28 pin PLCC (QM)
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Change TEST LEVELS from 3 to 1 for LOCK, SS[2:0] and CLK_EN
parameters in DC ELectrical Characteristic Table.
Change TEST LEVEL 10 to 3 for Supply Voltage in DC Electrical
Characteristic Table.
Change TEST LEVEL 3 to 9 for INPUT JITTER TOLERANCE in AC
Electrical Characteristic Table.
For latest product information, visit www.gennum.com
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku,
Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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