STMicroelectronics HCF4027BM1 Dual j-k master slave flip-flop Datasheet

HCF4027B
DUAL J-K MASTER SLAVE FLIP-FLOP
■
■
■
■
■
■
■
■
■
SET RESET CAPABILITY
STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINETELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW"
MEDIUM-SPEED OPERATION - 16MHz
(Typ. clock toggle rate at 10V)
QUIESCENT CURRENT SPECIFIED UP TO
20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4027B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4027B is a single monolithic chip integrated
circuit
containing
two
identical
complementary-symmetry
J-K
master-slave
flip-flops. Each flip-flop has provisions for
individual J, K, Set, Reset, and Clock input
DIP
SOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
HCF4027BEY
HCF4027BM1
HCF4027M013TR
signals. Buffered Q and Q signals are provided as
outputs. This input-output arrangement provides
for compatible operation with the HCF4013B dual
D type flip-flop.
This device is useful in performing control,
register, and toggle functions. Logic levels present
at the J and K inputs, along with internal
self-steering, control the state of each flip-flop;
changes in the flip-flop state are synchronous with
the positive-going transition of the clock pulse. Set
and Reset functions are independent of the clock
and are initiated when a high level signal is
present at either the Set or Reset input.
PIN CONNECTION
September 2002
1/9
HCF4027B
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
6, 5
10,11
8
J2, K2
J1, K1
CLOCK1,
CLOCK2
RESET1,
RESET2
SET1, SET2
Q2, Q2
Q1, Q1
VSS
16
VDD
13, 3
12, 4
9, 7
1, 2
15, 14
NAME AND FUNCTION
Inputs
inputs
Clock Inputs
Reset Inputs
Set Inputs
Outputs
Outputs
Negative Supply Voltage
Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
PRESENT STATE
Inputs
Output
CLOCK*
Outputs
J
K
S
R
Q
Q
Q
H
X
L
L
L
H
L
X
L
L
L
H
H
L
L
X
L
L
L
L
H
X
H
L
L
H
L
H
X
X
L
L
X
X
X
X
X
X
X
H
L
H
L
H
H
X
X
X
H
L
H
L
H
H
X : Don"t Care
* : Level Change
2/9
NEXT STATE
NO CHANGE
X
X
X
HCF4027B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
mA
V
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
3/9
HCF4027B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
CI
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
18
TA = 25°C
Min.
Typ.
Max.
0.02
0.02
0.02
0.04
1
2
4
20
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
30
60
120
600
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
±0.1
5
7.5
0.05
0.05
0.05
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
4/9
V
V
1.5
3
4
±1
µA
V
3.5
7
11
-1.15
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
Max.
30
60
120
600
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
Unit
V
mA
mA
±1
µA
pF
HCF4027B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time(Clock to Q or Q
Outputs)
tPLH
tPHL
Propagation Delay Time
(Set to Q or Reset to Q)
Propagation Delay Time
(Set to Q or Reset to Q)
tTLH tTHL Transition Time
tW
tW
tr, tf
tsetup
fMAX
Pulse Width (Clock)
Pulse Width (Set or Reset)
Clock input Rise or Fall
Time
Setup Time (DATA)
Maximum Clock Input
Frequency (1)
(toggle mode)
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Value (*)
Unit
Min.
Typ.
Max.
300
130
90
300
130
90
400
170
120
200
100
80
140
60
40
180
80
50
150
65
45
150
65
45
200
85
60
100
50
40
70
30
20
90
40
25
100
35
25
7
16
24
ns
ns
ns
ns
ns
15
4
1
200
75
50
3.5
8
12
ns
µs
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) Input tr, tf = 5ns
5/9
HCF4027B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD
TIME (J or K to CK) (f=1MHz; 50% duty cycle)
6/9
HCF4027B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
7/9
HCF4027B
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45˚ (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 ˚ (max.)
PO13H
8/9
HCF4027B
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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