ON NBSG86ABAR2 2.5v/3.3v sige differential smart gate with output level select Datasheet

NBSG86A
2.5V/3.3VSiGe Differential
Smart Gate with Output
Level Select
The NBSG86A is a multi−function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm™ family of high
performance Silicon Germanium products. The device is housed in a
low profile 4x4 mm, 16−pin, flip−chip BGA or a 3x3 mm 16 pin QFN
package.
Differential inputs incorporate internal 50 W termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak−to−peak output amplitude between 0 and 800 mV
in five discrete steps.
The NBSG86A employs input default circuitry so that under open
input conditions (Dx, Dx, VTDx, VTDx, VTSEL) the outputs of the
device will remain stable.
•
SG
86A
LYW
FCBGA−16
BA SUFFIX
CASE 489
ÇÇ
ÇÇ
16
1
QFN−16
MN SUFFIX
CASE 485G
• Maximum Input Clock Frequency > 8 GHz Typical
•
MARKING
DIAGRAM*
1
Features
•
•
•
•
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SG
86A
ALYWG
G
Maximum Input Data Rate > 8 Gb/s Typical
165 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Selectable Swing PECL Output with Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV,
600 mV, or 800 mV Peak−to−Peak Output)
50 W Internal Input Termination Resistors
•
• Pb−Free Packages are Available
July, 2006 − Rev. 10
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
*Output Level Select
© Semiconductor Components Industries, LLC, 2006
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
1
Publication Order Number:
NBSG86A/D
NBSG86A
1
A
B
2
3
4
VTD1
D1
D1
VTD1
SEL
VTSEL
VTD0 D0
16
VCC
OLS
1
SEL
2
15
D0
VTD0
14
13
Exposed Pad
(EP)
12
VEE
11
Q
Q
NBSG86A
C
SEL
OLS
VEE
Q
D
VTD0
D0
D0
VTD0
SEL
3
10
Q
VTSEL
4
9
VCC
Figure 1. BGA−16 Pinout (Top View)
5
6
VTD1
D1
7
8
D1 VTD1
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
C2
1
OLS
(Note 3)
Input
C1
2
SEL
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Select Logic Input.
B1
3
SEL
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Select Logic Input.
B2
4
VTSEL
−
Common Internal 50 W Termination Pin for SEL/SEL. See Table 7. (Note 1)
A1
5
VTD1
−
Internal 50 W termination pin. See Table 7. (Note 1)
A2
6
D1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 1. Internal 75 kW to VEE.
A3
7
D1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 1. Internal 75 kW to VEE and 36.5 kW to VCC.
A4
8
VTD1
−
Internal 50 W Termination Pin. See Table 7. (Note 1)
B3
9
VCC
−
Positive Supply Voltage (Note 2)
B4
10
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V.
C4
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V
C3
12
VEE
−
Negative Supply Voltage (Note 2)
D4
13
VTD0
−
Internal 50 W Termination Pin. See Table 7. (Note 1)
D3
14
D0
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 0. Internal 75 kW to VEE and 36.5 kW to VCC.
D2
15
D0
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 0. Internal 75 kW to VEE.
D1
16
VTD0
−
Internal 50 W Termination Pin. See Table 7. (Note 1)
N/A
−
EP
−
Exposed Pad. The thermally exposed pad on package bottom (see case drawing)
must be attached to a heat−sinking conduit.
Description
Input Pin for the Output Level Select (OLS). See Table 2.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self−oscillation.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE.
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NBSG86A
Table 2. OUTPUT LEVEL SELECT OLS
Q/Q VPP
OLS Sensitivity
VCC
OLS
800 mV
OLS − 75 mV
VCC − 0.4 V
200 mV
OLS $ 150 mV
VCC − 0.8 V
600 mV
OLS $ 100 mV
VCC − 1.2 V
0
OLS $ 75 mV
VEE (Note 4)
400 mV
OLS $ 100 mV
Float
600 mV
N/A
4. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2.0 kW resistor should be
connected from OLS to VEE.
50 W
VTD0
D0
R1
R2
D0
R1
VTD0
50 W
Q
50 W
Q
VTD1
D1
R1
R2
D1
50 W
R1
VTD1
50 W
50 W
VTSEL
SEL
SEL
Figure 3. Logic Diagram
50 W
VTD0
VT or
VBB
Table 3. AND/NAND TRUTH TABLE (Note 5)
D0
VCC
VTD0
b
*b
D0
D1
SEL
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
D0
50 W
Q
50 W
Q
VTD1
D1
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise.
D1
VTD1
50 W
50 W
50 W
VEE
VCC
VTSEL
SEL
b
SEL
Figure 4. Configuration for AND/NAND Function
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NBSG86A
50 W
VTD0
D0
Table 4. OR/NOR TRUTH TABLE**
D0
b
or b
D0
D1
SEL
Q
0
1
0
0
VTD1
0
1
1
1
VCC
D1
1
1
0
1
VT or VBB
D1
1
1
1
1
VTD0
50 W
Q
50 W
Q
50 W
VTD1
50 W
50 W
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
VTSEL
b
SEL
SEL
Figure 5. Configuration for OR/NOR Function
50 W
VTD0
D0
Table 5. XOR/XNOR TRUTH TABLE**
D0
VTD0
50 W
Q
50 W
Q
D1
SEL
Q
0
1
0
0
D1
0
1
1
1
D1
1
0
0
1
1
0
1
0
50 W
50 W
XOR b
D0
VTD1
VTD1
b
50 W
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
VTSEL
b
SEL
SEL
Figure 6. Configuration for XOR/XNOR Function
50 W
VTD0
D0
D0
Table 6. 2:1 MUX TRUTH TABLE**
VTD0
50 W
Q
SEL
50 W
Q
1
D1
0
D0
VTD1
D1
Q
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
D1
VTD1
50 W
50 W
50 W
VTSEL
SEL
SEL
Figure 7. Configuration for 2:1 MUX Function
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NBSG86A
Table 7. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to VCC
LVDS
Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open.
AC−COUPLED
Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
Table 8. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistors
(R1)
75 kW
Internal Input Pullup Resistor
(R2)
37.5 kW
Human Body Model
Machine Model
Charged Device Model
> 1 KV
> 50 V
> 4 KV
16−FCBGA
16−QFN
Level 3
Level 1
ESD Protection
Moisture Sensitivity (Note 6)
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
364
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS (Note 7)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage |Dn − Dn|
VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC − VEE|
V
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
45
80
mA
mA
Iout
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
16−FCBGA
16−QFN
−40 to +70
−40 to +85
°C
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 8)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 8)
2S2P (Note 9)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
Tsol
Wave Solder
< 15 sec
< 3 sec @ 248°C
< 3 sec @ 260°C
225
265
265
°C
Pb (BGA)
Pb (QFN)
Pb−Free (QFN)
VI v VCC
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
7. Maximum Ratings are those values beyond which device damage may occur.
8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
9. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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5
NBSG86A
Table 10. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 10)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)**
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
VOH
Output HIGH Voltage (Note 11)
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
VOL
Output LOW Voltage (Note 11)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1385
1015
1585
1215
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1445
1080
1640
1275
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
VOUTPP
mV
Output Voltage Amplitude
mV
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
VIH
Input HIGH Voltage (Single−Ended)
(Note 13)
D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 14)
D, D
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
IIH
Input HIGH Current (@VIH)
D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
mA
IIL
Input LOW Current (@VIL)
D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
mA
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
11. All loading with 50 W to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
13. VIH cannot exceed VCC.
14. VIL always w VEE.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
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NBSG86A
Table 11. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 15)
−40°C
25°C
70°C(BGA)/85°C(QFN)***
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
VOH
Output HIGH Voltage (Note 16)
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
VOL
Output LOW Voltage (Note 16)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2180
1790
2390
1995
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2215
1825
2420
2030
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2240
1855
2445
2060
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
690
125
525
0
335
800
215
630
0
425
Symbol
VOUTPP
Characteristic
mV
Output Amplitude Voltage
mV
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
VIH
Input HIGH Voltage (Single−Ended)
(Note 18)
D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 19)
D, D
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
1.2
3.3
1.2
3.3
1.2
3.3
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
IIH
Input HIGH Current (@VIH)
D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
mA
IIL
Input LOW Current (@VIL)
D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
mA
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.
16. All loading with 50 W to VCC − 2.0 V.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
18. VIH cannot exceed VCC.
19. VIL always w VEE.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
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NBSG86A
Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 20)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)***
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
VOH
Output HIGH Voltage (Note 21)
−1040
−990
−940
−1010
−960
−910
−985
−935
−885
mV
VOL
Output LOW Voltage (Note 21)
−3.465 V v VEE v −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE v −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
VOUTPP
Output Voltage Amplitude
−3.465 V v VEE v −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE v −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
−1980
−1270
−1750
−1040
−1515
−1830
−1210
−1630
−990
−1425
−1680
−1120
−1510
−910
−1305
−1940
−1235
−1715
−1010
−1480
−1790
−1175
−1595
−960
−1390
−1640
−1085
−1475
−880
−1270
−1910
−1210
−1685
−985
−1450
−1760
−1150
−1565
−935
−1360
−1610
−1060
−1445
−855
−1240
−1945
−1265
−1725
−1045
−1495
−1795
−1205
−1605
−995
−1405
−1645
−1115
−1485
−915
−1285
−1905
−1230
−1690
−1010
−1460
−1755
−1170
−1570
−960
−1370
−1605
−1080
−1450
−880
−1250
−1875
−1205
−1660
−990
−1435
−1725
−1145
−1540
−940
−1345
−1575
−1055
−1420
−860
−1225
mV
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
690
125
525
0
335
800
215
630
0
425
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
VIH
Input HIGH Voltage (Single−Ended)
(Note 23)
D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 24)
D, D
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 22)
0.0
V
RTIN
Internal Input Termination Resistor
50
55
W
IIH
Input HIGH Current (@VIH)
IIL
Input LOW Current (@VIL)
VEE+1.2
45
0.0
50
55
D, D
SEL
30
5
D, D
SEL
20
5
VEE+1.2
45
0.0
VEE+1.2
50
55
45
100
50
30
5
100
50
30
5
100
50
mA
100
50
20
5
100
50
20
5
100
50
mA
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
20. Input and output parameters vary 1:1 with VCC.
21. All loading with 50 W to VCC − 2.0 V.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
23. VIH cannot exceed VCC.
24. VIL always w VEE.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
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NBSG86A
Table 13. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
25°C
Min
Typ
Min
Typ
Min
Typ
7
8
7
8
7
8
GHz
fin v 7 GHz
550
740
500
720
450
700
mV
Propagation Delay to Output Differential
D/SEL → Q
110
160
210
115
165
215
120
170
220
5
15
5
15
5
15
ps
5
20
5
20
5
20
ps
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 8) (Note 25)
VOUTPP
Output Voltage Amplitude
(OLS = VCC)
tPLH,
tPHL
tSKEW
Duty Cycle Skew (Note 26)
tSKEW
Channel Skew
tJITTER
RMS Random Clock Jitter
(See Figure 8) (Note 25)
Max
70°C
Max
Max
Unit
ps
Q → D/SEL
ps
fin v 7 GHz
Peak−to−Peak Data Dependent Jitter
fin v 7 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
0.5
1.5
0.5
12
75
1.5
0.5
12
2600
75
65
20
1.5
12
2600
75
65
20
2600
(Q, Q)
mV
ps
20
40
40
40
65
25. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
26. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. See Figure 12.
27. VINPP (max) cannot exceed VCC − VEE.
Table 14. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
Characteristic
Min
Typ
7
25°C
Max
Min
Typ
8
7
85°C
Max
Min
Typ
Max
8
7
8
GHz
470
230
720
420
540
180
700
390
mV
mV
115
165
215
120
170
220
Unit
fmax
Maximum Frequency
(See Figure 8) (Note 28)
VOUTPP
Output Voltage Amplitude
(OLS = VCC)
fin v 7 GHz
fin = 8 GHz
590
270
730
440
tPLH,
tPHL
Propagation Delay to Output Differential
D/SEL → Q
110
160
210
tSKEW
Duty Cycle Skew (Note 29)
5
15
5
15
5
15
ps
tSKEW
Channel Skew
5
20
5
20
5
20
ps
tJITTER
RMS Random Clock Jitter
(See Figure 8) (Note 31)
ps
Q → D/SEL
ps
fin v 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 32)
fin v 7 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 30)
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
0.5
0.5
12
75
(Q, Q)
tr
tf
1.5
1.5
0.5
12
2600
75
60
65
30
17
1.5
12
2600
75
60
65
30
17
2600
mV
ps
30
17
45
35
45
35
45
35
60
65
28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
29. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. See Figure 12.
30. VINPP (max) cannot exceed VCC − VEE.
31. Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
32. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data rate at 7 Gb/s.
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9
NBSG86A
9
OLS = VCC
800
700
8
7
OLS = VCC − 0.8 V,
OLS = FLOAT
600
6
500
5
*OLS = VEE
400
4
300
3
OLS = VCC − 0.4 V
200
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
900
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
0
10
INPUT FREQUENCY (GHz)
Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for 2:1 MUX Mode (VCC − VEE = 2.5 V @ 25C; Repetitive 1010 Input Data Pattern)
800
9
8
OLS = VCC
700
600
7
OLS = VCC − 0.8 V
OLS = FLOAT
6
5
500
*OLS = VEE
400
300
4
3
OLS = VCC − 0.4 V
200
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
900
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
0
10
INPUT FREQUENCY (GHz)
Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for 2:1 MUX Mode (VCC − VEE = 3.3 V @ 25C; Repetitive 1010 Input Data Pattern)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG86A
300
200
100
IOLS (mA)
0
−100
−200
−300
−400
−500
−600
−700
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
VOLS (mV)
Figure 10. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 25C)
1000
VCC − 75
VOUTPP (mV)
800
VCC − 700
VCC − 900
600
VEE + 100
400
VCC − 250
VCC − 550
200
VCC − 1125
VCC − 1275
0
VCC
VCC − 400
VCC − 800
VCC − 1200
OLS (mV)
Figure 11. OLS Operating Area
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11
VEE
NBSG86A
D
VINPP(D) = VIH(D) − VIL(D)
VINPP(D) = VIH(D) − VIL(D)
D
Q
VOUTPP(Q) = VOH(Q) − VOL(Q)
VOUTPP(Q) = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 12. AC Reference Measurement
Q
Z = 50 W
D
Receiver
Device
Driver
Device
Q
Z = 50 W
D
50 W
50 W
V TT
V TT = V CC − 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
ORDERING INFORMATION
Package Type
Shipping†
NBSG86ABA
4x4 mm
FCBGA−16
100 Units / Tray (Contact Sales Representative)
NBSG86ABAR2
4x4 mm
FCBGA−16
100 / Tape & Reel
3x3 mm
QFN−16
123 Units / Rail
NBSG86AMNG
3x3 mm
QFN−16
(Pb−Free)
123 Units / Rail
NBSG86AMNR2
3x3 mm
QFN−16
3000 / Tape & Reel
3x3 mm
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
NBSG86AMN
NBSG86AMNR2G
Board
Description
NBSG86ABAEVB
NBSG86ABA Evaluation Board
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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12
NBSG86A
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
M
−Y−
K
E
M
0.20
3X
e
4
3
2
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
1
A
3
B
b
16 X
C
D
S
VIEW M−M
0.15
M
Z X Y
0.08
M
Z
5
0.15 Z
A
A2
A1
16 X
4
−Z−
0.10 Z
DETAIL K
ROTATED 90 _ CLOCKWISE
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13
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.40 MAX
0.25
0.35
1.20 REF
0.30
0.50
4.00 BSC
4.00 BSC
1.00 BSC
0.50 BSC
NBSG86A
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
PIN 1
LOCATION
ÇÇ
ÇÇ
ÇÇ
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
SOLDERING FOOTPRINT*
D2
16X
0.575
0.022
e
L
5
NOTE 5
EXPOSED PAD
8
4
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
3.25
0.128
0.30
0.012
EXPOSED PAD
9
E2
16X
K
12
1
16
16X
1.50
0.059
3.25
0.128
13
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
0.50
0.02
NOTE 3
0.30
0.012
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NBSG86A/D
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