Intersil EL5455IS-T13 270mhz ultra-accurate amplifier Datasheet

EL5152, EL5153, EL5252, EL5455
®
Data Sheet
May 7, 2007
FN7385.5
270MHz Ultra-Accurate Amplifiers
Features
The EL5152, EL5153, EL5252, and EL5455 are 270MHz
bandwidth -3dB voltage mode feedback amplifiers with DC
accuracy of <0.01%, 1mV offsets and 50kV/V open loop
gains. These amplifiers are ideally suited for applications
ranging from precision measurement instrumentation to
high-speed video and monitor applications demanding
higher linearity at higher frequency. Capable of operating
with as little as 3.0mA of current from a single supply ranging
from 5V to 12V dual supplies ranging from ±2.5V to ±5.0V
these amplifiers are also well suited for handheld, portable
and battery-powered equipment.
• 270MHz -3dB bandwidth
Single amplifiers are offered in SOT-23 packages and duals in
a 10 Ld MSOP package for applications where board space is
critical. Quad amplifiers are available in a 14 Ld SOIC
package. Additionally, singles and duals are available in the
industry-standard 8 Ld SOIC. All parts operate over the
industrial temperature range of -40°C to +85°C.
• Fast disable on the EL5152 and EL5252
• 180V/µs slew rate
• ±1mV maximum VOS
• Very high open loop gains 50kV/V
• Low supply current = 3mA
• 105mA output current
• Single supplies from 5V to 12V
• Dual supplies from ±2.5V to ±5V
• Low cost
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Imaging
• Instrumentation
• Video
• Communications devices
Pinouts
EL5153
(5 LD SOT-23)
TOP VIEW
EL5152
(8 LD SOIC)
TOP VIEW
NC 1
IN- 2
IN+ 3
+
8 CE
OUT 1
7 VS+
VS- 2
6 OUT
IN+ 3
4 IN-
EL5455
(14 LD SOIC)
TOP VIEW
EL5252
(10 LD MSOP)
TOP VIEW
INA+ 1
10 INA+
VS- 3
CEB 4
+ -
5 NC
VS- 4
CEA 2
5 VS+
+
-
9 OUTA
INA- 2
8 VS+
INA+ 3
7 OUTB
6 INB-
INB+ 5
OUTA 1
- +
+ -
11 VS-
INB+ 5
OUTB 7
13 IND12 IND+
VS+ 4
INB- 6
1
14 OUTD
10 INC+
- +
+ -
9 INC8 OUTC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5152, EL5153, EL5252, EL5455
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG.
DWG. #
EL5152IS
5152IS
-
8 Ld SOIC (150 mil)
MDP0027
EL5152IS-T7
5152IS
7”
8 Ld SOIC (150 mil)
MDP0027
EL5152IS-T13
5152IS
13”
8 Ld SOIC (150 mil)
MDP0027
EL5152ISZ (Note)
5152ISZ
-
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5152ISZ-T7 (Note)
5152ISZ
7”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5152ISZ-T13 (Note)
5152ISZ
13”
8 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5153IW-T7
BGAA
7” (3k pcs)
5 Ld SOT-23
MDP0038
EL5153IW-T7A
BGAA
7” (250 pcs)
5 Ld SOT-23
MDP0038
EL5153IWZ-T7 (Note)
BAAL
7” (3k pcs)
5 Ld SOT-23 (Pb-free)
MDP0038
EL5153IWZ-T7A (Note)
BAAL
7” (250 pcs)
5 Ld SOT-23 (Pb-free)
MDP0038
EL5252IY
BAGAA
-
10 Ld MSOP (3.0 mm)
MDP0043
EL5252IY-T7
BAGAA
7”
10 Ld MSOP (3.0 mm)
MDP0043
EL5252IY-T13
BAGAA
13”
10 Ld MSOP (3.0 mm)
MDP0043
EL5455IS
5455IS
-
14 Ld SOIC (150 mil)
MDP0027
EL5455IS-T7
5455IS
7”
14 Ld SOIC (150 mil)
MDP0027
EL5455IS-T13
5455IS
13”
14 Ld SOIC (150 mil)
MDP0027
EL5455ISZ (Note)
5455ISZ
-
14 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5455ISZ-T7 (Note)
5455ISZ
7”
14 Ld SOIC (150 mil) (Pb-free)
MDP0027
EL5455ISZ-T13 (Note)
5455ISZ
13”
14 Ld SOIC (150 mil) (Pb-free)
MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . 13.2V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5V to VS +0.5V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = ±5V, RF = RG = 750Ω, RL = 150Ω, TA = +25°C, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = +1, RL = 500Ω, CL = 5.0pF
270
MHz
AV = +2, RL = 150Ω
85
MHz
GBWP
Gain Bandwidth Product
RL = 150Ω
165
MHz
BW1
0.1dB Bandwidth
AV = +1, RL = 500Ω
50
MHz
SR
Slew Rate
VO = -3V to +3V, AV = +2
155
V/µs
VO = -3V to +3V, AV = 1, RL = 500Ω
180
V/µs
30
ns
120
tS
0.1% Settling Time
VOUT = -1V to +1V, AV = +2
dG
Differential Gain Error
AV = +2, RL = 150Ω
0.06
%
dP
Differential Phase Error
AV = +2, RL = 150Ω
0.045
°
VN
Input Referred Voltage Noise
12
nV/√Hz
IN
Input Referred Current Noise
1.8
pA/√Hz
DC PERFORMANCE
VOS
Offset Voltage
TCVOS
Input Offset Voltage Temperature
Coefficient
Measured from TMIN to TMAX
AVOL
Open Loop Gain
VO is from -2.5V to 2.5V (EL5152 & EL5153)
VO is from -2.5V to 2.5V (EL5252 & EL5455)
-1
0.5
1
mV
-2
µV/°C
10
20
kV/V
15
50
kV/V
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
Guaranteed by CMRR test
CMRR
Common Mode Rejection Ratio
VCM = 2.5 to -2.5
IB
-2.5
2.5
V
85
110
dB
Bias Current
-0.4
0.12
+0.6
µA
IOS
Input Offset Current
-80
12
80
nA
RIN
Input Resistance
25
60
MΩ
CIN
Input Capacitance
1
pF
OUTPUT CHARACTERISTICS
VOUT
IOUT
Output Voltage Swing
Output Current
RL = 150Ω to GND
±3.0
±3.3
V
RL = 500Ω to GND
±3.4
±3.7
V
RL = 10Ω to GND
60
105
mA
200
ns
ENABLE (SELECTED PACKAGES ONLY)
tEN
Enable Time
3
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = ±5V, RF = RG = 750Ω, RL = 150Ω, TA = +25°C, Unless Otherwise Specified. (Continued)
DESCRIPTION
CONDITIONS
tDIS
Disable Time
IIHCE
CE Pin Input High Current
CE = VS+
IILCE
CE Pin Input Low Current
CE = VS-
VIHCE
CE Input High Voltage for Power-down
VILCE
CE Input Low Voltage for Power-up
MIN
TYP
MAX
UNIT
300
5
ns
0
-1
µA
13
25
µA
VS+ -1
V
VS+ -3
V
SUPPLY
ISON
Supply Current - Enabled (per amplifier)
ISOFF
PSRR
No load, VIN = 0V, CE = +5V
2.46
3.0
3.43
mA
Supply Current - Disabled (per amplifier) No load, VIN = 0V, CE = 5V
5
13
25
µA
Power Supply Rejection Ratio
DC, VS = ±3.0V to ±6.0V (EL5152 & EL5153)
85
116
dB
DC, VS = ±3.0V to ±6.0V (EL5252 & EL5455)
80
95
dB
Typical Performance Curves
90
60
3
30
2
AV=+1
1
0
AV=+2
-1
AV=+5
-2
-3 Supply=±5.0V
-4 INPUT=-30dBm=20mV
RL=500Ω
-5 C =5pF
L
-6
100K
1M
10M
PHASE (°)
NORMALIZED GAIN (dB)
4
AV=+2
AV=+1
-30
-60
-90
-120
-150
-180
100M
AV=+5
0
Supply=±5.0V
INPUT=-30dBm=20mV
RL=500Ω
CL=5pF
-210
100K
500M
1M
FREQUENCY (Hz)
FIGURE 1. EL5152 SMALL SIGNAL FREQUENCY FOR
VARIOUS GAINS
FIGURE 2. EL5152 SMALL SIGNAL FREQUENCY PHASE
FOR VARIOUS GAINS
10Ω
CL=5pF
AV=+1
50Ω
2
500Ω
150Ω
1
0
-1
-2
-3
4
AV=+1
RL=500Ω
12pF
3
10pF
2
4.7pF
3.3pF
1
0
-1
2.2pF
-2
1pF
-3
What should label
be fore this curve?
-4
-4
-5
100K
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
500M
5
5
4
100M
10M
FREQUENCY (Hz)
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS RL
4
-5
100K
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS CL
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Typical Performance Curves
(Continued)
3
2
5
AV=+2
CL=5pF
RF=500Ω
50Ω
100Ω
200Ω
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
4
0
250Ω
500Ω
-1
-2
-3
-4
-5
4
3
AV=+2
RL=500Ω
RF=500Ω
22pF
18pF
2
12pF
1
0
-1
4.7pF
-2
2.7pF
-3
-4
-6
100K
1M
100M
10M
-5
100K
800M
1M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS RL
50Ω
1
200Ω
0
-1
500Ω
-2
250Ω
-3
-4
3
2
0
39pF
27pF
-2
-3
18pF
-4
-5
100M
50pF
-1
-6
100K
10M
68pF
1
-6
100K
1M
87pF
RL=500Ω
AV=+5
RF=102Ω
-5
1M
FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS RL
500M
5
4.7pF
RL=150Ω
AV=+2
RF=500Ω
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
100M
FIGURE 8. FREQUENCY RESPONSE FOR VARIOUS CL
5
3
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
4
500M
4
AV=+5
CL=5pF
RF=102Ω
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
2
100M
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS CL
4
3
10M
FREQUENCY (Hz)
3.3pF
2
1
3.2pF
0
1pF
-1
-2
-3
3
RL=500Ω
CL=5pF
AV=+2
RF=RG=
1500Ω
1000Ω
2
1
750Ω
0
500Ω
-1
-2
-3
-4
-4
-5
100K
4
1M
10M
100M
FREQUENCY (Hz)
FIGURE 9. FREQUENCY RESPONSE FOR
VARIOUS CIN
5
500M
-5
100K
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 10. FREQUENCY RESPONSE vs RF/RG
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Typical Performance Curves
(Continued)
-5
-3
5
RL=500Ω
AV=+5
RF=102Ω
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
-4
34pF
-2
22pF
-1
0
-1
0pF
-2
-3
4
3
2
Supply=±5.0V
RL=500Ω
AV=+2
RF=500Ω
1
-1
-2
-3
-4
-4
-5
100K
-5
100K
1M
100M 300M
10M
±2.0V
±3.0V
±4.0V
±5.0V
0
1M
FREQUENCY (Hz)
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS CIN
500M
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS POWER
SUPPLY
-30
0
AV=+1
-10
-40
-20
-50
-30
-60
CMRR (dB)
PSRR (dB)
100M
10M
FREQUENCY (Hz)
-40
-50
-60
-70
±2.5
-70
±3.0
-80
±5.0
-90
-100
-80
-110
-90
-120
-130
100
-100
1K
10K
1M
100K
10M
100M
FREQUENCY (Hz)
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. PSRR
FIGURE 14. CMRR FOR VARIOUS POWER SUPPLY VALUES
1000
OUTPUT IMPEDANCE (Ω)
AV=+1
100
AV=+1
RL=500Ω
CL=0
10
CH 1
CH 2
1
0.01
0.001
328ns
DISABLE
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 15. OUTPUT IMPEDANCE
6
216ns
ENABLE
100M
TIME (400ns/DIV)
FIGURE 16. ENABLE/DISABLE RESPONSE
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Typical Performance Curves
(Continued)
VOLTAGE (500mV/DIV)
VOLTAGE (500mV/DIV)
AV=+1
RL=500Ω
CL=5pF
0V
AV=+1
RL=500Ω
CL=5pF
0V
TIME (4ns/DIV)
TIME (4ns/DIV)
FIGURE 17. RISE TIME - LARGE SIGNAL RESPONSE
VOLTAGE (100mV/DIV)
VOLTAGE (100mV/DIV)
AV=+1
RL=500Ω
CL=5pF
FIGURE 18. FALL TIME - LARGE SIGNAL RESPONSE
0V
AV=+1
RL=500Ω
CL=5pF
0V
TIME (2ns/DIV)
TIME (2ns/DIV)
FIGURE 19. RISE TIME - SMALL SIGNAL RESPONSE
FIGURE 20. FALL TIME - SMALL SIGNAL RESPONSE
-10
-45
90
80
70
0
GAIN
45
50
40
90
30
PHASE
20
PHASE (°)
GAIN (dB)
60
135
10
-30
AV=+1
RL-500Ω
CL=0pF
-40
IN #2
OUT #1
-50
-60
IN #1
OUT #2
-70
-80
-90
0
-10
1K
CROSSTALK (dB)
-20
10K
100K
1M
10M
180
100M 500M
FREQUENCY (Hz)
FIGURE 21. EL5152 SMALL SIGNAL OPEN LOOP GAIN vs
FREQUENCY INVERTING
7
-100
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 22. EL5252 SMALL SIGNAL FREQUENCY vs
CROSSTALK
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Typical Performance Curves
(Continued)
4
6
5
4
3
AV=+2
RL=500Ω
CL=5pF
2
1
3
NORMALIZED GAIN (dB)
SUPPLY CURRENT (mA)
7
2
1
±1.5
±2
±2.5
±3
±3.5
±4
±4.5
±2.0V
±3.0V
±4.0V
±5.0V
0
-1
-2
-3
-4
-5
-6
100K
0
±1
RL=500Ω
CL=0pF
±5
1M
VOLTAGE (V)
100M
10M
800M
FREQUENCY (Hz)
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 24. FREQUENCY RESPONSE FOR VARIOUS
VOLTAGE SUPPLY LEVELS
NORMALIZED GAIN (dB)
5
4
3
AV=+1
RL-500Ω
CL=0pF
2
1
CHANNEL #1
0
CHANNEL #2
-1
-2
-3
-4
-5
100K
1M
100M
10M
1G
FREQUENCY (Hz)
FIGURE 25. EL5252 SMALL SIGNAL FREQUENCY - CHANNEL TO CHANNEL
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1
SO14
θJA=88°C/W
1.2 1.136W
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.4
SO8
θJA=110°C/W
1 909mW
0.9
0.8 870mW
MSOP8/10
θJA=115°C/W
0.6
0.4 435mW
SOT23-5/6
θJA=230°C/W
0.2
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
SO14
0.9
0.8 833mW
0.7
0.6 625mW
0.5
486mW
0.4
0.3 391mW
0.2
SOT23-5/6
0.1 θ =256°C/W
JA
0
0
25
50
θJA=120°C/W
SO8
θJA=160°C/W
MSOP8/10
θJA=206°C/W
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
EL5152 Product Description
The EL5152, EL5153, EL5252, and EL5455 are wide
bandwidth, low power, low offset voltage feedback
operational amplifiers capable of operating from a single or
dual power supplies. This family of operational amplifiers are
internally compensated for closed loop gain of +1 or greater.
Connected in voltage follower mode, driving a 500Ω load
members of this amplifier family demonstrate a -3dB
bandwidth of about 270MHz. With the loading set to
accommodate typical video application, 150Ω load and gain
set to +2, bandwidth reduces to about 180MHz with a
600V/µs slew rate. Power down pins on the EL5152 and
EL5252 reduce the already low power demands of this
amplifier family to 17µA typical while the amplifier is
disabled.
Input, Output and Supply Voltage Range
The EL5152 and EL5153 families have been designed to
operate with supply voltage ranging from 5V to 12V. Supply
voltages range from ±2.5V to ±5V for split supply operation.
Of course split supply operation can easily be achieved
using single supplies by splitting off half of the single supply
with a simple voltage divider as illustrated in the application
circuit section.
Input Common Mode Range
These amplifiers have an input common mode voltage
ranging from 1.5V above the negative supply (VS- pin) to
1.5V below the positive supply (VS+ pin). If the input signal is
driven beyond this range the output signal will exhibit
distortion.
Maximum Output Swing & Load Resistance
The outputs of the EL5152 and EL5153 families maximum
output swing ranges from -4V to 4V for VS = ±5V with a load
resistance of 500Ω. Naturally, as the load resistance
becomes lower, the output swing lowers accordingly; for
instance, if the load resistor is 150Ω, the output swing
ranges from -3.5V to 3.5V. This response is a simple
application of Ohms law indicating a lower value resistance
results in greater current demands of the amplifier.
Additionally, the load resistance affects the frequency
response of this family as well as all operational amplifiers,
as clearly indicated by the Gain vs Frequency for Various RL
curves clearly indicate. In the case of the frequency
response reduced bandwidth with decreasing load
resistance is a function of load resistance in conjunction with
the output zero response of the amplifier.
Choosing a Feedback Resistor
A feedback resistor is required to achieve unity gain; simply
short the output pin to the inverting input pin. Gains greater
than +1 require a feedback and gain resistor to set the
desired gain. This gets interesting because the feedback
resistor forms a pole with the parasitic capacitance at the
inverting input. As the feedback resistance increases the
9
position of the pole shifts in the frequency domain, the
amplifier's phase margin is reduced and the amplifier
becomes less stable. Peaking in the frequency domain and
ringing in the time domain are symptomatic of this shift in
pole location. So we want to keep the feedback resistor as
small as possible. You may want to use a large feedback
resistor for some reason; in this case to compensate the shift
of the pole and maintain stability a small capacitor in the few
Pico farad range in parallel with the feedback resistor is
recommended.
For the gains greater than unity, it has been determined a
feedback resistance ranging from 500Ω to 750Ω provides
optimal response.
Gain Bandwidth Product
The EL5156 and EL5157 families have a gain bandwidth
product of 210MHz for a gain of +5. Bandwidth can be
predicted by the following equation:
Gain × BW = GainBandwidthProduct
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and same frequency
response as DC levels are changed at the output; this
characteristic is widely referred to as “diffgain-diffphase”.
Many amplifiers have a difficult time with this especially while
driving standard video loads of 150Ω, as the output current
has a natural tendency to change with DC level. The EL5152
dG and dP for these families is a respectable 0.006% and
0.04%, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance as the current output demands placed on the
amplifier lessen with increased load.
Driving Capacitive Loads
The EL5152 and EL5153 families can easily drive capacitive
loads as demanding as 27pF in parallel with 500Ω while
holding peaking to within 5dB of peaking at unity gain. Of
course if less peaking is desired, a small series resistor
(usually between 5Ω to 50Ω) can be placed in series with the
output to eliminate most peaking. However, there will be a
small sacrifice of gain which can be recovered by simply
adjusting the value of the gain resistor.
Driving Cables
Both ends of all cables must always be properly terminated;
double termination is absolutely necessary for reflection-free
performance. Additionally, a back-termination series resistor
at the amplifier's output will isolate the amplifier from the
cable and allow extensive capacitive drive. However, other
applications may have high capacitive loads without a backtermination resistor. Again, a small series resistor at the
output can help to reduce peaking.
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Disable/Power-Down
For sinking:
The EL5152 and EL5253 can be disabled with their output
placed in a high impedance state. The turn off time is about
330ns and the turn on time is about 130ns. When disabled,
the amplifier's supply current is reduced to 17µA typically;
essentially eliminating power consumption. The amplifier's
power down is controlled by standard TTL or CMOS signal
levels at the ENABLE pin. The applied logic signal is relative
to VS- pin. Letting the ENABLE pin float or the application of
a signal that is less than 0.8V above VS- enables the
amplifier. The amplifier is disabled when the signal at
ENABLE pin is above VS+ -1.5V.
Output Drive Capability
The EL5152 and EL5153 families do not have internal short
circuit protection circuitry. Typically, short circuit currents as
high as 95mA and 70mA can be expected and naturally, if
the output is shorted indefinitely the part can easily be
damaged from overheating, or excessive current density
may eventually compromise metal integrity. Maximum
reliability is maintained if the output current is always held
below ±40mA. This limit is set and limited by the design of
the internal metal interconnect. Note that in transient
applications, the part is extremely robust.
Power Dissipation
With the high output drive capability of the EL5152 and
EL5153 families, it is possible to exceed the 125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for an application to
determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
n
∑ ( VOUTi – VS ) × ILOADi
PD MAX = V S × I SMAX +
i=1
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
N = number of amplifiers (Max = 2)
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail. See Figure 1 for a complete tuned power supply
bypass methodology.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
n
PD MAX = V S × I SMAX +
V OUTi
∑ ( VS – VOUTi ) × ---------------R Li
i=1
10
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Application Circuits
Sullen Key Low Pass Filter
Sullen Key High Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the EL5152. A derivation of the transfer function is provided
for convenience. (See Figure 28.)
Again this useful filter benefits from the characteristics of the
EL5152. The transfer function is very similar to the low pass
so only the results are presented. (See Figure 29.)
K = 1+
5V
1
V1
R2C2s + 1
Vo
V1 − Vi
Vo − Vi
K
1 + − V1 +
=0
1
R1
R2
C1s
K
H(s) =
R1C1R2C2s 2 + ((1 − K )R1C1 + R1C2 + R21C2)s + 1
1
H( jw ) =
1 − w 2R1C1R2C2 + jw ((1 − K )R1C1 + R1C2 + R2C2)
V2
Vo = K
L1
10µH
R5
C3
1K
1n
C6
1n
C1
R1
1K
V1
1n 3 U1A
R2
+
1K
Holp = K
4
1
V+
2
C2
1n
VOUT
R7
11
R1C1R2C2
1
Q=
(1 − K )
1K
C5
RB
RA
1K
1
wo =
V-
-
RB
RA
1K
R1C1
R1C2
R2C2
+
+
R2C2
R2C1
R1C1
1n
Holp = K
R6
C4
1K
1n
L3
10µH
1
wo =
RC
1
Q=
3 −K
Equations simplify if we let all
components be equal R=C
5V
V3
FIGURE 28. SULLEN KEY LOW PASS FILTER
11
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
5V
V2
L1
10µH
R5
C3
1K
1n
C6
Holp = K
1n
R8
V1
C7
C9
1n
1n
1K
3 U1A
+
R1C1R2C2
4
1
V+
2
C2
1n
R7
11
1
Q=
VOUT
R1C1
R1C2
R2C2
(1 − K )
+
+
R2C2
R2C1
R1C1
V-
-
1
wo =
1K
1K
C5
RB
RA
1K
1n
R6
1K
Holp =
C4
K
4 −K
Equations simplify if we let
all components be equal R=C
2
wo =
RC
1n
L3
10µH
Q=
2
4 −K
5V
V3
FIGURE 29. SULLEN KEY HIGH PASS FILTER
Differential Output Instrumentation Amplifier
The addition of a third amplifier to the conventional three
amplifier Instrumentation Amplifier introduces the benefits of
differential signal realization, specifically the advantage of
using common mode rejection to remove coupled noise and
ground-potential errors inherent in remote transmission. This
configuration also provides enhanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
e1
A1
+
-
R3
R3
A3
R2
+
RG
e2
+
R3
R3
R3
A4
R2
A2
R3
+
R3
e o3 = – ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
eo3
+
REF
eo
eo4
R3
e o4 = ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
e o = – 2 ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 )
2f C1, 2
BW = -----------------A Di
12
A Di = – 2 ( 1 + 2R 2 ⁄ R G )
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwidth and high accuracy of the EL5152.
The operation of the circuit is very straight forward. As the
strain variable component resistor in the balanced bridge is
subjected to increasing strain its resistance changes
resulting in an imbalance in the bridge. A voltage variation
from the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain is
converted into an output voltage.
5V
V2
L1
10µH
R5
C3
1K
1n
C6
VARIABLE SUBJECT TO STRAIN
1n
1K
V5
0V
R15
22
R16
1K
4
R17
4
1K
R18
1K
R14
1K
22
3 U1A
+
4
1
V+
2
VOUT (V1+V2+V3+V4)
V-
-
RL
11
1K
1K
1K
RF
C12
1n
R11 C11
1K
1n
L4
10µH
5V
V4
13
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
15
0.25
0° +3°
-0°
FN7385.5
May 7, 2007
EL5152, EL5153, EL5252, EL5455
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
0.08 M C A B
b
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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16
FN7385.5
May 7, 2007
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