TI1 DAC7744 16-bit, quad voltage output digital-to-analog converter Datasheet

DAC7744
®
DAC
774
4
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit, Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 200mW
● UNIPOLAR OR BIPOLAR OPERATION
● SINGLE-SUPPLY OUTPUT RANGE: +10V
● DUAL SUPPLY OUTPUT RANGE: ±10V
● SETTLING TIME: 10µs to 0.003%
● 16-BIT MONOTONICITY: –40°C to +85°C
The DAC7744 is a 16-bit, quad voltage output digitalto-analog converter with guaranteed 16-bit monotonic
performance over the specified temperature range. It
accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing simultaneous update of all
DACs), and provides a readback mode of the internal
input registers. Programmable asynchronous reset
clears all registers to a mid-scale code of 8000H or to
a zero-scale of 0000H. The DAC7744 operates from
either a single +15V supply or from a +15V, –15V,
and +5V supply.
Low power and small size per DAC make the DAC7744
ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop
servo-control. The DAC7744 is available in a 48lead SSOP package, and offers guaranteed specifications over the –40°C to +85°C temperature range.
● PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
● DATA READBACK
● DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
VDD
VSS
VREFL
AB Sense
VCC
VREFL AB VREFH AB
VREFH
AB Sense
DAC7744
16
DATA I/O
I/O
Buffer
Input
Register A
DAC
Register A
Input
Register B
DAC
Register B
DAC A
VOUTA
VOUTA Sense
DAC B
VOUTB
VOUTB Sense
A1
A0
CS
R/W
Control
Logic
Input
Register C
DAC
Register C
Input
Register D
DAC
Register D
DAC C
VOUTC
VOUTC Sense
DAC D
VOUTD
VOUTD Sense
AGND
DGND
RST
RSTSEL LOADDACs
VREFL
CD Sense
VREFL CD VREFH CD
VREFH
CD Sense
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1999 Burr-Brown Corporation
SBAS120
PDS-1534A
1
Printed in U.S.A. November, 1999
DAC7744
SPECIFICATIONS (Dual Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted.
DAC7744E
PARAMETER
CONDITIONS
ACCURACY
Linearity Error
TMIN to TMAX
Linearity Match
Differential Linearity Error
TMIN to TMAX
Monotonicity, TMIN to TMAX
Bipolar Zero Error
Bipolar Zero Error, TMIN to TMAX
Full-Scale Error
Full-Scale Error, TMIN to TMAX
Bipolar Zero Matching
Full-Scale Matching
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MAX
MIN
TYP
±3
±4
DAC7744EC
MAX
MIN
TYP
✻
✻
MAX
UNITS
±2
±3
±0.025
±0.05
±0.025
±0.05
±0.024
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
LSB
LSB
LSB
LSB
LSB
Bits
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
Channel-to-Channel
Matching
±0.024
✻
✻
% of FSR
At Full Scale
25
✻
✻
ppm/V
✻
V
mA
pF
mA
✻
✻
V
V
mA
mA
✻
µs
±4
T = 25°C
T = 25°C
Channel-to-Channel
Matching
VREFL
±5
VREFH
VREFL + 1.25
–10
–0.3
–3.2
To ±0.003%, 20V
Output Step
See Figure 5
9
0.7 • VDD
0
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
POWER SUPPLY
VDD
VCC
VSS
IDD
ICC
ISS
Power
3.6
+4.75
+14.25
–14.25
TEMPERATURE RANGE
Specified Performance
✻
✻
–40
+5.0
+15.0
–15.0
50
6
–5
170
✻
✻
✻
✻
✻
✻
11
✻
✻
✻
✻
✻
✻
✻
✻
✻
VDD
0.3 • VDD
±10
±10
4.5
0.3
✻
✻
✻
✻
0.5
2
60
f = 10kHz
✻
✻
✻
✻
+10
VREFH – 1.25
2.6
–0.3
LSB
nV-s
nV/√Hz
✻
V
V
µA
µA
✻
✻
✻
✻
✻
✻
✻
200
+85
✻
✻
✻
✻
0.4
+5.25
+15.75
–15.75
±1
±1
16
✻
✻
500
±20
Indefinite
To VSS, VDD or GND
DIGITAL INPUT
VIH
VIL
IIH
IIL
±2
±2
15
±0.01
±2
✻
±3
±3
14
T = 25°C
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
TYP
T = 25°C
Power Supply Rejection Ratio (PSRR)
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
MIN
DAC7744EB
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
✻
✻
✻
V
V
V
µA
mA
mA
mW
✻
°C
✻ Specifications same as grade to the left.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7744
2
SPECIFICATIONS (Single Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted.
DAC7744E
PARAMETER
ACCURACY
Linearity Error(1)
TMIN to TMAX
Linearity Match
Differential Linearity Error
TMIN to TMAX
Monotonicity, TMIN to TMAX
Unipolar Zero
Unipolar Zero Error, TMIN to TMAX
Full-Scale Error
Full-Scale Error, TMIN to TMAX
Unipolar Zero Matching
Full-Scale Matching
Power Supply Rejection Ratio (PSRR)
ANALOG OUTPUT
Voltage Output
Output Current
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
CONDITIONS
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MAX
MIN
TYP
±3
±4
DAC7744EC
MAX
MIN
TYP
✻
✻
MAX
UNITS
±2
±3
±0.025
±0.05
±0.025
±0.05
±0.024
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
LSB
LSB
LSB
LSB
LSB
Bits
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
Channel-to-Channel
Matching
±0.024
✻
✻
% of FSR
At Full Scale
25
✻
✻
ppm/V
✻
V
±4
T = 25°C
T = 25°C
Channel-to-Channel
Matching
VREFL = 0V, VSS = 0V
R = 10kΩ
0
VREFH
±5
To ±0.003%, 10V
Output Step
See Figure 6
POWER SUPPLY
VDD
VCC
VSS
IDD
ICC
Power
TEMPERATURE RANGE
Specified Performance
3.6
+4.75
+14.25
–40
+5.0
+15.0
0
50
3.5
50
✻
✻
✻
✻
✻
✻
V
V
mA
mA
✻
✻
µs
✻
✻
✻
✻
LSB
nV-s
nV/√Hz
✻
V
V
µA
µA
✻
✻
✻
✻
0.4
✻
✻
70
+85
✻
✻
✻
✻
✻
✻
✻
+5.25
+15.75
mA
pF
mA
✻
✻
✻
✻
✻
10
VDD
0.3 • VDD
±10
±10
4.5
0.3
✻
✻
✻
0.5
2
60
0.7 • VDD
0
✻
✻
✻
✻
+10
VREFH – 1.25
1.0
–0.3
8
f = 10kHz
✻
✻
VREFL + 1.25
0
–0.3
–1.5
±1
±1
16
✻
500
±20
Indefinite
To VSS, VCC or GND
IOH = –0.8mA
IOL = 1.6mA
±2
±2
15
±0.01
±2
✻
±3
±3
14
T = 25°C
DIGITAL INPUT
VIH
VIL
IIH
IIL
DIGITAL OUTPUT
VOH
VOL
TYP
T = 25°C
REFERENCE INPUT
Ref High Input Voltage Range
Ref Low Input Voltage Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
MIN
DAC7744EB
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
✻
✻
V
V
V
µA
mA
mW
✻
°C
✻ Specifications same as grade to the left.
NOTE: (1) If VSS = 0V, the specification applies at code 0021H and above, due to possible negative zero scale error.
®
3
DAC7744
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... –0.3V to +32V
VCC to AGND ...................................................................... –0.3V to +16V
VSS to AGND ...................................................................... +0.3V to –16V
AGND to DGND ................................................................. –0.3V to +0.3V
VREFH to AGND ..................................................................... –9V to +11V
VREFL to AGND ...................................................................... –11V to +9V
VDD to GND ........................................................................... –0.3V to +6V
VREFH to VREFL ........................................................................ –1V to 22V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
LINEARITY
ERROR
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
DAC7744E
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±4
±3
48-Lead SSOP
333
–40°C to +85°C
"
"
"
"
"
"
DAC7744EB
±4
±2
48-Lead SSOP
333
–40°C to +85°C
"
"
"
"
"
"
DAC7744EC
±3
±1
48-Lead SSOP
333
–40°C to +85°C
"
"
"
"
"
"
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC7744E
DAC7744E/1K
Rails
Tape and Reel
DAC7744EB
DAC7744EB/1K
Rails
Tape and Reel
DAC7744EC
DAC7744EC/1K
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7744E/1K” will get a single 1000-piece Tape and Reel.
ESD PROTECTION CIRCUITS
VCC
VCC
VOUT Sense
RefH
RefH Sense
VOUT
AGND
RefL Sense
RefL
VSS
VSS
4
1 of 2
1 of 4
VDD
VDD
Typ of Each
Logic Input Pin
DGND
Typ of Each
I/O Pin
DGND
®
DAC7744
4
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SSOP
PIN
NAME
DESCRIPTION
1
DB15
Data Bit 15, MSB
2
DB14
Data Bit 14
3
DB13
Data Bit 13
DB15 (MSB)
1
48
NC
4
DB12
Data Bit 12
DB14
2
47
NC
5
DB11
Data Bit 11
6
DB10
Data Bit 10
7
DB9
Data Bit 9
Data Bit 8
DB13
3
46
NC
DB12
4
45
NC
8
DB8
VOUTA Sense
9
DB7
Data Bit 7
10
DB6
Data Bit 6
DB11
5
44
DB10
6
43
VOUTA
11
DB5
Data Bit 5
DB9
7
42
VREFL AB Sense
12
DB4
Data Bit 4
13
DB3
Data Bit 3
14
DB2
Data Bit 2
VREFH AB
15
DB1
Data Bit 1
VREFH AB Sense
16
DB0
17
RSTSEL
Reset Select. Determines the action of RST. If
HIGH, a RST command will set the DAC registers to mid-scale. If LOW, a RST command will
set the DAC registers to zero.
18
RST
Reset, Edge-Triggered. Depending on the state
of RSTSEL, the DAC Input and Output registers
are set to either mid-scale or zero.
19
LOADDACs
DAC Output Registers Load Control. Rising edge
triggered.
20
R/W
Enabled by the CS, controls data read and write
from the input register.
21
A1
Enabled by the CS, in combination with A0
selects the Individual DAC Input Registers.
A0
Enabled by the CS, in combination with A1
selects the individual DAC input registers.
DB8
DB7
DB6
8
41
9
40
10
39
VREFL AB
DB5
11
38
VOUTB Sense
DB4
12
37
VOUTB
DAC7744
DB3
13
36
VOUTC Sense
DB2
14
35
VOUTC
DB1
15
34
VREFH CD Sense
DB0 (LSB)
16
33
VREFH CD
RSTSEL
17
32
VREFL CD
RST
18
31
VREFL CD Sense
LOADDACs
19
30
VOUTD Sense
22
R/W
20
29
VOUTD
23
CS
A1
21
28
VSS
24
DGND
A0
22
27
AGND
Data Bit 0, LSB
Chip Select, Active LOW.
Digital Ground
25
VDD
Positive Power Supply
26
VCC
Positive Power Supply
CS
23
26
VCC
27
AGND
DGND
24
25
VDD
28
VSS
Negative Power Supply
DAC D Voltage Output
29
VOUTD
30
VOUTD Sense
31
VREFL CD Sense
32
VREFL CD
33
VREFH CD
34
VREFH CD Sense
35
VOUTC
36
VOUTC Sense
Analog Ground
DAC D’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
DAC C and D Reference Low Sense Input
DAC C and D Reference Low Input
DAC C and D Reference High Input
DAC C and D Reference High Sense Input
DAC C Voltage Output
DAC C’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
37
VOUTB
38
VOUTB Sense
39
VREFH AB Sense
40
VREFH AB
DAC A and B Reference High Input
41
VREFL AB
DAC A and B Reference Low Input
42
VREFL AB Sense
43
VOUTA
44
VOUTA Sense
45
NC
No Connection
46
NC
No Connection
47
NC
No Connection
48
NC
No Connection
DAC B Voltage Output
DAC B’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
DAC A and B Reference High Sense Input
DAC A and B Reference Low Sense Input
DAC A Voltage Input
DAC A’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
®
5
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+25°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
+85°C
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
®
DAC7744
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
6
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+85°C
(cont.)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
–40°C
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
®
7
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
ZERO-SCALE ERROR vs TEMPERATURE
FULL-SCALE ERROR vs TEMPERATURE
2
Code (FFFFH)
Code (0021
(0040H)
DAC B
Positive Full-Scale Error (mV)
Zero-Scale Error (mV)
1.5
2
DAC D
1
0.5
0
–0.5
DAC A
DAC C
–1
–1.5
–2
0
10
20
30 40
50
60 70
80
DAC D
1
0.5
0
–0.5
DAC A
DAC C
–1
–1.5
90
–40 –30 –20 –10
0
10
20
30 40
50
60 70
VREFL
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
90
VREF Current (mA)
CURRENT vs CODE
All DACS Sent to Indicated Code
(DAC C and D)
VREFH
80
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
VREF Current (mA)
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
VREFH
VREF Current (mA)
Temperature (°C)
VREF Current (mA)
Temperature (°C)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
VREFL
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
POWER SUPPLY CURRENT vs TEMPERATURE
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
4.0
4.0
Data = FFFFH (all DACs)
No Load
No Load
3.5
ICC
3.0
3.0
2.5
2.5
ICC (mA)
Quiescent Current (mA)
DAC B
–2
–40 –30 –20 –10
3.5
1.5
2.0
1.5
2.0
1.5
1.0
1.0
0.5
IDD
0
0.5
0
–0.5
–40 –30 –20 –10
0
10
20
30 40
50
60 70
80
0
90
4000H
6000H
8000H
A000H
Digital Input Code
Temperature (°C)
®
DAC7744
2000H
8
C000H
E000H
FFFFH
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to 0V)
Large-Signal Settling Time: 5V/div
Output Voltage
Output Voltage
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
Small-Signal Settling Time: 3LSB/div
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
Output Voltage (50mV/div)
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
7FFFH to 8000H
8000H to 7FFFH
+5V
LDAC
0
+5V
LDAC
0
Time (1µs/div)
Time (1µs/div)
OUTPUT NOISE VOLTAGE vs FREQUENCY
BROADBAND NOISE
120
Noise (nV/√Hz)
Noise Voltage (20µV/div)
100
80
60
40
20
BW = 10kHz
Code = 8000H
0
100
Time (100µs/div)
1k
10k
100k
1M
Frequency (Hz)
®
9
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
OUTPUT VOLTAGE vs RLOAD
16
14
10
12
Source
8
VOUT (V)
Logic Supply Current (mA)
12
6
4
10
8
6
4
2
2
Sink
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
0.01
5
0.1
1
Logic Input Level for Data Bits (V)
SINGLE-SUPPLY CURRENT LIMIT
vs INPUT CODE
100
POWER SUPPLY REJECTION RATIO vs FREQUENCY
0
20
Short to Ground
–10
15
–20
10
–30
PSRR (dB)
5
0
–5
+15V
–40
–50
–60
+5V
–10
–70
–15
–80
Short to VCC
–90
–20
0000H 2000H 4000H 6000H 8000H A000H 0000H E000H FFFFH
100
1k
10k
Frequency (Hz)
Input Code
DIGITAL-TO-ANALOG OUTPUT GLITCH
Output Voltage (50mV/div)
IOUT (mA)
10
RLOAD (kΩ)
2LSB/div
+5V
CS
0
Time (500ns/div)
®
DAC7744
10
100k
1M
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
+25°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
+85°C
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
®
11
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
+85°C
(cont.)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
–40°C
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
®
DAC7744
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
12
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
VREFH
VREF Current (mA)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VREF Current (mA)
VREF Current (mA)
VREFL
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
VREFL
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
BIPOLAR ZERO SCALE ERROR vs TEMPERATURE
(Code 8000H)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFFH)
2
2
1.5
1.5
1
Positive Full-Scale Error (mV)
Bipolar Zero Scale Error (mV)
2.0
1.5
1.0
0.5
0
-0.5
–1.0
–1.5
VREF Current (mA)
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
VREFH
DAC D
DAC B
0.5
0
DAC A
–0.5
DAC C
–1
–1.5
–2
1.0
DAC B
DAC D
0.5
0
DAC A
–0.5
DAC C
–1.0
–1.5
–2.0
–40
–20
0
20
40
60
80
–40 –30 –20 –10
100
0
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000H)
DAC B
Quiescent Current (mA)
Negative Full-Scale Error (mV)
1.5
DAC D
0.5
0
–0.5
DAC A
DAC C
–1.0
–1.5
–2.0
–40 –30 –20 –10
0
10
20 30
40
20 30
40
50 60
70
80
90
80
90
POWER SUPPLY CURRENT vs TEMPERTURE
2
1.0
10
Temperature (°C)
Temperature (°C)
50 60
70
80
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
ICC
IDD
ISS
Data = FFFFH (all DACs)
No Load
–40 –30 –20 –10
90
0
10
20 30
40
50 60
70
Temperature (°C)
Temperature (°C)
®
13
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
SUPPLY CURRENT vs CODE
OUTPUT VOLTAGE vs RLOAD
15
10
Source
(mA)
VOUT (V)
5
0
–5
Sink
–10
–15
0.01
0.1
1
10
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
ICC
IDD
ISS
0000H
100
2000H
4000H
6000H
8000H
A000H
C000H
E000H
RLOAD (kΩ)
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Small-Signal Settling Time: 3LSB/div
Output Voltage
Output Voltage
Large-Signal Settling Time: 5V/div
FFFFH
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
Short to Ground
POWER SUPPLY REJECTION RATIO vs FREQUENCY
20
0
15
–10
–20
10
PSRR (dB)
IOUT (mA)
–30
5
0
–5
–40
–50
–15V
–60
+15V
–70
–10
–80
–15
–90
–20
0000H
+5V
–100
2000H
4000H
6000H
8000H
A000H
C000H
E000H
FFFFH
100
Digital Input Code
10k
Frequency (Hz)
®
DAC7744
1k
14
100k
1M
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
Output Voltage (50mV/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
7FFFH to 8000H
8000H to 7FFFH
+5V
LDAC
0
+5V
LDAC
0
Time (1µs/div)
Time (1µs/div)
®
15
DAC7744
THEORY OF OPERATION
by the external voltage references (VREFL and VREFH, respectively). The digital input is a 16-bit parallel word and
the DAC input registers offer a readback capability. The
converters can be powered from either a single +15V supply
or a dual ±15V supply. The device offers a reset function
which immediately sets all DAC output voltages and DAC
registers to mid-scale code 8000H or to zero scale, code
0000H. See Figures 2 and 3 for the basic operation of the
DAC7744.
The DAC7744 is a quad voltage output, 16-bit digital-toanalog converter (DAC). The architecture is an R-2R ladder
configuration with the three MSB’s segmented followed by
an operational amplifier that serves as a buffer. Each DAC
has its own R-2R ladder network, segmented MSBs and
output op amp (see Figure 1). The minimum voltage output
(zero scale) and maximum voltage output (full scale) are set
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREFH
VREFH Sense
VREFL
VREFL Sense
FIGURE 1. DAC7744 Architecture.
Data
Bus
1
DB15 (MSB)
NC
48
2
DB14
NC
47
3
DB13
NC
46
4
DB12
NC
45
5
DB11
VOUTA Sense
44
6
DB10
VOUTA
43
7
DB9
VREFL AB Sense
42
8
DB8
VREFL AB
41
9
DB7
VREFH AB
40
10
DB6
VREFH AB Sense
39
11
DB5
VOUTB Sense
38
12
DB4
VOUTB
37
13
DB3
VOUTC Sense
36
14
DB2
VOUTC
35
15
DB1
VREFH CD Sense
34
16
DB0 (LSB)
VREFH CD
33
17
RSTSEL
VREFL CD
32
VREFL CD Sense
31
VOUTD Sense
30
VOUTD
29
DAC7744
Reset DACs
18
RST
Load DAC Registers
19
LOADDACS
READ/WRITE
20
R/W
21
A1
VSS
28
22
A0
AGND
27
23
CS
VCC
26
24
DGND
VDD
25
Address
Chip Select
0V to +10V
+10.000V
0V to +10V
0V to +10V
+10.000V
0V to +10V
0.1µF
NC = No Connection
0.1µF
FIGURE 2. Basic Single-Supply Operation of the DAC7744.
®
DAC7744
16
+
+
+15V
1µF
+5V
1µF
Data
Bus
1
DB15 (MSB)
NC
48
2
DB14
NC
47
3
DB13
NC
46
4
DB12
NC
45
5
DB11
VOUTA Sense
44
6
DB10
VOUTA
43
7
DB9
VREFL AB Sense
42
8
DB8
VREFL AB
41
–10V
9
DB7
VREFH AB
40
+10V
10
DB6
VREFH AB Sense
39
11
DB5
VOUTB Sense
38
12
DB4
VOUTB
37
13
DB3
VOUTC Sense
36
14
DB2
VOUTC
35
15
DB1
VREFH CD Sense
34
DAC7744
–10V to +10V
–10V to +10V
–10V to +10V
16
DB0 (LSB)
VREFH CD
33
+10V
+5V
17
RSTSEL
VREFL CD
32
–10V
Reset DACs
18
RST
VREFL CD Sense
31
Load DAC Registers
19
LOADDACS
VOUTD Sense
30
READ/WRITE
20
R/W
VOUTD
29
21
A1
VSS
28
Address
Chip Select
A0
AGND
27
23
CS
VCC
26
DGND
VDD
–15V
0.1µF
22
24
–10V to +10V
+
1µF
+15V
+
1µF
0.1µF
25
NC = No Connection
+5V
+
0.1µF
1µF
FIGURE 3. Basic Dual-Supply Operation of the DAC7744.
ANALOG OUTPUTS
When VSS = –15V (dual supply operation), the output amplifier can swing to within 4V of the supply rails, guaranteed
over the –40°C to +85°C temperature range. With VSS = 0V
(single-supply operation), and with RLOAD also connected to
ground, the output can swing to ground. Care must also be
taken when measuring the zero-scale error when VSS = 0V.
Since the output voltage cannot swing below ground, the
output voltage may not change for the first few digital input
codes (0000H, 0001H, 0002H, etc.), if the output amplifier has
a negative offset. At the negative limit of –5mV, the first
specified output starts at code 0021H.
allows the loop around the output amplifier to be closed at
the load, thus ensuring an accurate output voltage, as shown
in Figure 4.
DAC7744
Due to the high accuracy of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 10V fullscale range has a 1LSB value of 152µV. With a load current
of 1mA, series wiring and connector resistance of only
150mΩ (RW2) will cause a voltage drop of 150µV, as shown
in Figure 4. To understand what this means in terms of a
system layout, the resistivity of a typical 1 ounce copper-clad
printed circuit board is 1/2 mΩ per square. For a 1mA load,
a 20 milli-inch wide printed circuit conductor 6 inches long
will result in a voltage drop of 150µV.
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
VOUTB Sense
38
VOUTB
37
RW1
RW2
VOUT
RLOAD
+V
+10V
RW1
RW2
VOUT
RLOAD
FIGURE 4. Analog Output Closed-Loop Configuration
(1/2 DAC7744). RW represents wiring resistances.
The DAC7744 offers a force and sense output configuration
for the high open-loop gain output amplifiers. This feature
®
17
DAC7744
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V, provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
connected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation
of the device is not guaranteed.
microamps to approximately 2.0mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. The DAC7744 features a reference drive and
sense connection such that the internal errors caused by the
changing reference current and the circuit impedances can be
minimized. Figures 5 through 12 show different reference
configurations and the effect on the linearity and differential
linearity.
The analog supplies (or the analog supplies and the reference
power supplies) have to come up first. If the power supplies
for the reference come up first, then the VCC and VSS
supplies will be “powered from the reference via the ESD
protection diode”, see page 4.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages and can vary from a few
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
DAC7744
+V
OPA2234
VOUT
100Ω
2200pF
–10V
1000pF
VOUTB Sense
38
VOUTB
37
100Ω
–V
1000pF
+V
2200pF
+10V
VOUT
FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves (1/2 DAC7744).
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
DAC7744
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
VOUTB Sense
38
VOUTB
37
+V
VOUT
100Ω
2kΩ
2200pF
OPA350
1000pF
+0.050V
100Ω
99kΩ
1000pF
2200pF
+V
OPA227
+10V
VOUT
NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage
drops across the 100Ω resistor and the output stage of the buffer op amp.
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV Used for Single-Supply Performance Curves
(1/2 DAC7744).
®
DAC7744
18
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0.5
0
–0.5
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8.
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
VOUTB Sense
38
VOUTB
37
DAC7744
+V
OPA2234
VOUT
100Ω
2200pF
–5V
1000pF
–V
100Ω
1000pF
2200pF
+V
+5V
VOUT
–V
FIGURE 8. Dual-Supply Buffered Referenced with VREFL = –5V and VREFH = +5V (1/2 DAC7744).
®
19
DAC7744
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
DAC7744
+V
VOUT
1kΩ
100Ω
2200pF
OPA350
1000pF
VOUTB Sense
38
VOUTB
37
0.05V
100Ω
99kΩ
1000pF
2200pF
+V
OPA227
+5V
VOUT
FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0.5
0
–0.5
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0
–0.5
–1.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9.
®
DAC7744
20
A1
A0
R/W
CS
RST
L
L
H
H
L
L
H
H
X
X
X
X
L
H
L
H
L
H
L
H
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
↑
↑
RSTSEL LOADDACS
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
↑
H
X
X
INPUT
REGISTER
DAC
REGISTER
MODE
DAC
Write
Write
Write
Write
Read
Read
Read
Read
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Write
Hold
Reset to Zero
Reset to Midscale
Write Input
Write Input
Write Input
Write Input
Read Input
Read Input
Read Input
Read Input
Update
Hold
Reset to Zero
Reset to Midscale
A
B
C
D
A
B
C
D
All
All
All
All
TABLE I. DAC7744 Logic Truth Table.
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The DAC7744 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7744 offers
both a differential reference input as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows transistor
to be placed within the loop to implement a digitallyprogrammable, uni-directional current source. The availability of a differential reference also allows programmability
for both the full-scale and zero-scale currents. The output
current is calculated as:
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7744. Note
that each DAC register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the DAC register is
latched. The first set of registers (the input registers) are
triggered via the A0, A1, R/W, and CS inputs. Only one of
these registers is transparent at any given time.
The double-buffered architecture is designed mainly so that
each DAC input register can be written to at any time and
then all DAC voltages updated simultaneously by the rising
edge of LOADDACS. It also allows a DAC input register to
be written to at any point then the DAC output voltages can
be synchronously changed via a trigger signal connected to
LOADDACS.
  V H – VREF L   N  
I OUT =   REF

 • 
R SENSE
 65, 536  

DIGITAL TIMING
Figure 11 and Table II provide detailed timing for the digital
interface of the DAC7744.
+ (VREF L / R SENSE )
Figure 12 shows a DAC7744 in a 4-to-20mA current output
configuration. The output current can be determined by
Equation 3:
DIGITAL INPUT CODING
The DAC7744 input data is in Straight Binary format. The
output voltage is given by Equation 1.
VOUT = VREF
(V H – VREF L) • N
L + REF
(2)
(3)
 5V – 1V   N    1V 
•
I OUT =  
 +
  250Ω   65, 536    250Ω 
(1)
65, 536
where N is the digital input code. This equation does not
include the effects of offset (zero scale) or gain (full scale)
errors.
At full scale, the output current is 16mA plus the 4mA for
the zero current. At zero scale, the output current is the offset
current of 4mA (1V/250Ω).
®
21
DAC7744
tWCS
CS
tRCS
CS
tRDH
tRDS
tWS
tWH
tAS
tAH
R/W
A0/A1
R/W
tLS
tLH
tLWD
tAH
tAS
tLX
LOADDACS
A0/A1
tDZ
±0.003% of FSR
Error Band
tDH
tDS
Data In
tS
Data Valid
Data Out
tCSD
VOUT
Data Read Timing
Data Write Timing
tSS
±0.003% of FSR
Error Band
tSH
RESET SEL
tRSH
tRSS
RST
+FS
VOUT,RESET SEL LOW
–FS
+FS
VOUT,RESET SEL HIGH
MS
–FS
DAC7744 Reset Timing
FIGURE 11. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tLX
tDS
tDH
tLWD
tSS
tSH
tRSS
tRSH
tS
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
CS LOW to LOADDACS HIGH
CS LOW after LOADDACS HIGH
LOADDACS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDACS LOW
RSTSEL Valid Before RESET HIGH
RSTSEL Valid After RESET HIGH
RESET LOW Before RESET HIGH
RESET LOW After RESET HIGH
Settling Time
100
10
10
10
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
DAC7744
22
TYP
85
MAX
70
130
40
0
10
0
15
40
80
40
0
15
40
0
120
10
10
11
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
IOUT
VPROGRAMMED
DAC7744
NC
48
NC
47
NC
46
NC
45
VOUTA Sense
44
VOUTA
43
VREFL AB Sense
42
VREFL AB
41
VREFH AB
40
VREFH AB Sense
39
RSENSE
250Ω
+V
OPA2350
100Ω
20kΩ
2200pF
1000pF
VOUTB Sense
38
VOUTB
37
+1.0V
100Ω
80kΩ
1000pF
2200pF
+V
IOUT
VPROGRAMMED
RSENSE
250Ω
GND
FIGURE 12. 4-to-20mA Digitally-Controlled Current Source (1/2 DAC7744).
®
23
DAC7744
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC7744E
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
DAC7744E/1K
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
DAC7744E/1KG4
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
DAC7744EB
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
B
DAC7744EB/1K
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
B
DAC7744EBG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
B
DAC7744EC
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
C
DAC7744EC/1K
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
C
DAC7744ECG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
C
DAC7744EG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7744E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC7744E/1K
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
DAC7744EB/1K
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
DAC7744EC/1K
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7744E/1K
SSOP
DL
48
1000
367.0
367.0
55.0
DAC7744EB/1K
SSOP
DL
48
1000
367.0
367.0
55.0
DAC7744EC/1K
SSOP
DL
48
1000
367.0
367.0
55.0
Pack Materials-Page 2
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