Samsung K6F1016U4C-AF55 64k x16 bit super low power and low voltage full cmos static ram Datasheet

K6F1016U4C Family
CMOS SRAM
Document Title
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
Preliminary
0.0
Initial Draft
May 17, 2001
1.0
Finalize
- Changed 48-TBGA vertical dimension
E1(Typical) 0.55mm to 0.58mm
E2(Typical) 0.35mm to 0.32mm
September 27, 2001 Final
2.0
Revised
- Added Lead Free product(K6F1016U4C-AF55/AF70) in PRODUCT
LIST
September 15, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
64K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The K6F1016U4C families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with
low data retention current.
Process Technology: Full CMOS
Organization: 64K x16 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48-TBGA-6.00x7.00(Leaded and Lead Free)
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
PKG Type
K6F1016U4C-F
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
0.5µA2)
2mA
48-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
DNU
B
I/O9
UB
A3
A4
CS
I/O1
Clk gen.
Vcc
Vss
Row
Addresses
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
DNU
A7
I/O4
Vcc
E
Vcc
I/O13
DNU
DNU
I/O5
Vss
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
DNU
A12
A13
WE
I/O8
H
DNU
A8
A9
A10
A11
DNU
Precharge circuit.
Row
select
Data
cont
I/O1~I/O8
Memory array
1024 rows
64 × 16 columns
I/O Circuit
Column select
Data
cont
I/O9~I/O16
Data
cont
Column Addresses
48-TBGA: Top View
CS
OE
Name
Function
Name
Function
WE
CS
Chip Select Input
Vcc
Power
UB
OE
Output Enable Input
Vss
Ground
LB
WE
Write Enable Input
UB
Upper Byte(I/O9~16)
Address Inputs
LB
Lower Byte(I/O1~8)
A0~A15
I/O1~I/O16 Data Inputs/Outputs
DNU
Control Logic
Do Not Use
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F1016U4C-EF55
K6F1016U4C-EF70
K6F1016U4C-AF55
K6F1016U4C-AF70
48-TBGA(Leaded), 55ns, 3.0V
48-TBGA(Leaded), 70ns, 3.0V
48-TBGA(Lead Free), 55ns, 3.0V
48-TBGA(Lead Free), 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
I/O1~8
I/O9~16
Mode
Power
H
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
Standby
X1)
X1)
X1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
L
X1)
High-Z
High-Z
Output Disabled
Active
L
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
1)
L
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
H
L
L
Dout
Dout
Word Read
Active
L
L
L
H
Din
High-Z
Lower Byte Write
Active
L
1)
X
L
H
L
High-Z
Din
Upper Byte Write
Active
L
X1)
L
L
L
Din
Din
Word Write
Active
1)
X
1. X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to VCC+0.3V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 seconds may affect reliability.
-3-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
V
Input high voltage
VIH
2.2
-
Vcc+0.22)
V
Input low voltage
VIL
-
0.6
V
-0.2
3)
Note:
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min Typ1) Max Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V,
LB≤0.2V or/and UB≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
2
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, LB=VIL or/
and UB=VIL, VIN=VIL or VIH
70ns
-
-
20
55ns
-
-
26
-
-
0.4
V
2.4
-
-
V
-
0.5
5
µA
Average operating current
Output low voltage
VOL
Output high voltage
VOH
Standby Current (CMOS)
ISB1
IOL=2.1mA
IOH =-1.0mA
Other input = VSS to Vcc
1) CS≥Vcc-0.2V(CS controlled) or
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)
mA
1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.
-4-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
AC OPERATING CONDITIONS
VTM3)
TEST CONDITIONS (Test Load and Input/Output Reference)
R12)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL=30pF+1TTL
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
55ns
Min
Read
Write
Units
70ns
1)
Max
Min
Max
Read Cycle Time
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
UB, LB Access Time
tBA
-
55
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
20
0
25
ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
UB, LB Valid to End of Write
tBW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS≥Vcc-0.2V1), VIN≥0V
Data retention current
IDR
Vcc=1.5V, CS≥Vcc-0.2V , VIN≥0
Data retention set-up time
tSDR
Recovery time
tRDR
1)
See data retention waveform
Min
Typ2)
Max
Unit
1.5
-
3.3
V
µA
-
0.3
1
0
-
-
tRC
-
-
ns
1. 1) CS≥Vcc-0.2V(CS controlled) or
2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled)
2. Typical value are measured at TA=25°C and not 100% tested.
-5-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
Data out
High-Z
tOHZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
-6-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
Data in
High-Z
tDH
tWHZ
Data out
High-Z
Data Valid
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
-7-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
VCC
tSDR
Data Retention Mode
tRDR
2.7V
2.2V
VDR
CS, LB/UB
GND
CS≥VCC - 0.2V or LB=UB≥Vcc-0.2V
-8-
Revision 2.0
September 2003
K6F1016U4C Family
CMOS SRAM
PACKAGE OUTLINE
Units: millimeters
48 BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
Bottom View
B
B1
B
6
5
4
3
2
1
A
B
#A1
C
C
C
C1
D
C1/2
E
F
G
H
B/2
Detail A
Side View
A
Y
0.58/Typ.
E1
E
0.32/Typ.
E2
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
1. Bump counts: 48(8 row x 6 column)
B1
-
3.75
-
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
-
0.90
1.00
E1
-
0.58
-
E2
0.27
0.32
0.37
Y
-
-
0.08
Notes.
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
-9-
Revision 2.0
September 2003
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