NTMS7N03R2 Power MOSFET 7 Amps, 30 Volts N−Channel SOIC−8 Features • • • • • • • http://onsemi.com Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature SOIC−8 Surface Mount Package Avalanche Energy Specified IDSS Specified at Elevated Temperature Pb−Free Package is Available 7 AMPERES 30 VOLTS RDS(on) = 23 mW N−Channel D Typical Applications • • • • • DC−DC Converters Power Management Motor Controls Inductive Loads Replaces MMSF7N03HD, MMSF7N03Z, and MMSF5N03HD in Many Applications G S MARKING DIAGRAM 8 SOIC−8 CASE 751 STYLE 13 8 1 E7N03 AYWWG G 1 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT N−C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2005 June, 2005 − Rev. 4 1 Publication Order Number: NTMS7N03R2/D NTMS7N03R2 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage Rating VDSS 30 Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 30 Vdc Gate−to−Source Voltage − Continuous VGS ± 20 Vdc Thermal Resistance, Junction−to−Ambient (Note 1) RqJA 50 °C/W Total Power Dissipation @ TA = 25°C PD 2.5 W Drain Current − Continuous @ TA = 25°C Drain Current − Continuous @ TA = 70°C Drain Current − Pulsed (Note 4) ID ID Adc IDM 8.5 6.8 25 Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 85 °C/W Total Power Dissipation @ TA = 25°C PD 1.47 W Drain Current − Continuous @ TA = 25°C Drain Current − Continuous @ TA = 70°C Drain Current − Pulsed (Note 4) ID ID Adc IDM 6.5 5.2 18 Thermal Resistance, Junction−to−Ambient (Note 3) RqJA 156 °C/W Total Power Dissipation @ TA = 25°C PD 0.8 W Drain Current − Continuous @ TA = 25°C Drain Current − Continuous @ TA = 70°C Drain Current − Pulsed (Note 4) ID ID Adc IDM 4.8 3.8 14 TJ, Tstg − 55 to +150 °C EAS 288 mJ Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 4.0 mH, RG = 25 W) 1. 2. 3. 4. Apk Apk Apk 2 in. Sq. FR−4 PCB mounting, (2 oz. Cu 0.06 in. thick single sided), 10 Sec. Max. 2 in. Sq. FR−4 PCB mounting, (2 oz. Cu 0.06 in. thick single sided), t = steady state. Minimum FR4 or G10 PCB, t = steady state. Pulse test: Pulse Width = 300 ms, Duty Cycle = 2%. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model Class 1E Class A Class 0 ORDERING INFORMATION Package Shipping † SOIC−8 2500 / Tape & Reel SOIC−8 (Pb−Free) 2500 / Tape & Reel Device NTMS7N03R2 NTMS7N03R2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTMS7N03R2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max 30 − − 41 − − − − 0.02 − 1.0 10 − − 100 1.0 − 1.6 4.0 3.0 − − − 18.6 23.5 23 28 Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Notes 5 and 7) (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (Note 5) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Notes 5 and 7) (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 3.5 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 5.0 Adc) (Notes 5 and 7) VDS(on) − 93 115 mV gFS 3.0 13 − Mhos Ciss − 1064 1190 pF Coss − 300 490 Crss − 94 120 td(on) − 15 30 tr − 71 185 td(off) − 27 70 tf − 38 80 td(on) − 8.0 − tr − 38 − td(off) − 33 − Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) (Note 5) Vdc mV/°C mW DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 9.1 W) (Note 5) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 10 Vdc, RG = 9.1 W) (Note 5) Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (Note 5) tf − 49 QT − 26 43 Q1 − 3.1 − Q2 − 6.0 − Q3 − 5.5 − VSD − 0.82 1.1 − 0.67 − trr − 27 − ta − 15 − tb − 11.5 − QRR − 0.02 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 5) (IS = 7.0 Adc, VGS = 0 Vdc) (Note 5) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 5) Reverse Recovery Stored Charge 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperature. 7. Reflects Typical Values. Cpk + * TypŤ ŤMax limit 3 S http://onsemi.com 3 Vdc ns mC NTMS7N03R2 TYPICAL ELECTRICAL CHARACTERISTICS 10 VGS = 10 V 18 3.6 V 3.8 V 4V 4.6 V 8V 16 7V 14 TJ = 25°C I D, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 20 3.4 V 6V 12 3.2 V 5V 10 8 3V 6 2.4 V 4 2.8 V 2 0 9 VDS = 10 V 8 7 6 5 4 25°C 3 TJ = 100°C 2 −55°C 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 0 3.5 R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.6 0.05 ID = 3.5 A TJ = 25°C 0.5 TJ = 25°C 0.04 0.4 0.03 0.3 VGS = 4.5 V 0.02 0.2 10 V 0.01 0.1 0 1 2 3 4 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 3. On−Resistance versus Gate−To−Source Voltage 0 0 10 15 Figure 4. On−Resistance versus Drain Current and Gate Voltage VGS = 0 V VGS = 10 V ID = 3.5 A 1.5 1 0.5 0 −5 0 5 ID, DRAIN CURRENT (AMPS) 1000 2 I DSS , LEAKAGE (nA) R DS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics 0.5 1 1.5 2 2.5 3 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 125°C 100 TJ = 100°C 10 1 −2 0 25 50 75 100 125 5 T , JUNCTION TEMPERATURE (°C) J 150 0 10 20 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 4 30 NTMS7N03R2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. C, CAPACITANCE (pF) During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2800 VDS = 0 V 2400 Ciss VGS = 0 V TJ = 25°C 2000 Crss 1600 Ciss 1200 800 Coss 400 Crss 0 10 5 0 VGS 5 10 15 20 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 1.2 QT 1.0 8 VGS 6 0.8 4 Q1 0.6 Q2 ID = 3.5 A TJ = 25°C VDD = 24 V ID = 7 A VGS = 10 V td(off) tf 100 tr td(on) 10 0.4 2 0 1000 t, TIME (ns) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTMS7N03R2 0 5 10 15 20 25 30 0 QG, TOTAL GATE CHARGE (nC) 1 1 10 100 RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS , SOURCE CURRENT (AMPS) 8 7 6 VGS = 0 V TJ = 25°C 5 4 3 2 1 0 0.40 0.50 0.60 0.70 0.80 0.90 1.00 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current http://onsemi.com 6 NTMS7N03R2 di/dt = 300 A/ms I S, SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. I D, DRAIN CURRENT (AMPS) 100 10 1 VGS = 20 V SINGLE PULSE TC = 25°C 100 ms 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.01 10 ms dc Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 0.1 1 10 100 EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For 400 ID = 12 A 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 7 NTMS7N03R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 Normalized to qja at 10s. Chip 0.0163 W 0.0652 W 0.1988 W 0.0307 F 0.1668 F 0.5541 F 0.6411 W 0.9502 W 0.01 1.9437 F 72.416 F SINGLE PULSE Ambient 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 1.0E+01 Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 8 1.0E+02 1.0E+03 NTMS7N03R2 PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 1 0.25 (0.010) M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 STYLE 13: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 N.C. SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NTMS7N03R2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 10 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTMS7N03R2/D