IDT IDT6178S15P Cmos staticram 16k (4k x 4-bit) cache-tag ram Datasheet

IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
IDT6178S
CMOS StaticRAM
16K (4K x 4-BIT)
CACHE-TAG RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed Address to MATCH Valid time
– Military: 12/15/20/25ns
– Commercial: 10/12/15/20/25ns (max.)
• High-speed Address Access time
– Military: 12/15/20/25ns
– Commercial: 10/12/15/20/25ns (max.)
• Low-power consumption
– IDT6178S
Active: 300mW (typ.)
• Produced with advanced CMOS high-performance
technology
• Input and output TTL-compatible
• Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ
• Military product 100% compliant to MIL-STD-883,
Class B
The IDT6178 is a high-speed cache address comparator
sub-system consisting of a 16,384-bit StaticRAM organized
as 4K x 4. Cycle Time and Address to MATCH Valid are equal.
The IDT6178 features an onboard 4-bit comparator that
compares RAM contents and current input data. The result is
an active HIGH on the MATCH pin. The MATCH pins of
several IDT6178s can be handed together to provide enabling
or acknowledging signals to the data cache or processor.
The IDT6178 is fabricated using IDT’s high-performance,
high-reliability CMOS technology. Address to MATCH and
Data to MATCH times are as fast as 10ns.
All inputs and outputs of the IDT6178 are TTL-compatible
and the device operates from a single 5V supply.
The IDT6178 is packaged in either a 22-pin, 300-mil Plastic
or Ceramic DIP package or 24-pin SOJ. Military grade product
is manufactured in compliance with latest revision of MILSTD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
16,384-BIT
MEMORY
ARRAY
ADDRESS
DECODE
VCC
GND
A11
I/O0 – I/O3
4
CONTROL I/O
4
WE
OE
CLR
CLEAR
MEMORY
ARRAY
CONTROL
4
COMPARATOR
4
MATCH
2953 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1994 Integrated Device Technology, Inc.
MAY 1994
DSC-1059/2
11.1
11.1
1
1
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A0
1
24
VCC
A0
1
22
VCC
A1
2
23
A11
A1
2
21
A11
A2
3
22
A10
A2
3
20
A10
A3
4
21
A9
A3
4
19
A9
A4
5
20
A8
A4
5
18
A8
A5
6
19
NC
A5
6
17
CLR
NC
7
18
CLR
A6
7
16
I/O3
A6
8
17
I/O3
9
8
15
A7
A7
I/O2
16
I/O2
10
14
15
I/O1
9
I/O1
11
14
I/O0
10
13
I/O0
12
13
MATCH
11
12
MATCH
OE
WE
GND
P22-1
&
D22-1
OE
WE
GND
2953 drw 03
SOJ
TOP VIEW
2953 drw 02
DIP
TOP VIEW
S024-4
ABSOLUTE MAXIMUM RATINGS(1)
PIN DESCRIPTIONS
Symbol
Rating
Value
Unit
VTERM
Terminal Voltage with respect
to GND
–0.5 to +7.0
V
–55 to +125
°C
TA
Operating Temperature
A0–A11
Address Inputs
TBIAS
Temperature Under Bias
–65 to +135
°C
I/O0–I/O3
Data Input/Output
TSTG
Storage Temperature
–65 to +150
°C
MATCH
Match
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
WE
OE
CLR
Write Enable
2953 tbl 04
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
Output Enable
Clear
VCC
Power
GND
Ground
2953 tbl 01
RECOMMENDED DC
OPERATING CONDITIONS
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient Temperature
GND
Commercial
0°C to +70°C
0V
0V
Military
–55°C to +125°C
Symbol
Parameter
VCC
Supply Voltage
5.0V ± 10%
GND
Supply Voltage
5.0V ± 10%
VIH
Input High Voltage
VCC
VIL
2953 tbl 02
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2(2)
–
6.0
V
–
0.8
V
–0.5
(1)
NOTES:
1. VIL = –3.0V for pulse width less than 20ns, once per cycle.
2. VIH = 2.5V for clear pin.
TRUTH TABLES(1)
WE
OE
CLR
MATCH
Mode
H
L
H
X
H
H
Valid(2)
Invalid
Match Cycle
Write Cycle
H
L
H
Invalid
Read Cycle
X
X
L
Invalid
Clear Cycle
NOTE:
1. H = VIH, L = VIL, X = Don’t care.
2. Valid Match = VOH, Valid Non-Match = VOL.
2953 tbl 05
CAPACITANCE (TA = 25°C, f = 1MHz)
Symbol
CIN
CI/O
2953 tbl 03
Parameter
Input Capacitance
Condition
VIN = 0V
Max
8
Units
pF
I/O Capacitance
VOUT = 0V
8
pF
NOTE:
2953 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
11.1
2
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6178S
Symbol
|ILI|
Parameter
Test Condition
Input Leakage Current
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to VCC
—
10
µA
|ILO|
Output Leakage Current
OE = VIH, VOUT = 0V to VCC
—
10
µA
VOL
Output Low Voltage
IOL = 8mA (I/O0 – I/O3)
—
0.4
V
IOL = 10mA (I/O0 – I/O3)
—
0.5
V
VOH
Output High Voltage
IOL = 16mA (Match)
—
0.4
V
IOL = 20mA (Match)
—
0.5
V
IOH = –4mA (I/O0 – I/O3)
2.4
—
V
IOH = –8mA (Match)
2.4
—
V
2953 tbl 07
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
Symbol
Parameter
6178S10
Max.
6178S12(1)
Max.
6178S15(1)
Max.
6178S20/25
Max.
Unit
ICC1
Operating Power Supply Current
Outputs Open, VCC = Max., f = 0(2)
COM'L.
MIL.
90
—
90
110
90
110
90
110
mA
mA
ICC2
Dynamic Operating Current
COM'L.
Outputs Open, VCC = Max., f = fMAX(2) MIL.
180
—
160
180
140
160
140
160
mA
mA
NOTES:
1. Military values are preliminary only.
2. fMAX = 1/tRC, only address inputs are cycling at fMAX. f = 0 means no address inputs change.
2953 tbl 08
+5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
240Ω
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
MATCHOUT
See Figures 2 and 3
AC Test Load for Match Cycle
128Ω
30pF*
See Figure 1
2953 tbl 09
2953 drw 04
Figure 1. AC Test Load for MATCH
+5V
+5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
255Ω
30pF*
5pF*
2953 drw 06
2953 drw 05
Figure 2. AC Test Load
Figure 3. AC Test Load
(for tOLZ, tOHZ, tWHZ, tOW)
* Including scope and jig.
11.1
3
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
CYCLE DESCRIPTION
Read Cycle: When WE and CLR are HIGH and OE is LOW,
the RAM is in a read cycle. The state of the Match pin is not
guaranteed, but in the current implementation it continues to
reflect the output of the comparator. The Match pin goes
HIGH during read cycles since the data at the specified
address is the same as the data (being read) at the I/Os of the
RAM.
Match Cycle: A match cycle occurs when all control signals
(OE, WE, CLR) are HIGH. At that time, data supplied to the
RAM on the I/O pins is compared with the data stored at the
specified address. The totem-pole match output is HIGH
when there is a match at all data bits, and drives LOW if there
is not a match.
Write Cycle: The write cycle is conventional, occuring when
WE is LOW and CLR is HIGH. OE may be either HIGH or LOW,
since it is overridden by WE. The state of the Match pin is not
guaranteed, but in the current implementation it continues to
reflect the output of the comparator. The Match pin goes
HIGH during write cycles since the data at the specified
address is the same as the data (being written) at the I/Os of
the RAM.
Clear Cycle: When CLR is asserted, every bit in the RAM is
cleared to zero. If OE is LOW during a clear cycle, the RAM
I/Os will be driven. However, this data is not necessarily
zeros, even after a considerable time. The Match pin is
enabled, but its state is not predicable.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6178S10(1)
Symbol
Parameter
Min.
Max.
6178S12
Min.
Max.
6178S15
Min.
6178S20
Max.
Min.
Max.
6178S25
Min.
Max.
Unit
Match Cycle
tADM
Address to Match Valid
—
10
—
12
—
15
—
20
—
25
ns
tDAM
Data Input to Match Valid
—
8
—
11
—
13
—
15
—
15
ns
tMHO
Match Valid Hold from OE
0
—
0
—
0
—
0
—
0
—
ns
—
10
—
12
—
15
—
20
—
20
ns
0
—
0
—
0
—
0
—
0
—
ns
—
10
—
12
—
15
—
20
—
20
ns
0
—
0
—
0
—
0
—
0
—
ns
ns
tMHCLR
OE HIGH to Match Valid
Match Valid Hold from WE
WE HIGH to Match Valid
Match Valid Hold from CLR
tMHA
Match Valid Hold from Address
3
—
3
—
3
—
3
—
3
—
tMHD
Match Valid Hold from Data
3
—
3
—
3
—
3
—
3
—
tOEM
tMHW
tWEM
NOTE:
1. 0°C to +70°C temperature range only.
ns
2953 tbl 10
TIMING WAVEFORM OF MATCH CYCLE(1)
ADDRESS
tADM
tMHA
OE
tOEM
tMHO
WE
tWEM
tMHW
CLR
tMHCLR
I/O1–4 VALID READ DATAOUT
VALID MATCH DATAIN
tDAM
tMHD
MATCH
MATCH
MATCH VALID
NO MATCH
MATCH
2953 drw 07
NOTE:
1. It is not recommended to let address and data input pins float while MATCH pin is active.
11.1
4
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6178S10(1)
Symbol
Parameter
Min.
6178S12
Max.
Min.
6178S15
Max.
Min.
6178S20/25
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
10
—
12
—
15
—
20/25
—
ns
tAA
Address Access Time
—
10
—
12
—
15
—
20/25
ns
tOE
Output Enable Access Time
—
7
—
8
—
10
—
15
ns
tOH
tOLZ
Output Hold from Address Change
3
—
3
—
3
—
3
—
ns
(2)
Output Enable to Output in Low-Z Time
2
—
2
—
2
—
2
—
ns
(2)
Output Disable to Output in High-Z Time
—
6
—
7
—
9
—
12
ns
tOHZ
NOTES:
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
2953 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOLZ
(3)
tOE
tOHZ (3)
DATAOUT
DATAOUT VALID
2953 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Output enable is continuously active, OE is LOW.
3. Transition is measured ±200V from steady state.
DATAOUT VALID
DATAOUT
VALID
2953 drw 09
11.1
5
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6178S10(1)
Symbol
Parameter
6178S12
6178S15
6178S20/25
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWC
Write Cycle Time
10
—
12
—
15
—
20
—
ns
tAW
Address Valid to End-of-Write
8
—
10
—
12
—
14
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
8
—
10
—
12
—
14
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
6
—
8
—
10
—
12
—
ns
Data Hold from Write Time
0
—
0
—
0
—
0
—
ns
tWHZ
Write Enable to Output in High-Z
—
5
—
6
—
7
—
9
ns
tOW(2)
Output Active from End-of-Write
0
—
0
—
0
—
0
—
ns
tDH
(2)
NOTES:
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
2953 tbl 12
TIMING WAVEFORM OF WRITE CYCLE(1,3)
tWC
ADDRESS
tAW
tAS
tWP
tWR
WE
tWHZ
DATAOUT
(4)
(4)
tOW
(2)
(2)
tDW
DATAIN
(4)
tDH
(4)
DATAIN VALID
2953 drw 10
NOTES:
1. WE must be HIGH during all address transitions.
2. During this period, I/O pins are in the output state and the input signals must not be applied.
3. OE is HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater of tWP or (tWHZ + tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
write pulse is the specified tWP.
4. Transition is measured ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6178S10(1)
Symbol
Parameter
6178S12
Min.
Max.
Min.
12
—
5
—
50
5
6178S15
Max.
Min.
15
—
5
—
—
60
—
5
6178S20/25
Max.
Min.
Max.
Unit
20
—
25
—
ns
5
—
5
—
ns
—
80
—
100
—
ns
—
5
—
5
—
ns
Clear Cycle
tCLRC
CLR Pulse Width
CLR HIGH to WE LOW
tPOCL(3)
Power on Reset
tWECL
WE HIGH to Clear HIGH
tCLPW(2)
NOTES:
1. 0°C to +70°C temperature range only.
2. Recommended duty cycle of 10% maximum.
3. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
11.1
2953 tbl 13
6
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF CLEAR CYCLE
tCLPW
CLR
tWECL
tCLRC
WE
2953 drw 11
POWER ON RESET TIMING
tPOCL
VCC
CLR
tCLRC
WE
tWECL
2953 drw 12
ORDERING INFORMATION
IDT
6178
S
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
11.1
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C,
Compliant to MIL-STD-883, Class B)
P
Y
D
300 mil Plastic DIP (P22-1)
300 mil Small Outline, J bend (SO24-4)
300 mil Ceramic DIP (D22-1)
10
12
15
20
25
Commercial only
Speed in nanoseconds
2953 drw 13
7
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