TI1 LT1013AMFKB Dual precision operational amplifier Datasheet

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LT1013, LT1013D, LT1013M, LT1013AM
SLOS018I – MAY 1988 – REVISED JULY 2016
LT1013x Dual Precision Operational Amplifier
1 Features
3 Description
•
The LT1013x devices are dual precision operational
amplifiers, featuring high gain, low supply current, low
noise, and low-offset-voltage temperature coefficient.
1
•
•
•
•
•
•
•
•
•
Single-Supply Operation
– Input Voltage Range Extends to Ground
– Output Swings to Ground While Sinking
Current
Phase Reversal Protection
Input Offset Voltage
– 150 µV Maximum at 25°C for LT1013AM
Offset-Voltage Temperature Coefficient
– 2 µV/°C Maximum for LT1013AM
Input Offset Current
– 0.8 nA Maximum at 25°C for LT1013AM
High Gain
– 1.5 V/µV Minimum (RL = 2 kΩ) for LT1013AM
– 0.8 V/µV Minimum (RL = 600 kΩ) for
LT1013AM
Low Supply Current
– 0.5 mA Maximum at TA = 25°C for LT1013AM
Low Peak-to-Peak Noise Voltage
– 0.55 µV Typical
Low Current Noise
– 0.07 pA/√Hz Typical
For Die Only Option, See LT1013-DIE
The LT1013x devices can be operated from a single
5-V power supply; the common-mode input voltage
range includes ground, and the output can also swing
to within a few millivolts of ground. Crossover
distortion is eliminated. The LT1013x can be operated
with both dual ± 15-V and single 5-V supplies.
The LT1013C and LT1013D are characterized for
operation from 0°C to 70°C. The LT1013DI is
characterized for operation from −40°C to 105°C. The
LT1013M,
LT1013AM,
and
LT1013DM
are
characterized for operation over the full military
temperature range of −55°C to 125°C.
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
LT1013P
LT1013DP
PDIP (8)
9.81 mm × 6.35 mm
LT1013MFK
LT1013AMFK
LCCC (20)
8.89 mm × 8.89 mm
LT1013MJG
LT1013AMJG
CDIP (8)
9.60 mm × 6.67 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
PACKAGE (PINS)
LT1013D
LT1013DD
Thermocouple Amplifiers
Low-Side Current Measurement
Instrumentation Amplifiers
Symbol (Each Amplifier)
IN+
IN−
+
−
OUT
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LT1013, LT1013D, LT1013M, LT1013AM
SLOS018I – MAY 1988 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: LT1013C, ±15 V .............. 5
Electrical Characteristics: LT1013C, 5 V .................. 6
Electrical Characteristics: LT1013D, ±15 V .............. 6
Electrical Characteristics: LT1013D, 5 V .................. 7
Electrical Characteristics: LT1013DI, ±15 V ............. 7
Electrical Characteristics: LT1013DI, 5 V ............... 8
Electrical Characteristics: LT1013M, ±15 V ............ 8
Electrical Characteristics: LT1013M, 5 V ................ 9
Electrical Characteristics: LT1013AM, ±15 V.......... 9
Electrical Characteristics: LT1013AM, 5 V............ 10
Electrical Characteristics: LT1013DM, ±15 V ....... 10
Electrical Characteristics: LT1013DM, 5 V ........... 11
Operating Characteristics...................................... 11
6.18 Typical Characteristics .......................................... 12
7
Detailed Description ............................................ 17
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision H (November 2004) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet ...................................................................... 1
2
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Copyright © 1988–2016, Texas Instruments Incorporated
Product Folder Links: LT1013 LT1013D LT1013M LT1013AM
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SLOS018I – MAY 1988 – REVISED JULY 2016
5 Pin Configuration and Functions
LT1013 and LT1013D D Package
8-Pin SOIC
Top View
LT1013M and LT1013AM JG Package
or LT1013 and LT1013D P Package
8-Pin CDIP or PDIP
Top View
1IN+
1
8
1IN–
VCC–
2
7
1OUT
1OUT
1
8
VCC+
2IN+
3
6
VCC+
1IN–
2
7
2OUT
2IN–
4
5
2OUT
1IN+
3
6
2IN–
VCC–
4
5
2IN+
Not to scale
Not to scale
VCC+
NC
NC
1
19
1OUT
2
20
NC
3
LT1013M and LT1013AM FK Package
20-Pin LCCC
Top View
5
17
2OUT
NC
6
16
NC
1IN+
7
15
2IN±
NC
8
14
NC
NC
2IN+
NC
VCC±
NC
13
1IN±
12
NC
11
18
10
4
9
NC
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
SOIC
LCCC
CDIP, PDIP
1IN+
1
7
3
I
Noninverting input for channel 1
1IN–
8
5
2
I
Inverting input for channel 1
1OUT
7
2
1
O
Output for channel 1
2IN+
3
12
5
I
Noninverting input for channel 2
2IN–
4
15
6
I
Inverting input for channel 2
2OUT
5
17
7
O
Output for channel 2
NC
—
1, 3, 4, 6, 8, 9,
11, 13, 14, 16,
18, 19
—
—
No internal connection
VCC+
6
20
8
—
Positive supply Voltage
VCC–
2
10
4
—
Negative supply Voltage
Copyright © 1988–2016, Texas Instruments Incorporated
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3
LT1013, LT1013D, LT1013M, LT1013AM
SLOS018I – MAY 1988 – REVISED JULY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
44
V
VCC– – 5
VCC+
V
±30
V
VCC+ – VCC– Supply voltage (2)
VI
Input voltage (any input)
Differential input voltage (3)
Duration of short-circuit current at (or below) 25°C (4)
Case temperature for 60 s
FK package
260
°C
Lead temperature 1,6 mm (1/16 inch)
from case for 10 s
JG package
300
°C
150
°C
150
°C
TJ
Operating virtual junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
Unlimited
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltage is VCC+ with respect to VCC–.
Differential voltage is IN+ with respect to IN−.
The output may be shorted to either supply.
6.2 ESD Ratings
VALUE
UNIT
LT1013 in D and P packages
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
LT1013D in D and P packages
V(ESD)
(1)
(2)
Electrostatic
discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC+ – VCC– Supply voltage
LT1013C, LT1013D
TA
VICM
4
Ambient temperature
Input common-mode voltage
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MIN
MAX
5
30
0
70
LT1013DI
–40
105
LT1013M, LT1013AM, LT1013DM
–55
125
VCC–
VCC+ – 2
VCC- + 0.1
VCC+ – 2
LT1013C, LT1013D, LT1013DI
LT1013M, LT1013AM, LT1013DM
UNIT
V
°C
V
Copyright © 1988–2016, Texas Instruments Incorporated
Product Folder Links: LT1013 LT1013D LT1013M LT1013AM
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SLOS018I – MAY 1988 – REVISED JULY 2016
6.4 Thermal Information
LT1013x
THERMAL METRIC (1)
Junction-to-ambient thermal resistance (2) (3)
RθJA
D (SOIC)
P (PDIP)
FK (LCCC)
JG (CDIP)
8 PINS
8 PINS
20 PINS
8 PINS
101.6
49.5
—
—
Junction-to-case (top) thermal resistance
47.6
38.7
RθJB
Junction-to-board thermal resistance
42
26.7
34.8
82.9
°C/W
ψJT
Junction-to-top characterization parameter
8.3
15.9
—
—
°C/W
ψJB
Junction-to-board characterization parameter
41.5
26.6
—
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
4.0 (4)
10.8 (4)
°C/W
(2)
(3)
(4)
58.5
°C/W
(4)
RθJC(top)
(1)
35.7
(4)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA )/ RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability. Due to variation in
individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power
levels slightly above or below the rated dissipation.
The package thermal impedance is calculated in accordance with JESD 51-7.
RθJC(top) and RθJC(bot)thermal impedances are calculated in accordance with MIL-STD-883 for LCCC and CDIP
6.5 Electrical Characteristics: LT1013C, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
RS = 50 Ω
MIN
25°C
TYP (2)
MAX
60
300
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Full range
0.4
Long-term drift of input offset
voltage
25°C
0.5
25°C
0.2
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage
range
Recommended range
VOM
Maximum peak output
voltage swing
RL = 2 kΩ
AVD
Large-signal differential
voltage amplification
Full range
–15
Full range
Full range
–15
13
±12.5
±14
0.5
0.2
1.2
7
Full range
0.7
VIC = −15 V to 13.5 V
25°C
97
VIC = −14.9 V to 13 V
Full range
94
Supply-voltage rejection ratio
(ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
–30
13.5
25°C
kSVR
1.5
–15
25°C
Common-mode rejection ratio
µV/mo
25°C
±12
CMRR
µV/°C
–38
Full range
VO = ±10 V, RL = 2 kΩ
2.5
2.8
25°C
VO = ±10 V, RL = 600 Ω
µV
400
Full range
25°C
UNIT
25°C
100
Full range
nA
nA
V
V
V/µV
114
dB
117
dB
97
25°C
120
137
dB
rid
Differential input resistance
25°C
70
300
MΩ
ric
Common-mode input
resistance
25°C
4
GΩ
ICC
Supply current per amplifier
25°C
0.35
(1)
(2)
Full range
0.55
0.7
mA
Full range is 0°C to 70°C.
All typical values are at TA = 25°C.
Copyright © 1988–2016, Texas Instruments Incorporated
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6.6 Electrical Characteristics: LT1013C, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC– = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
RS = 50 Ω
450
570
0.3
Recommended range
Large-signal differential voltage amplification
–18
25°C
0
3.5
Full range
0
3
25°C
15
25
25°C
5
10
220
350
Full range
UNIT
µV
nA
nA
V
13
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.2
Supply current per amplifier
–50
–90
Output low, Isink = 1 mA
VO = 5 mV to 4 V, RL = 500 Ω
2
6
Full range
Output high, RL = 600 Ω to GND
(1)
(2)
MAX
90
Full range
25°C
Maximum peak output voltage swing
ICC
25°C
TYP (2)
Full range
Output low, RL = 600 Ω to GND
AVD
MIN
25°C
Output low, No load
VOM
TA (1)
TEST CONDITIONS
25°C
1
25°C
0.32
Full range
V
V/µV
0.5
0.55
mA
Full range is 0°C to 70°C.
All typical values are at TA = 25°C.
6.7 Electrical Characteristics: LT1013D, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
RS = 50 Ω
MIN
25°C
TYP (2)
MAX
200
800
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset
voltage
Full range
0.7
Long-term drift of input offset voltage
25°C
0.5
25°C
0.2
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
Recommended range
VOM
Maximum peak output voltage swing
RL = 2 kΩ
AVD
Large-signal differential voltage amplification
Full range
1000
Full range
–15
Full range
–38
–15
13.5
Full range
–15
13
±12.5
±14
Full range
±12
25°C
0.5
2
25°C
1.2
7
Full range
0.7
VIC = −15 V to 13.5 V
25°C
97
VIC = −14.9 V to 13 V
Full range
94
VO = ±10 V, RL = 2 kΩ
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio (ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
–30
25°C
25°C
25°C
100
Full range
µV
µV/°C
µV/mo
1.5
2.8
25°C
VO = ±10 V, RL = 600 Ω
5
UNIT
nA
nA
V
V
V/µV
114
dB
117
dB
97
25°C
120
137
dB
rid
Differential input resistance
25°C
70
300
MΩ
ric
Common-mode input resistance
25°C
4
25°C
0.35
ICC
(1)
(2)
6
Supply current per amplifier
Full range
GΩ
0.55
0.6
mA
Full range is 0°C to 70°C.
All typical values are at TA = 25°C.
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6.8 Electrical Characteristics: LT1013D, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC– = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
RS = 50 Ω
950
Recommended range
Large-signal differential voltage amplification
0.3
–18
2
nA
–50
nA
–90
25°C
0
3.5
Full range
0
3
25°C
15
25
25°C
5
10
220
350
Full range
V
13
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.2
Supply current per amplifier
µV
6
Output low, Isink = 1 mA
VO = 5 mV to 4 V, RL = 500 Ω
UNIT
1200
Full range
Output high, RL = 600 Ω to GND
(1)
(2)
MAX
250
Full range
25°C
Maximum peak output voltage swing
ICC
25°C
TYP (2)
Full range
Output low, RL = 600 Ω to GND
AVD
MIN
25°C
Output low, No load
VOM
TA (1)
TEST CONDITIONS
25°C
1
25°C
0.32
Full range
V
V/µV
0.5
mA
0.55
Full range is 0°C to 70°C.
All typical values are at TA = 25°C.
6.9 Electrical Characteristics: LT1013DI, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
RS = 50 Ω
MIN
25°C
TYP (2)
MAX
200
800
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset
voltage
Full range
0.7
Long-term drift of input offset voltage
25°C
0.5
25°C
0.2
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
Recommended range
VOM
Maximum peak output voltage swing
RL = 2 kΩ
AVD
Large-signal differential voltage amplification
Full range
–15
Full range
–15
13.5
–15
13
25°C
±12.5
±14
0.5
0.2
25°C
1.2
7
Full range
0.7
VIC = −15 V to 13.5 V
25°C
97
VIC = −14.9 V to 13 V
Full range
94
Supply-voltage rejection ratio (ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
–30
Full range
25°C
kSVR
µV/mo
1.5
25°C
±12
Common-mode rejection ratio
µV/°C
–38
Full range
CMRR
5
2.8
25°C
VO = ±10 V, RL = 2 kΩ
µV
1000
Full range
VO = ±10 V, RL = 600 Ω
UNIT
25°C
100
Full range
nA
nA
V
V
V/µV
114
dB
117
dB
97
25°C
120
137
dB
rid
Differential input resistance
25°C
70
300
MΩ
ric
Common-mode input resistance
25°C
4
25°C
0.35
ICC
(1)
(2)
Supply current per amplifier
Full range
GΩ
0.55
0.6
mA
Full range is –40°C to 105°C.
All typical values are at TA = 25°C.
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6.10 Electrical Characteristics: LT1013DI, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC– = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
MIN
25°C
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
RS = 50 Ω
MAX
250
950
1200
0.3
2
nA
Full range
6
25°C
–18
–50
nA
Full range
Output low, RL = 600 Ω to GND
Maximum peak output voltage swing
Large-signal differential voltage amplification
ICC
25°C
0
3.5
Full range
0
3
V
25°C
15
25
25°C
5
10
220
350
Full range
13
Output low, Isink = 1 mA
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.2
Output high, RL = 600 Ω to GND
AVD
–90
Recommended range
Output low, No load
VOM
UNIT
µV
Full range
25°C
(1)
(2)
TYP (2)
VO = 5 mV to 4 V, RL = 500 Ω
25°C
1
25°C
0.32
V
V/µV
0.5
Supply current per amplifier
mA
Full range
0.55
Full range is –40°C to 105°C.
All typical values are at TA = 25°C.
6.11 Electrical Characteristics: LT1013M, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
TA (1)
TEST CONDITIONS
RS = 50 Ω
MIN
25°C
TYP (2)
MAX
60
300
Full range
550
Temperature coefficient of input offset voltage
Full range
0.5
(3)
Long-term drift of input offset voltage
25°C
0.5
25°C
0.2
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
Recommended range
VOM
Maximum peak output voltage swing
RL = 2 kΩ
AVD
Large-signal differential voltage amplification
Full range
–15
Full range
VO = ±10 V, RL = 600 Ω
VO = ±10 V, RL = 2 kΩ
–15
13.5
–14.9
13
25°C
±12.5
Full range
±11.5
0.5
2
1.2
7
Full range
97
Full range
94
Supply-voltage rejection ratio (ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
25°C
100
Full range
µV/°C
nA
nA
V
V
V/µV
0.25
25°C
kSVR
±14
25°C
VIC = −14.9 V to 13 V
Common-mode rejection ratio
–30
Full range
VIC = −15 V to 13.5 V
CMRR
1.5
–45
25°C
µV
µV/mo
5
25°C
25°C
2.5
UNIT
117
dB
117
dB
97
25°C
120
137
dB
rid
Differential input resistance
25°C
70
300
MΩ
ric
Common-mode input resistance
25°C
4
25°C
0.35
ICC
(1)
(2)
(3)
8
Supply current per amplifier
Full range
GΩ
0.55
0.7
mA
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
On products compliant to MIL-PRF-38535, Class B, this parameter is not production tested.
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6.12 Electrical Characteristics: LT1013M, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC− = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TYP (2)
MAX
90
450
Full range
400
1500
125°C
200
750
25°C
0.3
TEST CONDITIONS
MIN
25°C
VIO
RS = 50 Ω
Input offset voltage
RS = 50 Ω, VIC = 0.1 V
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
–50
nA
–120
25°C
0
3.5
Full range
0
3
Recommended range
Output low, No load
Output low, RL = 600 Ω to GND
Maximum peak output voltage swing
Large-signal differential voltage amplification
V
25°C
15
25
25°C
5
10
220
350
Full range
18
Output low, Isink = 1 mA
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.1
Output high, RL = 600 Ω to GND
(1)
(2)
-18
Full range
ICC
2
10
25°C
AVD
µV
nA
Full range
VOM
UNIT
VO = 5 mV to 4 V, RL = 500 Ω
25°C
1
25°C
0.32
V
V/µV
0.5
Supply current per amplifier
mA
Full range
0.65
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
6.13 Electrical Characteristics: LT1013AM, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RS = 50 Ω
TA (1)
MIN
25°C
TYP (2)
MAX
40
150
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset voltage
Full range
0.4
Long-term drift of input offset voltage
25°C
0.4
25°C
0.15
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
Recommended range
VOM
Maximum peak output voltage swing
RL = 2 kΩ
AVD
Large-signal differential voltage amplification
Full range
–12
Full range
25°C
Full range
13.5
13
±12
25°C
0.8
2.5
25°C
1.5
8
Full range
0.5
VIC = −15 V to 13.5 V
25°C
100
VIC = −14.9 V to 13 V
Full range
Supply-voltage rejection ratio (ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
–20
–15
±13
kSVR
0.8
–14.9
Full range
Common-mode rejection ratio
µV/°C
µV/mo
–30
25°C
CMRR
2 (3)
2.5
25°C
VO = ±10 V, RL = 2 kΩ
µV
300
Full range
VO = ±10 V, RL = 600 Ω
UNIT
±14
103
Full range
100
nA
V
V
V/µV
117
dB
97
25°C
nA
120
dB
25°C
123
140
dB
rid
Differential input resistance
25°C
100
400
MΩ
ric
Common-mode input resistance
25°C
5
25°C
0.35
ICC
(1)
(2)
(3)
Supply current per amplifier
Full range
GΩ
0.5
0.6
mA
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
On products compliant to MIL-PRF-38535, Class B, this parameter is not production tested.
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6.14 Electrical Characteristics: LT1013AM, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC− = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
TA (1)
TYP (2)
MAX
60
250
Full range
250
900
125°C
120
450
25°C
0.2
1.3
TEST CONDITIONS
MIN
25°C
VIO
RS = 50 Ω
Input offset voltage
RS = 50 Ω, VIC = 0.1 V
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
6
25°C
–80
25°C
0
3.5
Full range
0
3
Recommended range
Output low, RL = 600 Ω to GND
Maximum peak output voltage swing
Large-signal differential voltage amplification
V
25°C
15
25
25°C
5
10
220
350
Full range
15
Output low, Isink = 1 mA
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.2
Output high, RL = 600 Ω to GND
ICC
–35
nA
Output low, No load
(1)
(2)
–15
Full range
AVD
µV
nA
Full range
VOM
UNIT
VO = 5 mV to 4 V, RL = 500 Ω
25°C
1
25°C
0.31
V
V/µV
0.45
Supply current per amplifier
mA
Full range
0.55
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
6.15 Electrical Characteristics: LT1013DM, ±15 V
at specified free-air temperature, VCC± = ±15 V, VIC = 0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RS = 50 Ω
TA (1)
MIN
25°C
TYP (2)
MAX
200
800
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset voltage
Full range
0.5
Long-term drift of input offset voltage
25°C
0.5
25°C
0.2
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
Recommended range
VOM
Maximum peak output voltage swing
RL = 2 kΩ
AVD
Large-signal differential voltage amplification
Full range
1000
Full range
–15
Full range
VO = ±10 V, RL = 600 Ω
VO = ±10 V, RL = 2 kΩ
–15
13.5
–14.9
13
25°C
±12.5
Full range
±11.5
0.5
2
1.2
7
Full range
97
Full range
94
Supply-voltage rejection ratio (ΔVCC/ΔVIO)
VCC+ = ±2 V to ±18 V
Channel separation
VO = ±10 V, RL = 2 kΩ
25°C
100
Full range
µV/°C
nA
nA
V
V
V/µV
0.25
25°C
kSVR
±14
25°C
VIC = −14.9 V to 13 V
Common-mode rejection ratio
–30
Full range
VIC = −15 V to 13.5 V
CMRR
1.5
–45
25°C
µV
µV/mo
5
25°C
25°C
2.5 (3)
UNIT
114
dB
117
dB
97
25°C
120
137
dB
rid
Differential input resistance
25°C
70
300
MΩ
ric
Common-mode input resistance
25°C
4
25°C
0.35
ICC
(1)
(2)
(3)
10
Supply current per amplifier
Full range
GΩ
0.55
0.7
mA
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
On products compliant to MIL-PRF-38535, Class B, this parameter is not production tested.
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6.16 Electrical Characteristics: LT1013DM, 5 V
at specified free-air temperature, VCC+ = 5 V, VCC− = 0, VO = 1.4 V, VIC = 0 (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
RS = 50 Ω
Input offset voltage
RS = 50 Ω, VIC = 0.1 V
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
TYP (2)
250
950
Full range
800
2000
125°C
560
1200
25°C
0.3
2
Maximum peak output voltage
swing
–18
AVD
Large-signal differential voltage
amplification
ICC
Supply current per amplifier
nA
–50
25°C
0
3.5
Full range
0
3
25°C
15
25
25°C
5
10
220
350
Full range
nA
V
18
25°C
Output high, No load
25°C
4
4.4
25°C
3.4
4
Full range
3.1
VO = 5 mV to 4 V, RL = 500 Ω
µV
–120
Output low, Isink = 1 mA
Output high, RL = 600 Ω to GND
UNIT
10
Full range
Recommended range
MAX
25°C
25°C
Output low, RL = 600 Ω to GND
(1)
(2)
MIN
Full range
Output low, No load
VOM
TA (1)
25°C
1
25°C
0.32
Full range
V
V/µV
0.5
mA
0.65
Full range is –55°C to 125°C.
All typical values are at TA = 25°C.
6.17 Operating Characteristics
VCC± = ±15 V, VIC = 0, TA = 25°C
PARAMETER
SR
TEST CONDITIONS
Slew rate
MIN
TYP
0.2
0.4
f = 10 Hz
24
f = 1 kHz
22
MAX
UNIT
V/µs
Vn
Equivalent input noise voltage
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
0.55
µV
In
Equivalent input noise current
f = 10 Hz
0.07
pA/√Hz
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nV/√Hz
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6.18 Typical Characteristics
Table 1. Table of Graphs
FIGURE
vs Input Resistance
Figure 1
vs Temperature
Figure 2
Change in input offset voltage
vs Time
Figure 3
IIO
Input offset current
vs Temperature
Figure 4
IIB
Input bias current
vs Temperature
Figure 5
VIC
Common-mode input voltage
vs Input bias current
Figure 6
AVD
Differential voltage amplification
VIO
Input offset voltage
ΔVIO
vs Load resistance
Figure 7, Figure 8
vs Frequency
Figure 9, Figure 10
Channel separation
vs Frequency
Figure 11
Output saturation voltage
vs Temperature
Figure 12
CMRR
Common-mode rejection ratio
vs Frequency
Figure 13
kSVR
Supply-voltage rejection ratio
vs Frequency
Figure 14
ICC
Supply current
vs Temperature
Figure 15
IOS
Short-circuit output current
vs Time
Figure 16
Vn
Equivalent input noise voltage
vs Frequency
Figure 17
In
Equivalent input noise current
vs Frequency
Figure 17
VN(PP)
Peak-to-peak input noise voltage
vs Time
Pulse response
Phase shift
Figure 18
Small signal
Figure 19, Figure 21
Large signal
Figure 20, Figure 22, Figure 23
vs Frequency
Figure 9
250
10
VCC± = ±15 V
200
µV
VIO
V
IO − Input Offset Voltage − uV
VIO
V
IO − Input Offset Voltage − mV
VCC+ = 5 V, VCC− = 0
TA = −55°C to 125°C
VCC± = ±15 V
TA = −55°C to 125°C
1
VCC+ = 5 V
VCC− = 0
TA = 25°C
0.1
RS
0.01
1k
−
+
VCC± = ± 15V
TA = 25°C
3k
10 k
1M
3M
10 M
|V CC±| − Supply Voltage − V
Figure 1. Input Offset Voltage vs Input Resistance
12
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100
50
0
−50
−100
−150
−200
RS
30 k 100 k 300 k
150
−250
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 2. Input Offset Voltage of Representative Units vs
Free-Air Temperature
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1
VIC = 0
VCC± = ±15 V
TA = 25°C
4
0.8
IIIO
IO − Input Offset Current − nA
3
2
JG Package
0.6
VCC± =±2.5 V
0.4
VCC+ = 5 V, VCC− = 0
0.2
1
VCC± =±15 V
0
0
1
2
3
4
0
−50
5
t − Time After Power-On − min
75
125
100
15
5
VIC = 0
VIC
V IC − Common-Mode Input Voltage − V
TA = 25°C
−25
IIB
I IB − Input Bias Current − nA
50
Figure 4. Input Offset Current vs Free-Air Temperature
−30
−20
VCC± = 5 V, VCC− = 0
−15
VCC± = ±2.5 V
−10
VCC± = ±15 V
−5
0
−50
−25
0
25
50
100
75
TA − Free-Air Temperature − °C
125
Figure 5. Input Bias Current vs Free-Air Temperature
10
VCC± = ±15 V
VO = ±10 V
TA = 25°C
4
TA = −55°C
1
TA = 125°C
0.4
400
1k
4k
10 k
4
10
5
VCC± = ±15 V
(left scale)
0
3
VCC± = 5 V
VCC− = 0
(right scale)
2
−5
1
−10
0
−15
0
−5
−10
−15
−20
−25
IIB − Input Bias Current − nA
−1
−30
Figure 6. Common-Mode Input Voltage vs Input Bias
Current
A
AVD
VD − Differential Voltage Amplification − V/ µV
A
AVD
VD − Differential Voltage Amplification − V/ µV
25
TA − Free-Air Temperature − °C
Figure 3. Warm-Up Change in Input Offset Voltage vs Time
After Power On
0.1
100
0
−25
VIC
V IC − Common-Mode Input Voltage − V
XVIO
∆V
µV
IO − Change in Input Offset Voltage − uV
5
10
VCC± = 5 V, VCC− = 0
VO = 20 mV to 3.5 V
4
TA = −55°C
1
TA = 25°C
TA = 125°C
0.4
0.1
100
400
1k
4k
10 k
RL − Load Resistance − Ω
RL − Load Resistance − Ω
Figure 7. Differential Voltage Amplification vs Load
Resistance
Figure 8. Differential Voltage Amplification vs Load
Resistance
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80°
20
VIC = 0
CL = 100 pF
TA = 25°C
VCC± = ±15 V
15
100°
120°
Phase Shift
10
VCC+ = 5 V
VCC− = 0
AVD
140°
160°
5
0
VCC+ = 5 V
VCC− = 0
180°
200°
−5
VCC± = ±15 V
220°
−10
−15
0.01
0.3
140
A
AVD
VD − Differential Voltage Amplification − dB
A
AVD
VD − Differential Voltage Amplification − dB
25
Figure 9. Differential Voltage Amplification and Phase Shift
vs Frequency
80
VCC+ = 5 V
VCC− = 0
VCC± = ±15 V
60
40
20
0
1
10 100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 10. Differential Voltage Amplification vs Frequency
10
160
VCC+ = 5 V to 30 V
VCC− = 0
Limited by
Thermal
Interaction
120
Output Saturation Voltage − V
VCC± = ±15 V
VI(PP) = 20 V to 5 kHz
RL = 2 kΩ
TA = 25°C
140
Channel Separation − dB
100
−20
0.01 0.1
240°
10
1
3
f − Frequency − MHz
CL = 100 pF
TA = 25°C
120
RL = 100 Ω
RL = 1 kΩ
100
Limited by
Pin-to-Pin
Capacitance
80
Isink = 10 mA
1
Isink = 5 mA
Isink = 1 mA
0.1
Isink = 100 µA
Isink = 10 µA
Isink = 0
60
10
100
1k
100 k
10 k
0.01
−50
1M
−25
f − Frequency − Hz
Figure 11. Channel Separation vs Frequency
kSVR − Supply-Voltage Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
140
TA = 25°C
100
VCC± = ±15 V
VCC+ = 5 V
VCC− = 0
80
60
40
20
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 13. Common-Mode Rejection Ratio vs Frequency
14
125
Figure 12. Output Saturation Voltage vs Free-Air
Temperature
120
0
10
0
25
50
75
100
TA − Free-Air Temperature − °C
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VCC± = ±15 V
TA = 25°C
120
100
Positive
Supply
80
Negative
Supply
60
40
20
0
0.1
1
10
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 14. Supply-Voltage Rejection Ratio vs Frequency
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40
I OS − Short-Circuit Output Current − mA
I CC − Supply Current Per Amplifier − µ A
460
420
380
VCC = 15 V
340
300
VCC+ = 5 V, VCC− = 0
260
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
TA = 25°C
20
TA = 125°C
0
TA = 125°C
−10
TA = 25°C
−20
TA = −55°C
−30
−40
0
Figure 16. Short-Circuit Output Current vs Elapsed Time
V
Vn
nV/Hz
Hz
n − Equivalent Input Noise Voltage − fA/
VN(PP) − Noise Voltage − nV
VN(PP)
300 I
n
100
Vn
30
1/f Corner = 2 Hz
1
10
1600
1200
800
400
0
1k
100
VCC± = ±2 V to ±18 V
f = 0.1 Hz to 10 Hz
TA = 25°C
0
2
4
f − Frequency − Hz
10
20
VCC± = ±15 V
AV = 1
TA = 25°C
15
VCC± = ±15 V
AV = 1
TA = 25°C
10
VV)
O − Output Voltage − V
VO
VO − Output Voltage − mV
8
Figure 18. Peak-to-Peak Input Noise Voltage Over a
10-Second Period
40
20
0
−20
−40
5
0
−5
−10
−15
−60
−80
6
t − Time − s
Figure 17. Equivalent Input Noise Voltage and Equivalent
Input Noise Current vs Frequency
60
3
2000
VCC± = ±2 V to ±18 V
TA = 25°C
80
2
1
t − Elapsed Time − min
1000
Vn − Equivalent Input Noise Voltage − nV/
Vn
nV/Hz
Hz
30
10
125
Figure 15. Supply Current vs Free-Air Temperature
10
VCC = 15 V
TA = −55°C
0
2
4
6
8
10
12
14
−20
0
Figure 19. Voltage-Follower Small-Signal Pulse Response
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50
100 150 200 250 300 350
t − Time − µs
t − Time − µs
Figure 20. Voltage-Follower Large-Signal Pulse Response
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6
160
VCC+ = 5 V, VCC− = 0
VI = 0 to 100 mV
RL = 600 Ω to GND
AV = 1
TA = 25°C
VO
VO − Output Voltage − mV
120
5
VO
VO − Output Voltage − mV
140
100
80
60
40
20
0
−20
4
VCC+ = 5 V, VCC− = 0
VI = 0 to 4 V
RL = 4.7 kΩ to 5 V
AV = 1
TA = 25°C
3
2
1
0
−1
0
20
40
60
80
−2
100 120 140
0
t − Time − µs
Figure 21. Voltage-Follower Small-Signal Pulse Response
10 20 30
t − Time − µs
40
50
60
70
Figure 22. Voltage-Follower Large-Signal Pulse Response
6
VO
VO − Output Voltage − V
5
4
VCC+ = 5 V, VCC− = 0
VI = 0 to 4 V
RL = 0
AV = 1
TA = 25°C
3
2
1
0
−1
−2
0
10
20
30
40
50
60
70
t − Time − µs
Figure 23. Voltage-Follower Large-Signal Pulse Response
16
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7 Detailed Description
7.1 Overview
The LT1013x device is a dual operational amplifier with low natural VIO without programming memory that can be
erased. There are no side effects from active VIO correction used by other op amps. The LT1013x has built-in
protection for input voltage below VCC–. However, an external resistance must be add to protect the LT1013x
from input voltage greater than VCC+.
7.2 Functional Block Diagram
VCC+
9 kΩ
9 kΩ
1.6 kΩ
1.6 kΩ
100 Ω
1.6 kΩ
800 Ω
1 kΩ
Q36
Q5
Q6
Q13
Q16
Q14
Q15
Q32
Q35
Q30
J1
Q3
Q37
Q25
Q4
Q33
3.9 kΩ
Q1
2.4 kΩ
Q27
21 pF
400 Ω
Q41
Q26
2.5 pF
14 kΩ
18 Ω
Q38
IN−
OUT
Q21
Q2
Q28
Q39
400 Ω
IN+
Q12
4 pF
Q18
Q22
Q31
Q40
Q29
Q10
Q11
Q19
Q9
Q7
Q34
2 kΩ
Q8
10 pF
Q17
10 pF
Q23
Q20
75 pF
5 kΩ
5 kΩ
Q24
2 kΩ
2 kΩ
42 kΩ
600 Ω
30 Ω
1.3 kΩ
VCC−
Component values are nominal.
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Input Resistors
For voltages less than VCC–, a pair of 400-Ω resistors limit input current. These resistors have parasitic diodes to
VCC+. Therefore, external series resistance is needed if input voltage exceed VCC+
7.3.2 Output Stage
High output is provided by Q33 emitter for low output impedance. Q26 provides active current limiting for
sourcing current.
Low output is provided by Q34 collector for lower output voltage near VCC– rail. Q24 provides active current
limiting for sinking current.
Copyright © 1988–2016, Texas Instruments Incorporated
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Feature Description (continued)
7.3.3 Low-Supply Operation
The minimum supply voltage for proper operation of the LT1013x is 3.4 V (three NiCad batteries). Typical supply
current at this voltage is 290 µA; therefore, power dissipation is only 1 mW per amplifier.
7.3.4 Output Phase Reversal Protection
The LT1013x is fully specified for single-supply operation (VCC− = 0). The common-mode input voltage range
includes ground, and the output swings to within a few millivolts of ground.
Furthermore, the LT1013x has specific circuitry that addresses the difficulties of single-supply operation, both at
the input and at the output. At the input, the driving signal can fall below 0 V, either inadvertently or on a
transient basis. If the input is more than a few hundred millivolts below ground, the LT1013x is designed to deal
with the following two problems that can occur:
1. On many other operational amplifiers, when the input is more than a diode drop below ground, unlimited
current flows from the substrate (VCC− terminal) to the input, which can destroy the unit. On the LT1013x,
the 400-Ω resistors in series with the input protect the device, even when the input is 5 V below ground.
2. When the input is more than 400 mV below ground (at TA = 25°C), the input stage of similar operational
amplifiers saturates, and phase reversal occurs at the output. This can cause lockup in servo systems.
Because of unique phase-reversal protection circuitry (Q21, Q22, Q27, and Q28), the LT1013x outputs do
not reverse, even when the inputs are at −1.5 V (see Figure 24).
This phase-reversal protection circuitry does not function when the other operational amplifier on the LT1013x is
driven hard into negative saturation at the output. Phase-reversal protection does not work on amplifier 1 when
amplifier 2 output is in negative saturation nor on amplifier 2 when amplifier 1 output is in negative saturation.
At the output, other single-supply designs either cannot swing to within 600 mV of ground or cannot sink more
than a few micro amperes while swinging to ground. The all-npn output stage of the LT1013x maintains its low
output resistance and high-gain characteristics until the output is saturated. In dual-supply operations, the output
stage is free of crossover distortion.
5
4
3
2
1
0
−1
−2
VO
VO − Output Voltage − V
5
VO
VO − Output Voltage − V
VI(PP)
V
I(PP) − Input Voltage − V
5
4
3
2
1
0
3
2
1
0
−1
−1
(a) VI(PP) = −1.5 V TO4.5 V
4
(b) OUTPUT PHASE REVERSAL
EXHIBITED BY LM358
(c) NO PHASE REVERSAL
EXHIBITED BY LT1013
Figure 24. Voltage-Follower Response With Input Exceeding the Negative Common-Mode Input Voltage
Range
18
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SLOS018I – MAY 1988 – REVISED JULY 2016
Feature Description (continued)
7.3.4.1 Comparator Applications
The single-supply operation of the LT1013x is well suited for use as a precision comparator with TTL-compatible
output. In systems using both operational amplifiers and comparators, the LT1013x can perform multiple duties
(see Figure 25 and Figure 26).
4
10 mV
5 mV
2 mV
3
2
Overdrive
1
0
VO
VO − Output Voltage − V
5
VCC+ = 5 V
VCC− = 0
TA = 25°C
4
3
2
5 mV
10 mV
2 mV
1
Overdrive
Differential
Input Voltage
0
VCC+ = 5 V
VCC− = 0
TA = 25°C
100 mV
0
50 100 150 200 250 300 350 400 450
t − Time − µs
Figure 25. Low-to-High-Level Output Response for
Various Input Overdrives
Differential
Input Voltage
VO
VO − Output Voltage − V
5
100 mV
0
50 100 150 200 250 300 350 400 450
t − Time − µs
Figure 26. High-to-Low-Level Output Response for
Various Input Overdrives
7.4 Device Functional Modes
The LT1013x dual operational amplifier amplifies a differential voltage applied to the inputs.
Copyright © 1988–2016, Texas Instruments Incorporated
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LT1013x operational amplifiers are useful in a wide range of signal conditioning applications where high DC
accuracy is needed.
8.2 Typical Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative
voltages positive.
RF
RI
Vsup+
VOUT
VIN
+
VsupCopyright © 2016, Texas Instruments Incorporated
Figure 27. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable
because the amplifier circuit will use currents in the milliamp range. This ensures the part does not draw too
much current. This example chooses 10 kΩ for RI, which means 36 kΩ is used for RF. This was determined by
Equation 3.
(3)
20
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SLOS018I – MAY 1988 – REVISED JULY 2016
Typical Application (continued)
8.2.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 28. Input and Output Voltages of the Inverting Amplifier
9 Power Supply Recommendations
CAUTION
Supply voltages larger than 44 V for a single supply, or outside the range of ±22 V for
a dual supply can permanently damage the device (see Absolute Maximum Ratings).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use quality PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• Run the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Guidelines.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Copyright © 1988–2016, Texas Instruments Incorporated
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www.ti.com
10.2 Layout Examples
VIN
RIN
RG
+
VOUT
RF
Figure 29. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
VS+
RF
OUT1
VCC+
GND
IN1í
OUT2
VIN
IN1+
IN2í
VCCí
IN2+
RG
GND
RIN
Use low-ESR, ceramic
bypass capacitor
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
Ground (GND) plane on another layer
Figure 30. Operational Amplifier Board Layout for Noninverting Configuration
22
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LT1013, LT1013D, LT1013M, LT1013AM
www.ti.com
SLOS018I – MAY 1988 – REVISED JULY 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Developmental Support
For developmental support, see the following:
LT1013-DIE
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LT1013
Click here
Click here
Click here
Click here
Click here
LT1013D
Click here
Click here
Click here
Click here
Click here
LT1013M
Click here
Click here
Click here
Click here
Click here
LT1013AM
Click here
Click here
Click here
Click here
Click here
LT1013-DIE
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 1988–2016, Texas Instruments Incorporated
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SLOS018I – MAY 1988 – REVISED JULY 2016
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Product Folder Links: LT1013 LT1013D LT1013M LT1013AM
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-88760012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596288760012A
LT1013AMFKB
5962-8876001PA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8876001PA
LT1013AM
5962-88760022A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596288760022A
LT1013MFKB
5962-8876002PA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8876002PA
LT1013M
LT1013AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596288760012A
LT1013AMFKB
LT1013AMJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
LT1013AMJG
LT1013AMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8876001PA
LT1013AM
LT1013AMP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-55 to 125
LT1013CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013C
LT1013CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013C
LT1013CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013C
LT1013CDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013C
LT1013CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013C
LT1013CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LT1013CP
LT1013CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LT1013CP
LT1013DD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013D
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LT1013DDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013D
LT1013DDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013D
LT1013DDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013D
LT1013DDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
1013D
LT1013DID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
1013DI
LT1013DIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
LT1013DIP
LT1013DIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
LT1013DIP
LT1013DMD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1013DM
LT1013DMDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1013DM
LT1013DP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LT1013DP
LT1013DPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
LT1013DP
LT1013IP
OBSOLETE
PDIP
P
8
LT1013MFKB
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
TBD
POST-PLATE
N / A for Pkg Type
Addendum-Page 2
-55 to 125
596288760022A
LT1013MFKB
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LT1013MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
LT1013MJG
LT1013MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8876002PA
LT1013M
LT1013MP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-55 to 125
LT1013Y
OBSOLETE
DIESALE
Y
0
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LT1013, LT1013M :
• Catalog: LT1013
• Military: LT1013M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LT1013CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LT1013DDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
LT1013DIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LT1013CDR
SOIC
D
8
2500
340.5
338.1
20.6
LT1013DDR
SOIC
D
8
2500
340.5
338.1
20.6
LT1013DIDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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