STMicroelectronics LQFP64 Non-maskable interrupt Datasheet

SPC560D30x
SPC560D40x
32-bit MCU family built on the Power Architecture®
for automotive body electronics applications
Datasheet  preliminary data
Features
■
High-performance up to 48 MHz e200z0h CPU
– 32-bit Power Architecture® technology
CPU
– Variable length encoding (VLE)
■
Memory
– Up to 256 KB Code Flash with ECC
– Up to 64 (4x16) KB Data Flash with ECC
– Up to 16 KB SRAM with ECC
■
Interrupts
– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 38 external interrupts incl. 18 wakeup
lines
■
16-channel eDMA
■
GPIOs: 45 (LQFP64), 79 (LQFP100)
■
Timer units
– 4-channel 32-bit periodic interrupt timers
– 4-channel 32-bit system timer module
– System watchdog timer
– 32 bit real-time clock timer
■
16-bit counter time-triggered I/Os
– Up to 28 channels with PWM/MC/IC/OC
– 5 independent counters
– 27 ch. with ADC trigger capability
■
12-bit analog-to-digital converter (ADC) with up
to 33 channels
– Up to 61 channels via external multiplexing
– Individual conversion registers
– Cross triggering unit (CTU)
■
Dedicated diagnostic module for lighting
– Advanced PWM generation
– Time-triggered diagnostics
– PWM-synchronized ADC measurements
September 2013
LQFP64 (10 x 10 x 1.4 mm)
LQFP100 (14 x 14 x 1.4 mm)
■
Communications interfaces
– 1 FlexCAN interface (2.0B active) with
32 message buffers
– 3 LINFlex/UART, 1 with DMA capability
– 2 DSPI
■
Clock generation
– 4 to 16 MHz fast external crystal oscillator
– 16 MHz fast internal RC oscillator
– 128 kHz slow internal RC oscillator
– Software-controlled FMPLL
– Clock monitoring unit
■
Exhaustive debugging capability
– Nexus1 on all packages
– Nexus2+ available on emulation device
(SPC560B64B2-ENG)
■
On-chip CAN/UART bootstrap loader
■
Low power capabilities
– Several low power mode configurations
– Ultra-low power standby with RTC,SRAM
and CAN monitoring
– Fast wakeup schemes
■
Single 5 V or 3.3 V supply
■
Operates in ambient temperature range of
-40 to 125 °C
Table 1.
Device summary
Part number
Package
128 Kbyte code
Flash
256 Kbyte code
Flash
LQFP100
SPC560D30L3
SPC560D40L3
LQFP64
SPC560D30L1
SPC560D40L1
Doc ID 16315 Rev 7
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/90
www.st.com
1
Contents
SPC560D30x, SPC56040Dx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 12
4
3.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 29
4.3.3
NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 29
4.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.7
4.8
2/90
4.3.1
4.6.1
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6.2
Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.7.1
I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.7.2
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.7.3
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.7.4
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7.5
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
4.9
4.9.1
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 44
4.9.2
Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 47
Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.11
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11.1
Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11.2
Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.11.3
Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 52
4.12.1
Designing hardened software to avoid noise problems . . . . . . . . . . . . . 52
4.12.2
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.12.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53
4.13
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 55
4.14
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 58
4.16
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 59
4.17
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.18
6
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 44
4.10
4.12
5
Contents
4.17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.17.2
Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.17.3
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.18.1
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.18.2
DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.18.3
JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.1
LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.2
LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Doc ID 16315 Rev 7
3/90
List of tables
SPC560D30x, SPC56040Dx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
4/90
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC560D30, SPC560D40 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPC560D30, SPC560D40 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 37
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Program and erase specifications (code flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Program and erase specifications (data flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 56
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59
ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 49.
Table 50.
List of tables
Order codes for engineering samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Doc ID 16315 Rev 7
5/90
List of figures
SPC560D30x, SPC56040Dx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
6/90
SPC560D30, SPC560D40 series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LQFP100 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LQFP64 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 56
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 74
DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 75
DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LQFP100 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LQFP64 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Introduction
1
Introduction
1.1
Document overview
This document describes the device features and highlights the important electrical and
physical characteristics.
1.2
Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices
designed to be central to the development of the next wave of central vehicle body
controller, smart junction box, front module, peripheral body, door control and seat control
applications.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology and designed specifically for embedded
applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller
family complies with the Power Architecture technology and only implements the VLE
(variable-length encoding) APU (auxiliary processing unit), providing improved code density.
It operates at speeds of up to 48 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of
on-chip static random access memory (SRAM) and internal flash memory.
Table 2.
Pictus 512K device comparison
Device
Feature
SPC560D30L1
SPC560D30L3
CPU
SPC560D40L1
SPC560D40L3
e200z0h
Execution speed
Static – up to 48 MHz
Code flash memory
128 KB
256 KB
Data flash memory
64 KB (4 × 16 KB)
SRAM
12 KB
16 KB
eDMA
16 ch
ADC (12-bit)
16 ch
33 ch
CTU
16 ch
33 ch
16 ch
(1)
Total timer I/O
eMIOS
14 ch, 16-bit
28 ch, 16-bit
14 ch, 16-bit
28 ch, 16-bit
– Type X(2)
2 ch
5 ch
2 ch
5 ch
– Type Y(3)
—
9 ch
—
9 ch
7 ch
7 ch
7 ch
7 ch
– Type
G(4)
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Introduction
Table 2.
SPC560D30x, SPC56040Dx
Pictus 512K device comparison (continued)
Device
Feature
– Type H
(5)
SPC560D30L1
SPC560D30L3
SPC560D40L1
SPC560D40L3
4 ch
7 ch
4 ch
7 ch
45
79
LQFP64
LQFP100
SCI (LINFlex)
3
SPI (DSPI)
2
CAN (FlexCAN)
1
(6)
GPIO
45
79
Debug
Package
JTAG
LQFP64
LQFP100
1. Refer to eMIOS chapter of device reference manual for information on the channel configuration and functions.
2. Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC
3. Type Y = OPWMT + OPWMB + SAIC + SAOC
4. Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC
5. Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC
6. I/O count based on multiplexing with peripherals
8/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
2
Block diagram
Block diagram
Figure 1 shows a top-level block diagram of the Pictus 512K device series.
SRAM
16 KB
JTAG
Code Flash
256 KB
Data Flash
64 KB
64-bit 3 x 3 Crossbar Switch
JTAG Port
Instructions
(Master)
Nexus 1
e200z0h
Data
NMI
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
Flash
Controller
(Slave)
(Slave)
(Slave)
(Master)
INTC
Clocks
SRAM
Controller
eDMA
CMU
FMPLL
RTC
STM
SWT
MC_RGM MC_CGM
PIT
ECSM
MC_ME
MC_PCU
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
33 ch.
ADC
1x
eMIOS
CTU
3x
LINFlex
2x
DSPI
1x
FlexCAN
WKPU
External
Interrupt
Request
IMUX
Interrupt
Request
GPIO &
Pad Control
I/O
...
...
...
...
Legend:
ADC
BAM
CMU
CTU
DSPI
ECSM
eDMA
eMIOS
Flash
FlexCAN
FMPLL
IMUX
INTC
JTAG
LINFlex
Analog-to-Digital Converter
Boot Assist Module
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Error Correction Status Module
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Flash memory
Controller Area Network (FlexCAN)
Frequency-Modulated Phase-Locked Loop
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Figure 1.
MC_CGM
MC_ME
MC_PCU
MC_RGM
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
XBAR
Clock Generation Module
Mode Entry Module
Power Control Unit
Reset Generation Module
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Crossbar switch
Pictus 512K series block diagram
Doc ID 16315 Rev 7
9/90
Block diagram
SPC560D30x, SPC56040Dx
Table 3 summarizes the functions of all blocks present in the Pictus 512K series of
microcontrollers. Please note that the presence and number of blocks varies by device and
package.
Table 3.
Pictus 512K series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host
processor via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
network)
Supports the standard CAN communications protocol
Frequency-modulated phaselocked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller (JTAGC)
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-maskable interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
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SPC560D30x, SPC56040Dx
Table 3.
Block diagram
Pictus 512K series block summary (continued)
Block
Function
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Real-time counter (RTC)
Provides a free-running counter and interrupt generation capability that can be
used for timekeeping applications
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR (Automotive
Open System Architecture) and operating system tasks
Software watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup
events.
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Package pinouts and signal descriptions
SPC560D30x, SPC56040Dx
3
Package pinouts and signal descriptions
3.1
Package pinouts
The available LQFP pinouts are provided in the following figures. For pin signal descriptions,
please refer to Table 6.
12/90
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SPC560D30x, SPC56040Dx
Package pinouts and signal descriptions
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
Figure 2 shows the Pictus 512K in the LQFP100 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Figure 2.
LQFP100 pin configuration (top view)
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13/90
Package pinouts and signal descriptions
SPC560D30x, SPC56040Dx
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[2]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
Figure 3 shows the Pictus 512K in the LQFP64 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[3]
PB[15]
PB[14]
PB[13]
PB[12]
PB[11]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PB[4]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PB[1]
PC[6]
Figure 3.
3.2
LQFP64 pin configuration (top view)
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
3.3
●
PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from
flash.
●
PA[8] (ABS[0]) is pull-up.
●
RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
●
JTAG pads (TCK, TMS and TDI) are pull-up while TDO remains tristate.
●
Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
●
Main oscillator pads (EXTAL, XTAL) are tristate.
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used
for 1.2 V regulator stabilization.
14/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 4.
Package pinouts and signal descriptions
Voltage supply pin descriptions
Pin number
Port pin
Function
LQFP64
LQFP100
7, 28, 34, 56
15, 37, 52, 70, 84
6, 8, 26, 33, 55
14, 16, 35, 51, 69,
83
VDD_HV
Digital supply voltage
VSS_HV
Digital ground
VDD_LV
1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV
pin.(1)
11, 23, 57
19, 32, 85
VSS_LV
1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV
pin.(1)
10, 24, 58
18, 33, 86
VDD_BV
Internal regulator supply voltage
12
20
1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet for details).
3.4
Pad types
In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(a)
M = Medium(a) (b)
F = Fast(a) (b)
I = Input only with analog feature(a)
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
3.5
System pins
The system pins are listed in Table 5.
Table 5.
Port pin
RESET
System pin descriptions
I/O
Function
direction
Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
Pad type
I/O
M
RESET
Pin number
configuration LQFP64
Input, weak
pull-up only
after PHASE2
9
LQFP100
17
a. See the I/O pad electrical characteristics in the device datasheet for details.
b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium
(see the PCR[SRC] description in the device reference manual).
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Package pinouts and signal descriptions
Table 5.
SPC560D30x, SPC56040Dx
System pin descriptions (continued)
Port pin
I/O
Function
direction
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
EXTAL mode.
Analog input for the clock generator when the
oscillator is in bypass mode.(1)
XTAL
Analog input of the oscillator amplifier circuit.
Needs to be grounded if oscillator is used in
bypass mode.(1)
Pad type
RESET
Pin number
configuration LQFP64
LQFP100
I/O
X
Tristate
27
36
I
X
Tristate
25
34
1. Refer to the relevant section of the device datasheet.
3.6
Functional ports
The functional port pins are listed in Table 6.
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions
RESET
Table 6.
Pin number
LQFP64
LQFP100
Port A
PA[0]
PA[1]
PA[2]
16/90
PCR[0]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19](3)
SIUL
eMIOS_0
CGL
eMIOS_0
WKPU
I/O
I/O
O
I/O
I
M
Tristate
5
12
PCR[1]
AF0
AF1
AF2
AF3
—
—
GPIO[1]
E0UC[1]
—
—
NMI(4)
WKPU[2](3)
SIUL
eMIOS_0
—
—
WKPU
WKPU
I/O
I/O
—
—
I
I
S
Tristate
4
7
PCR[2]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3](3)
SIUL
eMIOS_0
—
ADC
WKPU
I/O
I/O
—
O
I
S
Tristate
3
5
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
PA[8]
PA[9]
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
PCR[3]
AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
—
CS4_0
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
—
DSPI_0
SIUL
ADC
I/O
I/O
—
I/O
I
I
S
Tristate
43
68
PCR[4]
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
CS0_1
WKPU[9](3)
SIUL
eMIOS_0
—
DSPI_1
WKPU
I/O
I/O
—
I/O
I
S
Tristate
20
29
PCR[5]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
51
79
PCR[6]
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
SIUL
I/O
I/O
—
I/O
I
S
Tristate
52
80
PCR[7]
AF0
AF1
AF2
AF3
—
—
GPIO[7]
E0UC[7]
—
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
—
—
SIUL
ADC
I/O
I/O
—
—
I
I
S
Tristate
44
71
PCR[8]
AF0
AF1
AF2
AF3
—
N/A(5)
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
I/O
I/O
—
—
I
I
S
Input, weak
pull-up
45
72
PCR[9]
AF0
AF1
AF2
AF3
N/A(5)
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
I/O
I
S
Pull-down
46
73
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Package pinouts and signal descriptions
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
SPC560D30x, SPC56040Dx
Pin number
LQFP64
LQFP100
PCR[10]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
—
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
—
LINFlex_2
ADC
I/O
I/O
—
O
I
S
Tristate
47
74
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
GPIO[11]
E0UC[11]
—
—
EIRQ[16]
ADC1_S[3]
LIN2RX
SIUL
eMIOS_0
—
—
SIUL
ADC
LINFlex_2
I/O
I/O
—
—
I
I
I
S
Tristate
48
75
PCR[12]
AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
—
—
EIRQ[17]
SIN_0
SIUL
—
—
—
SIUL
DSPI_0
I/O
—
—
—
I
I
S
Tristate
22
31
PCR[13]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
—
CS3_1
SIUL
DSPI_0
—
DSPI_1
I/O
O
—
I/O
M
Tristate
21
30
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M
Tristate
19
28
PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10](3)
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
I/O
I/O
I
M
Tristate
18
27
I/O
O
—
O
M
Tristate
14
23
Port B
PB[0]
18/90
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
—
LIN2TX
SIUL
FlexCAN_0
—
LINFlex_2
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PB[6]
PB[7]
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
I/O
—
—
I
I
I
S
SIUL
LINFlex_0
—
—
I/O
O
—
—
SIUL
GPIO[19]
—
—
—
—
—
—
WKPU
WKPU[11](3)
LIN0RX
LINFlex_0
SIUL
GPIO[17]
—
—
—
—
LINFlex_0
LIN0RX
WKPU
WKPU[4](3)
CAN0RX FlexCAN_0
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
Tristate
15
24
M
Tristate
64
100
I/O
—
—
—
I
I
S
Tristate
1
1
PCR[17]
AF0
AF1
AF2
AF3
—
—
PCR[18]
AF0
AF1
AF2
AF3
PCR[19]
AF0
AF1
AF2
AF3
—
—
PCR[20]
AF0
AF1
AF2
AF3
—
GPIO[20]
—
—
—
ADC1_P[0]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
32
50
PCR[21]
AF0
AF1
AF2
AF3
—
GPIO[21]
—
—
—
ADC1_P[1]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
35
53
PCR[22]
AF0
AF1
AF2
AF3
—
GPIO[22]
—
—
—
ADC1_P[2]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
36
54
PCR[23]
AF0
AF1
AF2
AF3
—
GPIO[23]
—
—
—
ADC1_P[3]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
37
55
GPIO[18]
LIN0TX
—
—
Doc ID 16315 Rev 7
19/90
Package pinouts and signal descriptions
PB[8]
PB[9]
PB[10]
PB[11]
PB[12]
PB[13]
PB[14]
20/90
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
SPC560D30x, SPC56040Dx
Pin number
LQFP64
LQFP100
PCR[24]
AF0
AF1
AF2
AF3
—
—
GPIO[24]
—
—
—
ADC1_S[4]
WKPU[25](3)
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I
Tristate
30
39
PCR[25]
AF0
AF1
AF2
AF3
—
—
GPIO[25]
—
—
—
ADC1_S[5]
WKPU[26](3)
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
I
Tristate
29
38
PCR[26]
AF0
AF1
AF2
AF3
—
—
GPIO[26]
—
—
—
ADC1_S[6]
WKPU[8](3)
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
I
J
Tristate
31
40
PCR[27]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC1_S[12]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
I/O
I
J
Tristate
38
59
PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC1_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
39
61
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC1_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
40
63
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC1_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
J
Tristate
41
65
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PB[15]
PCR
PCR[31]
Alternate
function(1)
AF0
AF1
AF2
AF3
—
I/O
Function
GPIO[31]
E0UC[7]
—
CS4_0
ADC1_X[3]
Peripheral
direction
SIUL
eMIOS_0
—
DSPI_0
ADC
Pad
(2)
type
I/O
I/O
—
O
I
J
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
Tristate
42
67
Port C
PC[0](6) PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input, weak
pull-up
59
87
PC[1](6) PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F
Tristate
54
82
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
—
—
EIRQ[5]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
50
78
PCR[35]
AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
—
EIRQ[6]
SIUL
DSPI_1
ADC
—
SIUL
I/O
I/O
O
—
I
S
Tristate
49
77
PCR[36]
AF0
AF1
AF2
AF3
—
—
GPIO[36]
—
—
—
SIN_1
EIRQ[18]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
M
Tristate
62
92
PCR[37]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
M
Tristate
61
91
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
—
—
SIUL
LINFlex_1
—
—
I/O
O
—
—
S
Tristate
16
25
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
Doc ID 16315 Rev 7
21/90
Package pinouts and signal descriptions
PC[7]
PC[8]
PC[9]
PC[10]
PC[11]
PC[12]
PC[13]
PC[14]
22/90
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
I/O
—
—
—
I
I
S
SIUL
LINFlex_2
eMIOS_0
—
I/O
O
I/O
—
SIUL
GPIO[41]
—
—
eMIOS_0
E0UC[7]
—
—
LINFlex_2
LIN2RX
WKPU
WKPU[13](3)
SIUL
GPIO[39]
—
—
—
—
—
—
LINFlex_1
LIN1RX
WKPU
WKPU[12](3)
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
SPC560D30x, SPC56040Dx
Pin number
LQFP64
LQFP100
Tristate
17
26
S
Tristate
63
99
I/O
—
I/O
—
I
I
S
Tristate
2
2
PCR[39]
AF0
AF1
AF2
AF3
—
—
PCR[40]
AF0
AF1
AF2
AF3
PCR[41]
AF0
AF1
AF2
AF3
—
—
PCR[42]
AF0
AF1
AF2
AF3
GPIO[42]
—
—
MA[1]
SIUL
—
—
ADC
I/O
—
—
O
M
Tristate
13
22
PCR[43]
AF0
AF1
AF2
AF3
—
GPIO[43]
—
—
MA[2]
WKPU[5](3)
SIUL
—
—
ADC
WKPU
I/O
—
—
O
I
S
Tristate
—
21
PCR[44]
AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
—
97
PCR[45]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
98
PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
—
—
EIRQ[8]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
S
Tristate
—
3
GPIO[40]
LIN2TX
E0UC[3]
—
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PC[15]
PCR
PCR[47]
Alternate
function(1)
AF0
AF1
AF2
AF3
—
I/O
Function
GPIO[47]
E0UC[15]
—
—
EIRQ[20]
Peripheral
direction
SIUL
eMIOS_0
—
—
SIUL
Pad
(2)
type
I/O
I/O
—
—
I
M
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
Tristate
—
4
Port D
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PCR[48]
AF0
AF1
AF2
AF3
—
—
GPIO[48]
—
—
—
WKPU[27](3)
ADC1_P[4]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
I
Tristate
—
41
PCR[49]
AF0
AF1
AF2
AF3
—
—
GPIO[49]
—
—
—
WKPU[28](3)
ADC1_P[5]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
I
Tristate
—
42
PCR[50]
AF0
AF1
AF2
AF3
—
GPIO[50]
—
—
—
ADC1_P[6]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
43
PCR[51]
AF0
AF1
AF2
AF3
—
GPIO[51]
—
—
—
ADC1_P[7]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
44
PCR[52]
AF0
AF1
AF2
AF3
—
GPIO[52]
—
—
—
ADC1_P[8]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
45
PCR[53]
AF0
AF1
AF2
AF3
—
GPIO[53]
—
—
—
ADC1_P[9]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
46
Doc ID 16315 Rev 7
23/90
Package pinouts and signal descriptions
PD[6]
PD[7]
PD[8]
PD[9]
PD[10]
PD[11]
PD[12]
PD[13]
24/90
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
SPC560D30x, SPC56040Dx
Pin number
LQFP64
LQFP100
PCR[54]
AF0
AF1
AF2
AF3
—
GPIO[54]
—
—
—
ADC1_P[10]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
47
PCR[55]
AF0
AF1
AF2
AF3
—
GPIO[55]
—
—
—
ADC1_P[11]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
48
PCR[56]
AF0
AF1
AF2
AF3
—
GPIO[56]
—
—
—
ADC1_P[12]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
49
PCR[57]
AF0
AF1
AF2
AF3
—
GPIO[57]
—
—
—
ADC1_P[13]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
56
PCR[58]
AF0
AF1
AF2
AF3
—
GPIO[58]
—
—
—
ADC1_P[14]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
57
PCR[59]
AF0
AF1
AF2
AF3
—
GPIO[59]
—
—
—
ADC1_P[15]
SIUL
—
—
—
ADC
I
—
—
—
I
I
Tristate
—
58
PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC1_S[8]
SIUL
DSPI_0
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
60
PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC1_S[9]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
I/O
I/O
—
I
J
Tristate
—
62
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PD[14]
PD[15]
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
PCR[62]
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ADC1_S[10]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
64
PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ADC1_S[11]
SIUL
DSPI_1
eMIOS_0
—
ADC
I/O
O
I/O
—
I
J
Tristate
—
66
Port E
PE[0]
PE[1]
PE[2]
PE[3]
PE[4]
PE[5]
PCR[64]
AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
—
WKPU[6](3)
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
6
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
M
Tristate
—
8
PCR[66]
AF0
AF1
AF2
AF3
—
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
—
I
I
M
Tristate
—
89
PCR[67]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
90
PCR[68]
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
—
93
PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC
I/O
I/O
I/O
O
M
Tristate
—
94
Doc ID 16315 Rev 7
25/90
Package pinouts and signal descriptions
PE[6]
PE[7]
PE[8]
PE[9]
PE[10]
PE[11]
PE[12]
PCR
Alternate
function(1)
I/O
Function
Peripheral
direction
(2)
type
Pin number
LQFP64
LQFP100
PCR[70]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
M
Tristate
—
95
PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC
SIUL
I/O
I/O
O
O
I
M
Tristate
—
96
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
—
E0UC[22]
—
SIUL
—
eMIOS_0
—
I/O
—
I/O
—
M
Tristate
—
9
PCR[73]
AF0
AF1
AF2
AF3
—
GPIO[73]
—
E0UC[23]
—
WKPU[7](3)
SIUL
—
eMIOS_0
—
WKPU
I/O
—
I/O
—
I
S
Tristate
—
10
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
—
CS3_1
—
EIRQ[10]
SIUL
—
DSPI_1
—
SIUL
I/O
—
O
—
I
S
Tristate
—
11
PCR[75]
AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
—
WKPU[14](3)
SIUL
eMIOS_0
DSPI_1
—
WKPU
I/O
I/O
O
—
I
S
Tristate
—
13
PCR[76]
AF0
AF1
AF2
AF3
—
—
GPIO[76]
—
—
—
ADC1_S[7]
EIRQ[11]
SIUL
—
—
—
ADC
SIUL
I/O
—
—
—
I
I
S
Tristate
—
76
Port H
26/90
Pad
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
SPC560D30x, SPC56040Dx
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
PCR
PH[9](6) PCR[121]
PH[10](6
)
PCR[122]
Alternate
function(1)
I/O
Function
Peripheral
direction
Pad
(2)
type
configuration
Port pin
Functional port pin descriptions (continued)
RESET
Table 6.
Package pinouts and signal descriptions
Pin number
LQFP64
LQFP100
AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
60
88
AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input, weak
pull-up
53
81
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0;
PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
3. All WKPU pins also support external interrupt capability. See “wakeup unit” chapter of the device reference manual for
further details.
4. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
5. “Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of the
device reference manual for details.
6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1 2001.
Doc ID 16315 Rev 7
27/90
Electrical characteristics
SPC560D30x, SPC56040Dx
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 7 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 7.
Parameter classifications
Classification tag
Note:
28/90
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D
Those parameters are derived mainly from simulations.
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
4.3
Electrical characteristics
NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the
device configuration, namely electrical parameters such as high voltage supply and
oscillator margin, as well as digital functionality (watchdog enable/disable after reset).
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
4.3.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 8 shows
how NVUSRO[PAD3V5V] controls the device configuration.
Table 8.
PAD3V5V field description
(1)
Value
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the
OSCILLATOR_MARGIN bit value. Table 9 shows how NVUSRO[OSCILLATOR_MARGIN]
controls the device configuration.
Table 9.
OSCILLATOR_MARGIN field description
Value(1)
Description
0
Low consumption configuration (4 MHz/8 MHz)
1
High margin configuration (4 MHz/16 MHz)
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.3
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the
WATCHDOG_EN bit value. Table 9 shows how NVUSRO[WATCHDOG_EN] controls the
device configuration.
Table 10.
WATCHDOG_EN field description
Value(1)
Description
0
Disable after reset
1
Enable after reset
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
Doc ID 16315 Rev 7
29/90
Electrical characteristics
SPC560D30x, SPC56040Dx
4.4
Absolute maximum ratings
Table 11.
Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Max
—
0
0
V
0.3
6.0
V
VSS
SR Digital ground on VSS_HV pins
VDD
SR
Voltage on VDD_HV pins with respect to
ground (VSS)
—
VSS_LV
SR
Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—
VDD_BV SR
Voltage on VDD_BV (regulator supply)
pin with respect to ground (VSS)
—
Relative to VDD
Voltage on VSS_HV_ADC (ADC
VSS_ADC SR reference) pin with respect to ground
(VSS)
Voltage on VDD_HV_ADC (ADC
VDD_ADC SR reference) pin with respect to ground
(VSS)
Unit
Min
—
—
Relative to VDD
VSS  0.1 VSS + 0.1
0.3
6.0
VDD  0.3 VDD + 0.3
VSS  0.1 VSS + 0.1
0.3
V
V
6.0
VDD  0.3 VDD + 0.3
0.3
V
V
VIN
SR
—
Voltage on any GPIO pin with respect to
ground (VSS)
Relative to VDD
IINJPAD
SR
Injected input current on any pin during
overload condition
—
10
10
mA
Absolute sum of all injected input
currents during overload condition
—
50
50
mA
—
70
—
64
—
—
150
mA
—
55
150
°C
IINJSUM SR
VDD = 5.0 V ± 10%, PAD3V5V =
0
Sum of all the static I/O current within a
IAVGSEG SR
supply segment(1)
V = 3.3 V ± 10%, PAD3V5V =
DD
1
ICORELV SR
Low voltage static current sink through
VDD_BV
TSTORAGE SR Storage temperature
6.0
VDD  0.3 VDD + 0.3
V
mA
1. Supply segments are described in Section 4.7.5, I/O pad current specification.
Note:
30/90
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS),
the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
4.5
Recommended operating conditions
Table 12.
Recommended operating conditions (3.3 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
—
0
0
V
Voltage on VDD_HV pins with respect to ground
(VSS)
—
3.0
3.6
V
VSS_LV(2) SR —
Voltage on VSS_LV (low voltage digital supply)
pins with respect to ground (VSS)
—
VDD_BV(3) SR —
Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS)
VSS_ADC SR —
Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS)
VSS
SR — Digital ground on VSS_HV pins
VDD(1)
SR —
VDD_ADC
(4)
SR —
VIN
SR —
IINJPAD
SR —
IINJSUM
SR —
TVDD
Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS)
VSS  0.1 VSS + 0.1
—
3.0
3.6
Relative to VDD
VDD  0.1 VDD + 0.1
—
VSS  0.1 VSS + 0.1
3.0(5)
—
Relative to VDD
V
V
V
3.6
V
VDD  0.1 VDD + 0.1
—
VSS  0.1
—
Relative to VDD
—
VDD + 0.1
Injected input current on any pin during overload
condition
—
5
5
mA
Absolute sum of all injected input currents during
overload condition
—
50
50
mA
—
3.0(7)
250 x 103
(0.25
[V/µs])
Voltage on any GPIO pin with respect to ground
(VSS)
SR — VDD slope to ensure correct power
up(6)
V
V/s
1. 100 nF capacitance needs to be provided between each VDD/VSS pair.
2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
3. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Guaranteed by device validation
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)
Table 13.
Recommended operating conditions (5.0 V)
Value
Symbol
VSS
VDD(1)
C
Parameter
SR — Digital ground on VSS_HV pins
SR —
Voltage on VDD_HV pins with respect to ground
(VSS)
Doc ID 16315 Rev 7
Conditions
—
—
(2)
Voltage drop
Unit
Min
Max
0
0
4.5
5.5
3.0
5.5
V
V
31/90
Electrical characteristics
Table 13.
SPC560D30x, SPC56040Dx
Recommended operating conditions (5.0 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
VSS_LV(3) SR —
Voltage on VSS_LV (low voltage digital supply) pins
with respect to ground (VSS)
—
VSS  0.1 VSS + 0.1
—
Voltage on VDD_BV pin (regulator supply) with
VDD_BV(4) SR —
respect to ground (VSS)
(5)
5.5
3.0
5.5
V
Relative to VDD VDD  0.1 VDD + 0.1
Voltage on VSS_HV_ADC (ADC reference) pin with
respect to ground (VSS
V
—
4.5
5.5
Voltage on VDD_HV_ADC pin (ADC reference) with
(2)
Voltage drop
SR —
3.0
5.5
respect to ground (VSS)
Relative to VDD VDD  0.1 VDD + 0.1
V
VIN
SR —
IINJPAD
SR —
IINJSUM
SR —
TVDD
Voltage drop(2)
4.5
V
VSS  0.1 VSS + 0.1
VSS_ADC SR —
VDD_ADC
Max
—
—
VSS  0.1
—
Relative to VDD
—
VDD + 0.1
Injected input current on any pin during overload
condition
—
5
5
mA
Absolute sum of all injected input currents during
overload condition
—
50
50
mA
—
3.0(7)
Voltage on any GPIO pin with respect to ground
(VSS)
SR — VDD slope to ensure correct power
up(6)
V
250 x 103
V/s
(0.25
[V/µs])
1. 100 nF capacitance needs to be provided between each VDD/VSS pair.
2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6. Guaranteed by device validation
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH)
Note:
32/90
SRAM data retention is guaranteed with VDD_LV not below 1.08 V.
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
Table 14.
LQFP thermal characteristics(1)
Symbol C
Conditions(2)
Parameter
Value
LQFP64
72.1
LQFP100
65.2
LQFP64
57.3
LQFP100
51.8
LQFP64
44.1
LQFP100
41.3
LQFP64
26.5
LQFP100
23.9
LQFP64
26.2
LQFP100
23.7
LQFP64
41
LQFP100
41.6
LQFP64
43
LQFP100
43.4
LQFP64
11.5
LQFP100
10.4
LQFP64
11.1
LQFP100
10.2
Unit
Single-layer board —1s
RJA CC D
Thermal resistance, junction-to-ambient natural
convection(3)
°C/W
Four-layer board — 2s2p
RJB CC D Thermal resistance, junction-to-board(4)
Four-layer board — 2s2p
°C/W
Single-layer board — 1s
RJC CC D Thermal resistance, junction-to-case(5)
°C/W
Four-layer board — 2s2p
Single-layer board — 1s
JB CC D
Junction-to-board thermal characterization
parameter, natural convection
°C/W
Four-layer board — 2s2p
Single-layer board — 1s
JC CC D
Junction-to-case thermal characterization
parameter, natural convection
°C/W
Four-layer board — 2s2p
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C
3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-7. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA.
4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package. When Greek letters are not available, the symbols are typed as RthJB.
5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters
are not available, the symbols are typed as RthJC.
4.6.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation 1:
Doc ID 16315 Rev 7
33/90
Electrical characteristics
SPC560D30x, SPC56040Dx
Equation 1 TJ = TA + (PD x RJA)
Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
Equation 2 PD = K / (TJ + 273 °C)
Therefore, solving equations 1 and 2:
Equation 3 K = PD x (TA + 273 °C) + RJA x PD2
Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value
of TA.
4.7
I/O pad electrical characteristics
4.7.1
I/O pad types
The device provides four main I/O pad types depending on the associated alternate
functions:
●
Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission.
●
Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission.
●
Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing
low input leakage.
Medium pads can use slow configuration to reduce electromagnetic emission except for
PC[1], that is medium only, at the cost of reducing AC performance.
4.7.2
I/O input DC characteristics
Table 15 provides input DC electrical characteristics as described in Figure 4.
34/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 4.
Table 15.
Symbol
Input DC electrical characteristics definition
I/O input DC electrical characteristics
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
VIH
SR P
Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P
Input low level CMOS (Schmitt
Trigger)
—
0.4
—
0.35VDD
V
Input hysteresis CMOS (Schmitt
Trigger)
—
0.1VDD
—
—
V
VHYS CC C
ILKG
WFI
(2)
WNFI
(2)
D
TA = 40 °C
—
2
200
D
—
2
200
—
5
300
D
TA = 25 °C
No injection on
TA = 85 °C
adjacent pin
TA = 105 °C
—
12
500
P
TA = 125 °C
—
70
1000
CC D Digital input leakage
nA
SR P Digital input filtered pulse
—
—
—
40
ns
SR P Digital input not filtered pulse
—
1000
—
—
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.
Doc ID 16315 Rev 7
35/90
Electrical characteristics
4.7.3
SPC560D30x, SPC56040Dx
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
Table 16.
●
Table 16 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
●
Table 17 provides output driver characteristics for I/O pads when in SLOW
configuration.
●
Table 18 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
I/O pull-up/pull-down DC electrical characteristics
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min Typ Max
P
PAD3V5V = 0
Weak pull-up current
|IWPU| CC C
absolute value
P
10
—
150
10
—
250
VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1
10
—
150
PAD3V5V = 0
10
—
150
10
—
250
10
—
150
VIN = VIL, VDD = 5.0 V ± 10%
P
Weak pull-down current
|IWPD| CC C
absolute value
P
VIN = VIH, VDD = 5.0 V ± 10%
PAD3V5V =
PAD3V5V =
1(2)
1(2)
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
µA
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are
configured in input or in high impedance state.
Table 17.
SLOW configuration output buffer electrical characteristics
Symbol C
P
VOH CC C
Parameter
IOH = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
Output high level
I = 2 mA,
Push Pull OH
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
Unit
Min
Typ
Max
0.8VDD
—
—
0.8VDD
—
—
—
—
C
IOH = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD  0.8
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
— 0.1VDD
—
— 0.1VDD
—
—
VOL CC C
C
Output low level
I = 2 mA,
Push Pull OL
SLOW configuration
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
36/90
Value
Conditions(1)
Doc ID 16315 Rev 7
0.5
V
V
SPC560D30x, SPC56040Dx
Electrical characteristics
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are
configured in input or in high impedance state.
Table 18.
Symbol C
MEDIUM configuration output buffer electrical characteristics
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
C
IOH = 3.8 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
P
IOH = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.8VDD
—
—
0.8VDD
—
—
VDD  0.8 —
—
VOH CC C
Output high level
I = 1 mA,
Push Pull OH
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
C
IOH = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
C
IOH = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
C
IOL = 3.8 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
— 0.2VDD
P
IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
— 0.1VDD
—
— 0.1VDD
VOL CC C
Output low level
I = 1 mA,
Push Pull OL
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
V
—
C
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
C
IOL = 100 µA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
— 0.1VDD
V
0.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are
configured in input or in high impedance state.
Doc ID 16315 Rev 7
37/90
Electrical characteristics
SPC560D30x, SPC56040Dx
4.7.4
Output pin transition times
Table 19.
Output pin transition times
Symbol C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
ttr CC
D
CL = 25 pF
—
—
50
T
CL = 50 pF
VDD = 5.0 V ± 10%, PAD3V5V = 0 —
—
100
D Output transition time output
pin(2)
D SLOW configuration
CL = 100 pF
—
—
125
CL = 25 pF
—
—
50
T
CL = 50 pF
VDD = 3.3 V ± 10%, PAD3V5V = 1 —
—
100
D
CL = 100 pF
—
—
125
D
CL = 25 pF
—
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
CL = 50 pF
SIUL.PCRx.SRC = 1
—
CL = 100 pF
—
10
—
20
—
40
CL = 25 pF
—
12
—
25
—
40
T
D Output transition time output
ttr CC
pin(2)
D MEDIUM configuration
ns
—
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
SIUL.PCRx.SRC = 1
—
CL = 100 pF
CL = 50 pF
T
D
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. CL includes device and package capacitances (CPKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 20.
Table 21 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.
Table 20.
I/O supply segment
Supply segment
Package
38/90
1
2
3
4
LQFP100
pin 16 – pin 35
pin 37 – pin 69
pin 70 – pin 83
pin 84 – pin 15
LQFP64
pin 8 – pin 26
pin 28 – pin 55
pin 56 – pin 7
—
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 21.
Symbol
ISWTSLW(2)
ISWTMED
(2)
Electrical characteristics
I/O consumption
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
CL = 100 pF, 13 MHz
—
—
18.3
CL = 25 pF, 13 MHz
—
—
5
—
—
8.5
CL = 100 pF, 13 MHz
—
—
11
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
Dynamic I/O current
CC D for SLOW
CL = 25 pF
configuration
mA
Dynamic I/O current
CC D for MEDIUM
CL = 25 pF
configuration
mA
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 25 pF, 4 MHz
IRMSSLW
Root mean square
CL = 100 pF, 2 MHz
CC D I/O current for SLOW
CL = 25 pF, 2 MHz
configuration
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
IRMSMED
Root mean square
I/O current for
CC D
MEDIUM
configuration
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CL = 25 pF, 40 MHz
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 25 pF, 40 MHz
IAVGSEG
Sum of all the static
SR D I/O current within a
supply segment
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 22 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on
a single segment should remain below 100%.
Table 22.
I/O weight(1)
LQFP100/LQFP64
Pad
Weight 5 V
Weight 3.3 V
SRC(2) = 0
SRC = 1
SRC = 0
SRC = 1
PB[3]
9%
9%
10%
10%
PC[9]
8%
8%
10%
10%
Doc ID 16315 Rev 7
39/90
Electrical characteristics
Table 22.
SPC560D30x, SPC56040Dx
I/O weight(1) (continued)
LQFP100/LQFP64
Pad
40/90
Weight 5 V
Weight 3.3 V
SRC(2) = 0
SRC = 1
SRC = 0
SRC = 1
PC[14]
8%
8%
10%
10%
PC[15]
8%
11%
9%
10%
PA[2]
8%
8%
9%
9%
PE[0]
7%
7%
9%
9%
PA[1]
7%
7%
8%
8%
PE[1]
7%
10%
8%
8%
PE[8]
6%
9%
8%
8%
PE[9]
6%
6%
7%
7%
PE[10]
6%
6%
7%
7%
PA[0]
5%
7%
6%
7%
PE[11]
5%
5%
6%
6%
PC[11]
7%
7%
9%
9%
PC[10]
8%
11%
9%
10%
PB[0]
8%
11%
9%
10%
PB[1]
8%
8%
10%
10%
PC[6]
8%
8%
10%
10%
PC[7]
8%
8%
10%
10%
PA[15]
8%
11%
9%
10%
PA[14]
7%
11%
9%
9%
PA[4]
7%
7%
8%
8%
PA[13]
7%
10%
8%
9%
PA[12]
7%
7%
8%
8%
PB[9]
1%
1%
1%
1%
PB[8]
1%
1%
1%
1%
PB[10]
5%
5%
6%
6%
PD[0]
1%
1%
1%
1%
PD[1]
1%
1%
1%
1%
PD[2]
1%
1%
1%
1%
PD[3]
1%
1%
1%
1%
PD[4]
1%
1%
1%
1%
PD[5]
1%
1%
1%
1%
PD[6]
1%
1%
1%
1%
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 22.
Electrical characteristics
I/O weight(1) (continued)
LQFP100/LQFP64
Pad
Weight 5 V
Weight 3.3 V
SRC(2) = 0
SRC = 1
SRC = 0
SRC = 1
PD[7]
1%
1%
1%
1%
PD[8]
1%
1%
1%
1%
PB[4]
1%
1%
1%
1%
PB[5]
1%
1%
1%
1%
PB[6]
1%
1%
1%
1%
PB[7]
1%
1%
1%
1%
PD[9]
1%
1%
1%
1%
PD[10]
1%
1%
1%
1%
PD[11]
1%
1%
1%
1%
PB[11]
9%
9%
11%
11%
PD[12]
8%
8%
10%
10%
PB[12]
8%
8%
10%
10%
PD[13]
8%
8%
9%
9%
PB[13]
8%
8%
9%
9%
PD[14]
7%
7%
9%
9%
PB[14]
7%
7%
8%
8%
PD[15]
7%
7%
8%
8%
PB[15]
6%
6%
7%
7%
PA[3]
6%
6%
7%
7%
PA[7]
4%
4%
5%
5%
PA[8]
4%
4%
5%
5%
PA[9]
4%
4%
5%
5%
PA[10]
5%
5%
6%
6%
PA[11]
5%
5%
6%
6%
PE[12]
5%
5%
6%
6%
PC[3]
5%
5%
6%
6%
PC[2]
5%
7%
6%
6%
PA[5]
5%
6%
5%
6%
PA[6]
4%
4%
5%
5%
PC[1]
5%
17%
4%
12%
PC[0]
6%
9%
7%
8%
PE[2]
7%
10%
8%
9%
Doc ID 16315 Rev 7
41/90
Electrical characteristics
Table 22.
SPC560D30x, SPC56040Dx
I/O weight(1) (continued)
LQFP100/LQFP64
Pad
Weight 5 V
Weight 3.3 V
SRC(2) = 0
SRC = 1
SRC = 0
SRC = 1
PE[3]
7%
10%
9%
9%
PC[5]
8%
11%
9%
10%
PC[4]
8%
11%
9%
10%
PE[4]
8%
12%
10%
10%
PE[5]
8%
12%
10%
11%
PE[6]
9%
12%
10%
11%
PE[7]
9%
12%
10%
11%
PC[12]
9%
13%
11%
11%
PC[13]
9%
9%
11%
11%
PC[8]
9%
9%
11%
11%
PB[2]
9%
13%
11%
12%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. SRC: “Slew Rate Control” bit in SIU_PCR
4.8
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
Figure 5.
42/90
device start-up phase
Start-up reset requirements
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
lowpass filter
filtered by
hysteresis
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 6.
Table 23.
Symbol
Noise filtering on reset signal
Reset electrical characteristics
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD + 0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
—
0.4
—
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
VOL
CC P Output low level
Doc ID 16315 Rev 7
V
43/90
Electrical characteristics
Table 23.
Symbol
ttr
SPC560D30x, SPC56040Dx
Reset electrical characteristics (continued)
C
Parameter
Output transition time
CC D output pin(3)
MEDIUM configuration
Value
Conditions(1)
Unit
Min
Typ
Max
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
ns
WFRST SR P
RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P
RESET input not filtered
pulse
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
Weak pull-up current
|IWPU| CC P
absolute value
VDD = 5.0 V ± 10%, PAD3V5V =
1(4)
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the
device reference manual).
3. CL includes device and package capacitance (CPKG < 5 pF).
4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET are
configured in input or in high impedance state.
4.9
Power management electrical characteristics
4.9.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the
common I/O supply VDD. The following supplies are involved:
44/90
●
HV: High voltage external power supply for voltage regulator module. This must be
provided externally through VDD power pin.
●
BV: High voltage external power supply for internal ballast module. This must be
provided externally through VDD_BV power pin. Voltage values should be aligned with
VDD.
●
LV: Low voltage internal power supply for core, FMPLL and flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
–
LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
–
LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
–
LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
–
LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
CREG2 (LV_COR/LV_CFLA)
VDD
VSS_LV
VDD_BV
Voltage Regulator
I
VSS_LVn
VDD_BV
CREG1 (LV_COR/LV_DFLA)
VDD_LVn
CDEC1 (Ballast decoupling)
VREF
VDD_LV
VDD_LV
VSS_LV
VSS_LV
DEVICE
DEVICE
VDD_LV
CREG3
(LV_COR/LV_PLL)
Figure 7.
VSS
VDD
CDEC2
(supply/IO decoupling)
Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the
device in order to provide a stable low voltage digital supply to the device. Capacitances
should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply
pairs to ensure stable voltage (see Section 4.5, Recommended operating conditions).
Doc ID 16315 Rev 7
45/90
Electrical characteristics
Table 24.
SPC560D30x, SPC56040Dx
Voltage regulator electrical characteristics
Symbol
C
CREGn
SR —
Internal voltage regulator external
capacitance
RREG
SR —
Stability capacitor equivalent serial
resistance
CDEC1
SR — Decoupling
CDEC2
SR —
VMREG
CC
IMREG
SR —
capacitance(2)
ballast
Decoupling capacitance regulator
supply
T
—
Range:
10 kHz to 20 MHz
VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to 5.5 V
Unit
Min
Typ
Max
200
—
500
nF
—
—
0.2

100(3)
—
470(4)
nF
VDD_BV/VSS_LV pair:
VDD_BV = 3 V to 3.6 V
400
VDD/VSS pair
10
100
—
Before exiting from reset
—
1.32
—
1.16
1.28
—
—
—
150
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
After trimming
1.16
1.28
—
V
—
—
15
mA
ILPREG = 15 mA;
TA = 55 °C
—
—
600
ILPREG = 0 mA;
TA = 55 °C
—
5
—
After trimming
1.16
1.28
—
V
—
—
5
mA
IULPREG = 5 mA;
TA = 55 °C
—
—
100
IULPREG = 0 mA;
TA = 55 °C
—
2
—
—
—
300(6)
—
nF
Main regulator output voltage
P
IMREGINT CC D
Main regulator current provided to
VDD_LV domain
Main regulator module current
consumption
CC P Low-power regulator output voltage
ILPREG
SR —
Low-power regulator module current
consumption
—
VULPREG CC P
Ultra low power regulator output
voltage
IULPREG
Ultra low power regulator current
provided to VDD_LV domain
SR —
Ultra low power regulator module
IULPREGINT CC D
current consumption
CC D
—
Low power regulator current provided
to VDD_LV domain
D
ILPREGINT CC
V
After trimming
VLPREG
IDD_BV
Value
Conditions(1)
Parameter
—
—
In-rush average current on VDD_BV
during power-up(5)
—
mA
mA
µA
µA
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V.
4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in
operating range.
5. In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs, depending on
external capacitances to be loaded).
46/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
4.9.2
Low voltage detector electrical characteristics
The device implements a power-on reset (POR) module to ensure correct power-up
initialization, as well as five low voltage detectors (LVDs) to monitor the VDD and the VDD_LV
voltage while device is supplied:
●
POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR
in device reference manual)
●
LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer
to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device
reference manual)
●
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
(refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in
device reference manual)
●
LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to
RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference
manual)
●
LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD1 in device reference manual)
●
LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)
VDD
VLVDHVxH
VLVDHVxL
RESET
Figure 8.
Low voltage detector vs reset
Doc ID 16315 Rev 7
47/90
Electrical characteristics
Table 25.
SPC560D30x, SPC56040Dx
Low voltage detector electrical characteristics
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
VPORUP
SR P Supply for functional POR module
1.0
—
5.5
V
VPORH
CC P Power-on reset threshold
1.5
—
2.6
V
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
—
2.95
V
VLVDHV3L
CC P LVDHV3 low voltage detector low threshold
2.6
—
2.9
V
—
—
2.95
V
2.6
—
2.9
V
VLVDHV3BH CC P LVDHV3B low voltage detector high threshold
TA = 25 °C,
after trimming
VLVDHV3BL CC P LVDHV3B low voltage detector low threshold
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
—
4.5
V
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
—
4.4
V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1.08
—
1.16
V
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1.08
—
1.16
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.10
Power consumption
Table 26 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.
Table 26.
Power consumption on VDD_BV and VDD_HV
Symbol
IDDMAX(2)
IDDRUN(4)
C
CC D
CC
IDDSTOP
RUN mode maximum
average current
Unit
—
Min
Typ
—
90
Max
130(3) mA
fCPU = 8 MHz
—
7
—
T RUN mode typical
(5)
T average current
fCPU = 16 MHz
—
18
—
fCPU = 32 MHz
—
29
—
P
fCPU = 48 MHz
—
40
100
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
TA = 125 °C
—
8
15
—
14
25
CC
HALT mode current(6)
P
mA
mA
P
TA = 25 °C
—
180
700(8)
D
TA = 55 °C
—
500
—
—
1
6(8)
—
2
9(8)
4.5
12(8)
CC D STOP mode current(7)
D
Slow internal RC oscillator
TA = 85 °C
(128 kHz) running
TA = 105 °C
P
48/90
Value
Conditions(1)
T
C
IDDHALT
Parameter
TA = 125 °C
Doc ID 16315 Rev 7
µA
—
mA
SPC560D30x, SPC56040Dx
Table 26.
Symbol
Electrical characteristics
Power consumption on VDD_BV and VDD_HV (continued)
C
Unit
Min
Typ
Max
—
30
100
—
75
—
TA = 25 °C
P
—
180
700
D
TA = 55 °C
internal RC oscillator
TA = 85 °C
(128 kHz) running
TA = 105 °C
—
315
1000
P
TA = 125 °C
—
560
1700
D
IDDSTDBY
Value
Conditions(1)
Parameter
(9) Slow
CC D STANDBY mode current
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is
thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation
ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals
(default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power
mode when possible.
3. Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush average current on
Table 24.
4. RUN current measured with typical application with accesses on both flash memory and SRAM.
5. Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master, PLL
as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency, periodic SW/WDG
timer reset enabled.
6. Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock. FlexCAN: 0
ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission),
instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz,
instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but
no conversion except 2 analog watchdogs.
7. Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off, ULPVreg/LPVreg on.
All possible peripherals off and clock gated. Flash in power down mode.
8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator
module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures
exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP
specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and
the main regulator will be automatically switched off when the load current is below 6 mA.
9. Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum consumption,
all possible modules switched off.
4.11
Flash memory electrical characteristics
The data flash operation depends strongly on the code flash operation. If code flash is
switched-off, the data flash is disabled.
4.11.1
Program/Erase characteristics
Table 27 shows the program and erase characteristics.
Table 27.
Program and erase specifications (code flash)
Value
Symbol
C
Parameter
Min
Typ(1)
Initial
max(2)
Max(3)
Unit
tdwprogram
CC C Double word (64 bits) program time(4)
—
22
50
500
µs
t16Kpperase
CC C 16 KB block preprogram and erase time
—
300
500
5000
ms
Doc ID 16315 Rev 7
49/90
Electrical characteristics
Table 27.
SPC560D30x, SPC56040Dx
Program and erase specifications (code flash)
Value
Symbol
t32Kpperase
C
Parameter
Typ(1)
Initial
max(2)
Max(3)
—
400
600
5000
ms
—
800
1300
7500
ms
—
—
30
30
µs
CC C 32 KB block preprogram and erase time
t128Kpperase CC C 128 KB block preprogram and erase time
CC C Erase suspend latency
tesus
Unit
Min
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
Table 28.
Program and erase specifications (data flash)
Value
Symbol
C
Parameter
Unit
Min
Typ(1)
Initial
max(2)
Max(3)
—
30
70
300
µs
t16Kpperase CC C 16 KB block preprogram and erase time
—
700
800
1500
ms
CC C 64 KB block preprogram and erase time
—
1900
2300
4800
ms
tswprogram
tBank_D
CC C Single word (32 bits) program time(4)
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
Table 29.
Flash module life
Value
Symbol
P/E
C
Parameter
Number of program/erase
cycles per block over the
CC C
operating temperature range
(TJ)
Minimum data retention at 85
Retention CC C °C average ambient
temperature(1)
Conditions
Unit
Min
Typ
Max
16 KB blocks
100000
—
—
cycles
32 KB blocks
10000
100000
—
cycles
128 KB blocks
1000
100000
—
cycles
Blocks with
0–1000 P/E cycles
20
—
—
Blocks with
1001–10000 P/E cycles
10
—
—
Blocks with
10001–100000 P/E cycles
5
—
—
1. Ambient temperature averaged over application duration. It is recommended not to exceed the product operating
temperature range.
50/90
Doc ID 16315 Rev 7
years
SPC560D30x, SPC56040Dx
Electrical characteristics
ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.
Table 30.
Symbol
fCFREAD CC
Flash memory read access timing
C
Conditions
Parameter
(1)
P Maximum working frequency for reading code flash memory at given
C number of wait states in worst conditions
fDFREAD CC P
Maximum working frequency for reading data flash memory at given
number of wait states in worst conditions
Max Unit
2 wait states
48
0 wait states
20
6 wait states
48
MHz
MHz
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.11.2
Flash power supply DC characteristics
Table 31 shows the power supply DC characteristics on external supply.
Note:
Power supply for data flash is actually provided by code flash; this means that data flash
cannot work if code flash is not powered.
Table 31.
Flash power supply DC electrical characteristics
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
Code flash
—
—
33
mA
Data flash
—
—
4
mA
Program/Erase on-going
Code flash
while reading flash registers,
Data flash
fCPU = 48 MHz
—
—
33
mA
—
—
6
mA
Code flash
—
— 910 µA
Code flash
—
— 125 µA
Data flash
—
—
ICFREAD CC D Sum of the current consumption on Flash module read
IDFREAD CC D VDDHV and VDDBV on read access fCPU = 48 MHz
ICFMOD CC D Sum of the current consumption on
VDDHV and VDDBV on matrix
IDFMOD CC D modification (program/erase)
Sum of the current consumption on
CC D VDDHV and VDDBV during
flash low-power mode
—
ICFPWD CC D Sum of the current consumption on
VDDHV and VDDBV during
IDFPWD CC D flash power-down mode
—
IFLPW
25
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.11.3
Start-up/Switch-off timings
Table 32.
Start-up time/Switch-off time
Symbol
tFLARSTEXIT
C
C
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
Code flash
—
—
125
µs
Data flash
—
—
150
µs
T Delay for flash module to exit reset mode
Doc ID 16315 Rev 7
51/90
Electrical characteristics
Table 32.
SPC560D30x, SPC56040Dx
Start-up time/Switch-off time (continued)
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
tFLALPEXIT
C
C
T
Delay for flash module to exit low-power
mode(2)
Code flash
—
—
0.5
µs
C
C
—
30
µs
T
Delay for flash module to exit power-down Code flash
mode
Data flash
—
tFLAPDEXIT
—
—
30(3)
µs
tFLALPENTRY
C
C
T
Delay for flash module to enter low-power
Code flash
mode
—
—
0.5
µs
C
C
—
—
1.5
µs
T
Delay for flash module to enter powerdown mode
Code flash
tFLAPDENTRY
—
4(3)
µs
Data flash
—
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. Data flash does not support low-power mode
3. If code flash is already switched-on.
4.12
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
●
●
Software recommendations The software flowchart must include the management of
runaway conditions such as:
–
Corrupted program counter
–
Unexpected reset
–
Critical data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see the application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).
4.12.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI
measurements.
52/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
EMI radiated emission measurement(1)(2)
Table 33.
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
—
0.150
—
fCPU SR — Operating frequency
—
—
48
—
MHz
VDD_LV SR — LV operating voltages
—
—
1.28
—
V
—
—
18 dBµV
—
—
14 dBµV
—
SR — Scan range
SEMI CC T Peak level
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
LQFP100 package
Test conforming to IEC 61967-2, ± 2% PLL frequency
fOSC = 8 MHz/fCPU = 48 MHz
modulation
Max
1000 MHz
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.
4.12.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
Table 34.
Symbol
ESD absolute maximum ratings(1) (2)
C
Ratings
Conditions
Class
Max value
Unit
VESD(HBM)
C
Electrostatic discharge voltage
T
C
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM)
C
Electrostatic discharge voltage
T
C
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
C
Electrostatic discharge voltage
T
C
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
500
V
VESD(CDM)
C3A
750 (corners)
V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
Doc ID 16315 Rev 7
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Electrical characteristics
SPC560D30x, SPC56040Dx
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin.
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 35.
Symbol
LU
54/90
CC
Latch-up results
C
Parameter
Conditions
T Static latch-up class
TA = 125 °C
conforming to JESD 78
Doc ID 16315 Rev 7
Class
II level A
SPC560D30x, SPC56040Dx
4.13
Electrical characteristics
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the
internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 36 provides the parameter description of 4 MHz to 16 MHz crystals used for the
design simulations.
EXTAL
C1
Crystal
EXTAL
XTAL
C2
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Figure 9.
Crystal oscillator and resonator connection scheme
Doc ID 16315 Rev 7
55/90
Electrical characteristics
Table 36.
SPC560D30x, SPC56040Dx
Crystal description
Crystal
equivalent
series
resistance
Crystal
motional
capacitance
Crystal
motional
inductance
(ESR) 
(Cm) fF
(Lm) mH
300
2.68
591.0
21
2.93
8
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
120
3.11
56.5
15
2.93
120
3.90
25.3
10
3.00
Nominal
frequency
NDK crystal
(MHz)
4
12
reference
NX8045GB
NX5032GA
16
Shunt
capacitance
Load on
xtalin/xtalout between xtalout
and xtalin
C1 = C2 (pF)(1)
C0(2) (pF)
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).
S_MTRANS bit (ME_GS register)
‘1’
‘0’
VXTAL
1/fFXOSC
VFXOSC
90%
VFXOSCOP
10%
TFXOSCSU
valid internal clock
Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram
Table 37.
Symbol
fFXOSC
56/90
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
C
SR —
Parameter
Fast external crystal
oscillator frequency
Value
Conditions(1)
—
Doc ID 16315 Rev 7
Unit
Min
Typ
Max
4.0
—
16.0
MHz
SPC560D30x, SPC56040Dx
Table 37.
Symbol
gmFXOSC
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
CC C
VDD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
—
8.2
CC P
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
2.0
—
7.4
Fast external crystal
oscillator transconductance V = 3.3 V ± 10%,
DD
CC C
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
CC C
VFXOSC
Electrical characteristics
CC T
Oscillation amplitude at
EXTAL
VFXOSCOP CC P Oscillation operating point
Fast external crystal
oscillator consumption
IFXOSC(2)
CC T
tFXOSCSU
Fast external crystal
CC T
oscillator start-up time
mA/V
2.7
—
9.7
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
2.5
—
9.2
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
—
—
V
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.3
—
—
—
0.95
—
—
2
3
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
—
V
mA
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
VIH
SR P
Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
—
VDD+0.4
V
VIL
SR P
Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.4
—
0.35VDD
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals)
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Electrical characteristics
4.14
SPC560D30x, SPC56040Dx
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.
Table 38.
Symbol
FMPLL electrical characteristics
C
Typ
Max
—
4
—
48
MHz
—
40
—
60
%
—
16
—
48
MHz
VCO frequency without
frequency modulation
—
256
—
512
VCO frequency with frequency
modulation
—
245
—
533
SR — FMPLL reference clock(2)
PLLIN
SR —
FMPLL reference clock duty
cycle(2)
fPLLOUT CC D FMPLL output clock frequency
fVCO
Unit
Min
fPLLIN
(3)
Value
Conditions(1)
Parameter
CC P
MHz
fCPU
SR — System clock frequency
—
—
—
48
MHz
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
Stable oscillator (fPLLIN = 16 MHz)
—
40
100
µs
fPLLIN = 16 MHz (resonator),
fPLLCLK at 48 MHz, 4000 cycles
—
—
10
ns
TA = 25 °C
—
—
4
mA
tLTJIT CC — FMPLL long term jitter
IPLL
CC C FMPLL consumption
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
3. Frequency modulation is considered ±4%.
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator (FIRC). This is used as the default
clock at the power-up of the device.
Table 39.
Symbol
fFIRC
Fast internal RC oscillator (16 MHz) electrical characteristics
C
Parameter
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
SR — frequency
—
Fast internal RC oscillator high
TA = 25 °C, trimmed
IFIRCRUN(2) CC T frequency current in running
mode
58/90
Value
Conditions(1)
Doc ID 16315 Rev 7
Unit
Min
Typ
Max
—
16
—
MHz
12
—
20
—
200
µA
SPC560D30x, SPC56040Dx
Table 39.
Symbol
IFIRCPWD
Electrical characteristics
Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
C
FIRCPRE
CC C
Typ
Max
—
—
10
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
—
1.1
2.0
µs
1
%
Fast internal RC oscillator startVDD = 5.0 V ± 10%
up time
Fast internal RC oscillator
CC C precision after software
trimming of fFIRC
TA = 25 °C
1
—
Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
5
—
FIRCTRIM CC C
FIRCVAR
Unit
Min
Fast internal RC oscillator high
CC D frequency current in power
TA = 25 °C
down mode
Fast internal RC oscillator high
IFIRCSTOP CC T frequency and system clock
TA = 25 °C
current in stop mode
tFIRCSU
Value
Conditions(1)
Parameter
Fast internal RC oscillator
variation in temperature and
CC C supply with respect to fFIRC at
TA = 55 °C in high-frequency
configuration
—
µA
µA
%
5
%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.16
Slow internal RC oscillator (128 kHz) electrical
characteristics
The device provides a 128 kHz slow internal RC oscillator (SIRC). This can be used as the
reference clock for the RTC module.
Table 40.
Symbol
fSIRC
Slow internal RC oscillator (128 kHz) electrical characteristics
C
Value
Conditions(1)
Parameter
CC P Slow internal RC oscillator low
SR — frequency
TA = 25 °C, trimmed
—
ISIRC(2)
CC C
Slow internal RC oscillator low
frequency current
tSIRCSU
CC P
Slow internal RC oscillator start-up
TA = 25 °C, VDD = 5.0 V ± 10%
time
TA = 25 °C, trimmed
Doc ID 16315 Rev 7
Unit
Min
Typ
Max
—
128
—
100
—
150
—
—
5
µA
—
8
12
µs
kHz
59/90
Electrical characteristics
Table 40.
Symbol
SPC560D30x, SPC56040Dx
Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
C
Value
Conditions(1)
Parameter
Slow internal RC oscillator precision
TA = 25 °C
after software trimming of fSIRC
SIRCPRE
CC C
SIRCTRIM
Slow internal RC oscillator trimming
CC C
step
SIRCVAR
Slow internal RC oscillator variation
in temperature and supply with
CC P
High frequency configuration
respect to fSIRC at TA = 55 °C in high
frequency configuration
Unit
Min
Typ
Max
2
—
2
%
—
—
2.7
—
10
—
10
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
60/90
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%
SPC560D30x, SPC56040Dx
Electrical characteristics
4.17
ADC electrical characteristics
4.17.1
Introduction
The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital
converter.
Offset Error (EO)
Gain Error (EG)
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(5)
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error (EO)
Figure 11. ADC characteristics and error definitions
Doc ID 16315 Rev 7
61/90
Electrical characteristics
4.17.2
SPC560D30x, SPC56040Dx
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is
considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a
frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to
ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a
resistance of 330 k is obtained (REQ = 1 / (fc × (CS+Cp2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF,
the external circuit must be designed to respect the Equation 4:
Equation 4
R +R
VA
S
F
 ---------------------  1--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on a resistive
path.
62/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RL
CF
VA
CP1
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
Figure 12.
Input equivalent circuit (precise channels)
Doc ID 16315 Rev 7
63/90
Electrical characteristics
SPC560D30x, SPC56040Dx
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
RF
Current Limiter
RL
CF
VA
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
Figure 13. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit in Figure 13): A charge sharing phenomenon is installed when the
sampling phase is started (A/D switch close).
Voltage transient on CS
VCS
VA
VA2
V <0.5 LSB
1
2
1 < (RSW + RAD) CS << ts
2 = RL (CS + CP1 + CP2)
VA1
ts
t
Figure 14. Transient behavior during sampling phase
64/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
In particular two different transient periods can be distinguished:
1.
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
 = R
+R

1
SW
AD
CP  CS
 ---------------------CP + CS
Equation 5 can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time ts is always much
longer than the internal time constant:
Equation 6
 1   R SW + R AD   C S « t s
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:
Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 
2.
A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
Equation 8
 2  R L   C S + C P1 + C P2 
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time ts, a constraints on
RL sizing is obtained:
Equation 9
10   2 = 10  R L   C S + C P1 + C P2   t s
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):
Doc ID 16315 Rev 7
65/90
Electrical characteristics
SPC560D30x, SPC56040Dx
Equation 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (ts). The filter is typically designed to act as anti-aliasing.
Analog source bandwidth (VA)
tc < 2 RFCF (conversion rate vs. filter pole)
Noise
fF = f0 (anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
fF
Sampled signal spectrum (fC = conversion rate)
f0
f
fC
f
Figure 15. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (tc). Again the conversion period tc is longer than the sampling time ts,
which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time ts, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
Equation 11
V A2
C P1 + C P2 + C F
------------ = ------------------------------------------------------VA
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
66/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
Equation 12
C F  2048  C S
4.17.3
ADC electrical characteristics
Table 41.
ADC input leakage current
Value
Symbol C
Parameter
Unit
Min
Typ
Max
—
1
—
—
1
—
TA = 40 °C
C
C
ILKG CC
Conditions
Input leakage current
TA = 25 °C
No current injection on adjacent pin
nA
C
TA = 105 °C
—
8
200
P
TA = 125 °C
—
45
400
Table 42.
ADC conversion characteristics
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
Voltage on
VSS_HV_ADC (ADC
VSS_ADC SR — reference) pin with
respect to ground
(VSS)(2)
—
0.1
—
0.1
V
Voltage on
VDD_HV_ADC pin
VDD_ADC SR — (ADC reference) with
respect to ground
(VSS)
—
VDD  0.1
—
VDD + 0.1
V
—
VSS_ADC  0.1
—
VDD = 5.0 V
3.33
—
32 + 4%
VDD = 3.3 V
3.33
—
20 + 4%
45
—
55
%
—
—
1.5
µs
600
—
—
ns
—
—
76.2
µs
500
—
—
ns
—
—
76.2
µs
VAINx
SR — Analog input voltage(3)
fADC
SR — ADC analog frequency
ADC_SYS SR —
MHz
ADC clock duty cycle
ADCLKSEL = 1(4)
(ipg_clk)
tADC_PU SR — ADC power up delay
CC
Sampling time(5)
T
VDD = 3.3 V
ts
Sampling time(5)
T
VDD = 5.0 V
VDD_ADC + 0.1 V
—
fADC = 20 MHz,
INPSAMP = 12
fADC = 3.33 MHz,
INPSAMP = 255
fADC = 24 MHz,
INPSAMP = 13
fADC = 3.33 MHz,
INPSAMP = 255
Doc ID 16315 Rev 7
67/90
Electrical characteristics
Table 42.
SPC560D30x, SPC56040Dx
ADC conversion characteristics (continued)
Symbol
C
Parameter
(6)
P
tc
Conversion time
VDD = 3.3 V
Value
Conditions(1)
fADC = 20 MHz,
INPCMP = 0
Unit
Min
Typ
Max
2.4
—
—
µs
fADC = 13.33 MHz,
INPCMP = 0
—
—
3.6
fADC = 32 MHz,
INPCMP = 0
1.5
—
—
CC
(6)
P
Conversion time
VDD = 5.0 V
µs
fADC = 13.33 MHz,
INPCMP = 0
—
—
3.6
CS
CC D
ADC input sampling
capacitance
—
5
pF
CP1
CC D
ADC input pin
capacitance 1
—
3
pF
CP2
CC D
ADC input pin
capacitance 2
—
1
pF
CP3
CC D
ADC input pin
capacitance 3
—
1.5
pF
RSW1
CC D
Internal resistance of
analog source
—
—
—
1
k
RSW2
CC D
Internal resistance of
analog source
—
—
—
2
k
RAD
CC D
Internal resistance of
analog source
—
—
—
0.3
k
5
—
5
IINJ
Current
injection on
one ADC input,
SR — Input current Injection
different from
the converted
one
VDD =
3.3 V ± 10%
mA
VDD =
5.0 V ± 10%
5
—
5
INLP
Absolute Integral nonCC T linearity-precise
No overload
channels
—
1
3
LSB
INLX
Absolute Integral nonCC T linearity-extended
No overload
channels
—
1.5
5
LSB
DNL
CC T
—
0.5
1
LSB
Absolute Differential
non-linearity
No overload
EO
CC T Absolute Offset error
—
—
2
—
LSB
EG
CC T Absolute Gain error
—
—
2
—
LSB
TUEP(7) CC
68/90
P Total unadjusted error Without current injection
for precise channels,
T input only pins
With current injection
Doc ID 16315 Rev 7
–6
6
–8
8
LSB
SPC560D30x, SPC56040Dx
Table 42.
Electrical characteristics
ADC conversion characteristics (continued)
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min
T Total unadjusted error Without current injection
T for extended channel With current injection
TUEX(7) CC
Typ
Max
–10
10
–12
12
LSB
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0xFFF.
4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
5. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the
sampling time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock
tS depend on programming.
6. This parameter does not include the sampling time tS, but only the time for determining the digital result and the time to load
the result’s register with the conversion result.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4.18
On-chip peripherals
4.18.1
Current consumption
Table 43.
On-chip peripherals current consumption(1)
Symbol
IDD_BV(CAN)
IDD_BV(eMIOS)
IDD_BV(SCI)
C
Parameter
Conditions
500 Kbyte/s Total (static + dynamic)
consumption:
– FlexCAN in loop-back
mode
CAN (FlexCAN) supply
CC T
current on VDD_BV
125 Kbyte/s – XTAL at 8 MHz used as
CAN engine clock source
– Message sending period
is 580 µs
CC T
CC T
eMIOS supply current
on VDD_BV
SCI (LINFlex) supply
current on VDD_BV
Static consumption:
– eMIOS channel OFF
– Global prescaler enabled
Dynamic consumption:
– It does not change varying the
frequency (0.003 mA)
Total (static + dynamic) consumption:
– LIN mode
– Baudrate: 20 Kbyte/s
Doc ID 16315 Rev 7
Typical value(2) Unit
8 × fperiph + 85
µA
8 × fperiph + 27
µA
29 × fperiph
µA
3
µA
5 × fperiph + 31
µA
69/90
Electrical characteristics
Table 43.
SPC560D30x, SPC56040Dx
On-chip peripherals current consumption(1) (continued)
Symbol
IDD_BV(SPI)
C
Parameter
Typical value(2) Unit
Conditions
SPI (DSPI) supply
CC T
current on VDD_BV
Ballast static consumption (only clocked)
1
µA
Ballast dynamic consumption (continuous
communication):
– Baudrate: 2 Mbit/s
– Transmission every 8 µs
– Frame: 16 bits
16 × fperiph
µA
41 × fperiph
µA
5 × fperiph
µA
2 × fperiph
µA
75 × fperiph + 32
µA
Ballast static consumption
(no conversion)
IDD_BV(ADC)
CC T
ADC supply current on
VDD_BV
VDD = 5.5 V Ballast dynamic
consumption (continuous
conversion)(3)
Analog static consumption
(no conversion)
IDD_HV_ADC(ADC) CC T
ADC supply current on
VDD_HV_ADC
VDD = 5.5 V Analog dynamic
consumption (continuous
conversion)
IDD_HV(FLASH)
CC T
CFlash + DFlash supply
VDD = 5.5 V
current on VDD_HV
—
8.21
mA
IDD_HV(PLL)
CC T
PLL supply current on
VDD_HV
—
30 × fperiph
µA
VDD = 5.5 V
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 48 MHz
2. fperiph is an absolute value.
3. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,
(41 + 5) × fperiph.
4.18.2
DSPI characteristics
Table 44.
DSPI characteristics(1)
DSPI0/DSPI1
No.
1
—
70/90
Symbol
tSCK
fDSPI
C
Unit
Min
Typ
Max
D
Master mode
(MTFE = 0)
125
—
—
D
Slave mode
(MTFE = 0)
125
—
—
SR
SR
Parameter
SCK cycle time
ns
D
Master mode
(MTFE = 1)
83
—
—
D
Slave mode
(MTFE = 1)
83
—
—
—
—
fCPU
D DSPI digital controller frequency
Doc ID 16315 Rev 7
MHz
SPC560D30x, SPC56040Dx
Electrical characteristics
DSPI characteristics(1) (continued)
Table 44.
DSPI0/DSPI1
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
tCSC
Internal delay between pad
associated to SCK and pad
CC D
associated to CSn in master
mode
Master mode
—
—
130(2)
ns
—
tASC
Internal delay between pad
associated to SCK and pad
CC D
associated to CSn in master
mode for CSn11
Master mode
—
—
130(2)
ns
2
tCSCext(3)
SR
D CS to SCK delay
Slave mode
32
—
—
ns
3
tASCext(4)
SR
D After SCK delay
Slave mode
1/fDSPI + 5
—
—
ns
Master mode
—
tSDC
tSCK/2
—
4
Slave mode
tSCK/2
—
—
—
CC D
SCK duty cycle
SR
D
ns
5
tA
SR
D Slave access time
—
1/fDSPI + 70
—
—
ns
6
tDI
SR
D Slave SOUT disable time
—
7
—
—
ns
7
tPCSC
SR
D PCSx to PCSS time
—
0
—
—
ns
8
tPASC
SR
D PCSS to PCSx time
—
0
—
—
ns
Master mode
43
—
—
9
tSUI
SR
D Data setup time for inputs
Slave mode
5
—
—
Master mode
0
—
—
tHI
SR
Slave mode
2(5)
—
—
Master mode
—
—
32
Slave mode
—
—
52
Master mode
0
—
—
Slave mode
8
—
—
10
11
12
ns
D Data hold time for inputs
tSUO(6)
CC D Data valid after SCK edge
tHO(6)
CC D Data hold time for outputs
ns
ns
ns
1. Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns
2. Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad
3. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext.
4. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext.
5. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR.
6. SCK and SOUT configured as MEDIUM pad
Doc ID 16315 Rev 7
71/90
Electrical characteristics
SPC560D30x, SPC56040Dx
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 44.
Figure 16. DSPI classic SPI timing – master, CPHA = 0
72/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Note: Numbers shown reference Table 44.
Figure 17. DSPI classic SPI timing – master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 44.
Figure 18. DSPI classic SPI timing – slave, CPHA = 0
Doc ID 16315 Rev 7
73/90
Electrical characteristics
SPC560D30x, SPC56040Dx
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Note: Numbers shown reference Table 44.
Figure 19. DSPI classic SPI timing – slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Note: Numbers shown reference Table 44.
Figure 20. DSPI modified transfer format timing – master, CPHA = 0
74/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Note: Numbers shown reference Table 44.
Figure 21. DSPI modified transfer format timing – master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Note: Numbers shown reference Table 44.
Figure 22. DSPI modified transfer format timing – slave, CPHA = 0
Doc ID 16315 Rev 7
75/90
Electrical characteristics
SPC560D30x, SPC56040Dx
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Note: Numbers shown reference Table 44.
Figure 23. DSPI modified transfer format timing – slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 44.
Figure 24. DSPI PCS strobe (PCSS) timing
76/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Electrical characteristics
4.18.3
JTAG characteristics
Table 45.
JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
83.33
—
—
ns
2
tTDIS
CC
D TDI setup time
15
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
15
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
—
49
ns
7
tTDOI
CC
D TCK low to TDO invalid
6
—
—
ns
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 45.
Figure 25. Timing diagram – JTAG boundary scan
Doc ID 16315 Rev 7
77/90
Package characteristics
SPC560D30x, SPC56040Dx
5
Package characteristics
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
Package mechanical data
5.2.1
LQFP100
Figure 26. LQFP100 mechanical drawing
78/90
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 46.
Package characteristics
LQFP100 mechanical data
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.000
—
—
0.4724
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.000
—
—
0.4724
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0 °
3.5 °
7.0 °
0.0 °
3.5 °
7.0 °
Tolerance
mm
inches
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16315 Rev 7
79/90
Package characteristics
5.2.2
SPC560D30x, SPC56040Dx
LQFP64
D
ccc C
D1
A
A2
D3
33
48
32
49
b
L1
E3 E1 E
L
A1
K
64
17
Pin 1
identification
16
1
c
5W_ME
Figure 27. LQFP64 mechanical drawing
Table 47.
LQFP64 mechanical data
inches(1)
mm
Symbol
80/90
Min
Typ
Max
Min
Typ
Max
A
—
—
1.6
—
—
0.0630
A1
0.05
—
0.15
0.0020
—
0.0059
A2
1.35
1.4
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
—
0.2
0.0035
—
0.0079
D
11.8
12
12.2
0.4646
0.4724
0.4803
D1
9.8
10
10.2
0.3858
0.3937
0.4016
D3
—
7.5
—
—
0.2953
—
E
11.8
12
12.2
0.4646
0.4724
0.4803
E1
9.8
10
10.2
0.3858
0.3937
0.4016
E3
—
7.5
—
—
0.2953
—
e
—
0.5
—
—
0.0197
—
L
0.45
0.6
0.75
0.0177
0.0236
0.0295
L1
—
1
—
—
0.0394
—
Doc ID 16315 Rev 7
SPC560D30x, SPC56040Dx
Table 47.
Package characteristics
LQFP64 mechanical data (continued)
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
—
—
0.08
—
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16315 Rev 7
81/90
Ordering information
SPC560D30x, SPC56040Dx
6
Ordering information
Table 48.
Order codes
Memory
Order code
CPU
Code flash /
SRAM (KB)
Package
Data flash
(°C)
(MHz)
Voltage
Packing
40 to 105
SPC560D30L1B3E0X
e200z0h
128 / 12
4 x 16 KB
LQFP64
e200z0h
128 / 12
4 x 16 KB
LQFP64
e200z0h
128 / 12
4 x 16 KB
LQFP64
e200z0h
128 / 12
4 x 16 KB
LQFP64
e200z0h
256 / 16
4 x 16 KB
LQFP100
e200z0h
256 / 16
4 x 16 KB
LQFP100
e200z0h
256 / 16
4 x 16 KB
LQFP100
e200z0h
256 / 16
4 x 16 KB
LQFP100
SPC560D30L1C3E0X
40 to 125
32
3.3 / 5 V Tape & Reel
48
3.3 / 5 V Tape & Reel
32
3.3 / 5 V Tape & Reel
48
3.3 / 5 V Tape & Reel
32
3.3 / 5 V Tape & Reel
48
3.3 / 5 V Tape & Reel
32
3.3 / 5 V Tape & Reel
48
3.3 / 5 V Tape & Reel
40 to 105
SPC560D30L1B4E0X
SPC560D30L1C4E0X
40 to 125
40 to 105
SPC560D30L1B3E0X
SPC560D30L1C3E0X
40 to 125
40 to 105
SPC560D30L1B4E0X
SPC560D30L1C4E0X
40 to 125
40 to 105
SPC560D40L3B3E0X
SPC560D40L3C3E0X
40 to 125
40 to 105
SPC560D40L3B4E0X
SPC560D40L3C4E0X
40 to 125
40 to 105
SPC560D40L3B3E0X
SPC560D40L3C3E0X
40 to 125
40 to 105
SPC560D40L3B4E0X
SPC560D40L3C4E0X
Table 49.
Op. temp. Speed
40 to 125
Order codes for engineering samples(1)
Memory
Order code
CPU
Code flash /
SRAM (KB)
Package
Data flash
SPC560D40L1-ENG
LQFP64
e200z0h
SPC560D40L3-ENG
256 / 16
4 x 16 KB
Op. temp. Speed
(°C)
(MHz)
40 to 125
48
Voltage
Packing
3.3 / 5 V Tape & Reel
LQFP100
1. Engineering samples are suitable only for evaluation and development purpose but NOT for qualification and production.
Their silicon version and maturity may vary until the product has reached qualification.
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SPC560D30x, SPC56040Dx
Ordering information
Example code:
SPC56
0
D
40
L3
C
4E0
Y
Product identifier Core Family Memory Package Temperature Custom version Packing
Y = Tray
X = Tape and Reel 90°
3E0 = 32 MHz EEPROM 5V/3V
4E0 = 48 MHz EEPROM 5V/3V
B = –40 to 105 °C
C = –40 to 125 °C
L1 = LQFP64
L3 = LQFP100
40 = 256 KB
30 = 128 KB
D = Access family
0 = e200z0h
SPC56 = Power Architecture in 90 nm
Figure 28. Commercial product code structure
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Ordering information
Appendix A
SPC560D30x, SPC56040Dx
Abbreviations
Table 50 lists abbreviations used in this document.
Table 50.
Abbreviations
Abbreviation
APU
Auxilliary processing unit
CMOS
Complementary metal–oxide–semiconductor
CPHA
Clock phase
CPOL
Clock polarity
CS
DAOC
Peripheral chip select
Double action output compare
ECC
Error code correction
EVTO
Event out
GPIO
General purpose input/output
IPM
IPWM
Input period measurement
Input pulse width measurement
MB
Message buffer
MC
Modulus counter
MCB
Modulus counter buffered (up / down)
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
NVUSRO
Non-volatile user options register
OPWFMB
Output pulse width and frequency modulation buffered
OPWMB
OPWMCB
OPWMT
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Meaning
Output pulse width modulation buffered
Center aligned output pulse width modulation buffered with dead time
Output pulse width modulation trigger
PWM
Pulse width modulation
SAIC
Single action input capture
SAOC
Single action output compare
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
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SPC560D30x, SPC56040Dx
Table 50.
Ordering information
Abbreviations (continued)
Abbreviation
Meaning
TDO
Test data output
TMS
Test mode select
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Revision history
SPC560D30x, SPC560D40x
Revision history
Table 51 summarizes revisions to this document.
Table 51.
Document revision history
Date
Revision
09-Jul-2009
1
Initial release.
2
Updated the following tables:
- Absolute maximum ratings
- Low voltage power domain electrical characteristics;
- On-chip peripherals current consumption
- DSPI characteristics;
- JTAG characteristics;
- ADC conversion characteristics;
Inserted a note on “Flash power supply DC characteristics” section.
18-Feb-2010
10-Aug-2010
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3
Changes
“Features” section: Updated information concerning eMIOS, ADC,
LINFlex, Nexus and low power capabilities
“Pictus 512K device comparison” table: updated the “Execution
speed” row
“Pictus 512K series block diagram” figure:
– updated max number of Crossbar Switches
– updated Legend
“Pictus 512K series block summary” table: added contents concernig
the eDMA block
“LQFP100 pin configuration (top view)” figure:
– removed alternate functions
– updated supply pins
“LQFP64 pin configuration (top view)” figure: removed alternate
functions
Added “Pin muxing” section
“NVUSRO register” section: Deleted “NVUSRO[WATCHDOG_EN]
field description“ section
“Recommended operating conditions (3.3 V)” table:
– TVDD: deleted min value
– In footnote No. 3, changed capacitance value between VDD_BV and
VSS_LV
“Recommended operating conditions (5.0 V)” table: deleted TVDD
min value
“LQFP thermal characteristics” table: changed RJC values
“I/O input DC electrical characteristics” table:
– WFI: updated max value
– WNFI: updated min value
“I/O consumption” table: removed IDYNSEG row
Added “I/O weight” table
“Program and erase specifications (Code Flash)” table: deleted
TBank_C row
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SPC560D30x, SPC560D40x
Table 51.
Revision history
Document revision history (continued)
Date
10-Aug-2010
Revision
3
(cont.)
Changes
Updated the following tables:
– “Voltage regulator electrical characteristics”
– “Low voltage monitor electrical characteristics”
– “Low voltage power domain electrical characteristics”
– “Start-up time/Switch-off time”
– “Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics”
– “FMPLL electrical characteristics”
– “Fast internal RC oscillator (16 MHz) electrical characteristics”
– “ADC conversion characteristics”
– “On-chip peripherals current consumption”
– “DSPI characteristics”
“DSPI characteristics” section: removed “DSPI PCS strobe (PCSS)
timing” figure
Updated “Order codes” table
Added “Order codes for engineering samples” table
Updated “Commercial product code structure” table
Formatting and editorial changes throughout
Device comparison table: for the “Total timer I/O eMIOS”, changed
“13 ch” to “14 ch”
16-Sep-2011
4
SPC560D30/SPC560D40 series block summary:
– added definition for “AUTOSAR” acronym
– changed “System watchdog timer” to “Software watchdog timer”
LQFP64 pin configuration (top view): changed pin 6 from VPP_TEST
to VSS_HV
Added section “Pad configuration during reset phases”
Added section “Voltage supply pins”
Added section “Pad types”
Added section “System pins”
Renamed and updated section “Functional ports” (was previously
section “Pin muxing”); update includes replacing all instances of
WKUP with WKPU (WKPU is the correct abbreviation for Wakeup
Unit)
Section “NVUSRO register”: edited content to separate configuration
into electrical parameters and digital functionality
Added section “NVUSRO[WATCHDOG_EN] field description”
Absolute maximum ratings: Removed “C” column from table
Replaced “TBD” with “—” in TVDD min value cell of 3.3 V and 5 V
recommended operating conditions tables
LQFP thermal characteristics: removed RJB single layer board
conditions; updated footnote 4
I/O input DC electrical characteristics: removed footnote “All values
need to be confirmed during device validation”; updated ILKG
characteristics
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Revision history
SPC560D30x, SPC560D40x
Table 51.
Document revision history (continued)
Date
16-Sep-2011
Revision
4
(cont.)
Changes
MEDIUM configuration output buffer electrical characteristics:
changed “IOH = 100 µA” to “IOL = 100 µA” in VOL conditions
I/O consumption: replaced instances of “Root medium square” with
“Root mean square”
Updated section “Voltage regulator electrical characteristics”
Section “Low voltage detector electrical characteristics”: changed
title (was “Voltage monitor electrical characteristics”); added a fifth
LVD (LVDHV3B); added event status flag names found in RGM
chapter of device reference manual to POR module and LVD
descriptions; replaced instances of “Low voltage monitor” with “Low
voltage detector”; deleted note referencing power domain No. 2 (this
domain is not present on the device); updated electrical
characteristics table
Updated and renamed section “Power consumption” (was previously
section “Low voltage domain power consumption”)
Program and erase specifications (code flash): updated symbols;
updated tesus values
Updated Flash memory read access timing
EMI radiated emission measurement: updated SEMI values
Updated FMPLL electrical characteristics
Crystal oscillator and resonator connection scheme: inserted
footnote about possibly requiring a series resistor
Fast internal RC oscillator (16 MHz) electrical characteristics:
updated tFIRCSU values
Section “Input impedance and ADC accuracy”: changed “VA/VA2” to
“VA2/VA” in Equation 13
ADC conversion characteristics:
– updated conditions for sampling time VDD = 5.0 V
– updated conditions for conversion time VDD = 5.0 V
Updated Abbreviations
Removed Order codes tables.
01-Dec-2011
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5
Replaced “TBD” with “8.21 mA” in IDD_HV(FLASH) cell of On-chip
peripherals current consumption table
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SPC560D30x, SPC560D40x
Table 51.
Revision history
Document revision history (continued)
Date
Revision
Changes
Removed all instances of table footnote “All values need to be
confirmed during device validation”
Section 4.1, Introduction, removed Caution note.
04-Feb-2013
6
17-Sep-2013
7
Table 11 (Recommended operating conditions (3.3 V)), added
minimum value of TVDD and footnote about it.
Table 12 (Recommended operating conditions (5.0 V)), added
minimum value of TVDD and footnote about it.
Updated Section 4.17.2, Input impedance and ADC accuracy
In Table 24, changed VLVDHV3L, VLVDHV3BL from 2.7 V to 2.6 V.
Revised the Table 28 (Flash module life)
Updated Table 43, DSPI characteristics, to add specifications 7 and
8, tPCSC and tPASC.
Inserted Figure 24, DSPI PCS strobe (PCSS) timing.
Updated Disclaimer.
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SPC560D30x, SPC56040Dx
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