Cypress CY7C024-55AXI 4k x 16/18 and 8k x 16/18 dual-port static ram with sem, int, busy Datasheet

CY7C024/0241
CY7C025/0251
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with SEM, INT, BUSY
Features
Functional Description
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 4K x 16 organization (CY7C024)
• 4K x 18 organization (CY7C0241)
• 8K x 16 organization (CY7C025)
• 8K x 18 organization (CY7C0251)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 150 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Available in 84-pin Lead (Pb)-free PLCC, 84-pin PLCC,
100-pin Lead (Pb)-free TQFP, and 100-pin TQFP
The CY7C024/0241 and CY7C025/0251 are low-power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs.
Various arbitration schemes are included on the CY7C024/
0241 and CY7C025/0251 to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C024/
0241 and CY7C025/0251 can be utilized as standalone
16-/18-bit dual-port static RAMs or multiple devices can be
combined in order to function as a 32-/36-bit or wider master/
slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt Flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a chip
select (CE) pin.
The CY7C024/0241 and CY7C025/0251 are available in
84-pin Lead (Pb)-free PLCCs, 84-pin PLCCs (CY7C024 and
CY7C025 only), 100-pin Lead (Pb)-free Thin Quad Plastic
Flatplack (TQFP) and 100-pin Thin Quad Plastic Flatpack.
Cypress Semiconductor Corporation
Document #: 38-06035 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 11, 2004
CY7C024/0241
CY7C025/0251
Logic Block Diagram
R/WR
UBR
L
L
LBR
L
CE
R
OE R
OE L
[3]
I/O 8L – I/O 15L
I/O 0L – I/O 7L
BUSYL
(CY7C025/0251)
I/O8R – I/O15R[3]
I/O
CONTROL
I/O
CONTROL
[2]
I/O 0R– I/O 7R [2]
[1]
[1]
BUSYR
A12R (CY7C025/0251)
A12L
A11L
MEMORY
ARRAY
ADDRESS
DECODER
A11R
ADDRESS
DECODER
A0L
A 0R
INTERRUPT
SEMAPHORE
ARBITRATION
CE L
OE L
CE R
OE R
UB R
LB R
UB L
LB L
R/W R
SEM R
R/W L
SEM L
INT L
M/S
INTR
Pin Configurations
9L
A
8L
A 10L
A
LB L
NC [4]
A11L
SEM L
CEL
UB L
R/WL
GND
I/O 1L
I/O 0L
OE L
V CC
I/O 2L
I/O 4L
I/O 3L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A10R
A 9R
A 8R
A 7R
NC [5]
A11R
GND
SEM R
CER
UB R
LB R
OE R
R/WR
GND
I/O15R
I/O13R
I/O 14R
I/O 11R
I/O 12R
I/O 9R
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
71
15
70
16
69
17
68
18
67
19
66
20
CY7C024/5
65
21
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O 10R
I/O8L
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O 5L
I/O 7L
I/O 6L
84-Pin PLCC
Top View
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. I/O0 –I/O8 on the CY7C0241/0251.
3. I/O9 –I/O17 on the CY7C0241/0251.
4. A12L on the CY7C025/0251.
5. A12R on the CY7C025/0251.
Document #: 38-06035 Rev. *C
Page 2 of 21
CY7C024/0241
CY7C025/0251
Pin Configurations (continued)
A7L
A6L
A9L
A8L
UBL
LBL
NC [4]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CY7C024/5
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
A7R
A6R
A5R
NC[5]
A11R
A10R
A9R
A8R
R/WR
GND
SEMR
CER
UBR
LBR
GND
I/O15R
ŒR
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O13R
I/O14R
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
A7L
A6L
A9L
A8L
UBL
LBL
NC [4]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Document #: 38-06035 Rev. *C
[
A7R
A6R
A5R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O9R
NC
NC
CY7C0241/0251
NC
A11R
A10R
A9R
A8R
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
GND
I/O16R
OER
R/WR
GND
SEMR
CER
UBR
LBR
NC
NC
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
I/O15L
I/O16L
Page 3 of 21
CY7C024/0241
CY7C025/0251
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A11/12L
A0R–A11/12R
Address
I/O0L–I/O15/17L
I/O0R–I/O15/17R
Data Bus Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
Selection Guide
7C024/0241–15
7C025/0251–15
7C024/0241–25
7C025/0251–25
7C024/0241–35
7C025/0251–35
7C024/0241–55
7C025/0251–55
Maximum Access Time (ns)
15
25
35
55
Typical Operating Current (mA)
190
170
160
150
Typical Standby Current for ISB1 (mA)
50
40
30
20
Architecture
The CY7C024/0241 and CY7C025/0251 consist of an array of
4K words of 16/18 bits each and 8K words of 16/18 bits each
of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C024/0241 and CY7C025/0251 can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/0241 and CY7C025/0251 have an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Document #: 38-06035 Rev. *C
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user of the CY7C024/0241 or
CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/0241, 1FFF for the CY7C025/0251) is the mailbox
for the right port and the second-highest memory location
(FFE for the CY7C024/0241, 1FFE for the CY7C025/0251) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the BUSY signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active BUSY to a port prevents that port from reading
its own mailbox and thus resetting the interrupt to it.
If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Page 4 of 21
CY7C024/0241
CY7C025/0251
Busy
The CY7C024/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic will
determine which port has access. If tPS is violated, one port
will definitely gain permission to the location, but which one is
not predictable. BUSY will be asserted tBLA after an address
match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA).
Otherwise, the slave chip may begin a write cycle during a
contention situation.When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C024/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports.The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch
by writing a zero to a semaphore location. The left port then
verifies its success in setting the latch by reading it. After
writing to the semaphore, SEM or OE must be deasserted for
tSOP before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the
left side will succeed in gaining control of the semaphore. If the
left side no longer requires the semaphore, a one is written to
cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within tSPS of each other, the
semaphore will definitely be obtained by one side or the other,
but there is no guarantee which side will control the
semaphore.
Table 1. Non-Contending Read/Write
Inputs
UB
Outputs
LB
SEM
I/O0–I/O7
[2]
I/O8–I/O15[3]
CE
R/W
OE
H
X
X
X
X
H
High Z
High Z
Deselected: Power-Down
X
X
X
H
H
H
High Z
High Z
Deselected: Power-Down
L
L
X
L
H
H
High Z
Data In
Write to Upper Byte Only
L
L
X
H
L
H
Data In
High Z
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
High Z
Data Out
Read Upper Byte Only
L
H
L
H
L
H
Data Out
High Z
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
Operation
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Document #: 38-06035 Rev. *C
Page 5 of 21
CY7C024/0241
CY7C025/0251
Table 2. Interrupt Operation Example (Assumes BUSYL=BUSYR=HIGH)[6]
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–11L
INTL
R/WR
CER
OER
A0R–11R
INTR
Set Right INTR Flag
L
L
X
(1)FFF
X
X
X
X
X
L[8]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
(1)FFF
H[7]
Set Left INTL Flag
X
X
X
X
L[7]
L
L
X
(1)FFE
X
[8]
X
X
X
X
X
Reset Left INTL Flag
X
L
L
(1)FFE
H
Table 3. Semaphore Operation Example
Function
I/O0–I/O15/17
Left
I/O0–I/O15/17
Right
Status
No action
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore.
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Notes:
6. A0L–12L and A0R–12R, 1FFF/1FFE for the CY7C025.
7. If BUSYR=L, then no change.
8. If BUSYL=L, then no change.
Document #: 38-06035 Rev. *C
Page 6 of 21
CY7C024/0241
CY7C025/0251
DC Input Voltage[10]........................................–0.5V to +7.0V
Maximum Ratings [9]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Commercial
Industrial
Electrical Characteristics Over the Operating Range
7C024/0241–15
7C025/0251–15
Parameter
Description
Test Conditions
Min. Typ.
Max. Min. Typ.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
–0.7
0.8
–10
–10
2.4
GND ≤ VI ≤ VCC
V
0.4
V
–0.7
0.8
V
+10
–10
+10
µA
+10
–10
+10
µA
mA
2.2
IIX
Input Leakage Current
Output Leakage Current Output Disabled,
GND ≤ VO ≤ VCC
ICC
Operating Current
ISB1
Standby Current
CEL and CER ≥ VIH,
(Both Ports TTL Levels) f = fMAX[11]
Ind
50
70
ISB2
Standby Current
(One Port TTL Level)
CEL or CER ≥ VIH,
f = fMAX[11]
Com’l
120
Ind
ISB3
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CER ≥
VCC – 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[11]
Com’l
Ind
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = fMAX[11]
ISB4
Max. Unit
2.4
0.4
IOZ
VCC = Max., IOUT = 0 mA,
Outputs Disabled
7C024/0241–25
7C025/0251–25
V
Com’l
190
300
170
250
Ind
200
320
170
290
Com’l
50
70
40
60
180
100
150
120
180
100
170
3
15
3
15
3
15
3
15
Com’l
110
160
90
130
Ind
110
160
90
150
mA
75
mA
mA
mA
Electrical Characteristics Over the Operating Range
7C024/0241–35
7C025/0251–35
Parameter
Description
Test Conditions
Min. Typ.
7C024/0241–55
7C025/0251–55
Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
–0.7
0.8
–0.7
0.8
V
IIX
Input Leakage Current
–10
+10
–10
+10
µA
IOZ
Output Leakage Current Output Disabled, GND ≤ VO ≤ VCC
–10
+10
–10
+10
µA
GND ≤ VI ≤ VCC
2.4
2.4
0.4
V
0.4
2.2
V
V
Notes:
9. The voltage on any input or sI/O pin cannot exceed the power pin during power-up
10. Pulse width < 20 ns.
11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
Document #: 38-06035 Rev. *C
Page 7 of 21
CY7C024/0241
CY7C025/0251
Electrical Characteristics Over the Operating Range (continued)
7C024/0241–35
7C025/0251–35
Parameter
ICC
Description
Test Conditions
Operating Current
ISB1
ISB2
ISB3
ISB4
Min. Typ.
7C024/0241–55
7C025/0251–55
Max. Min. Typ. Max. Unit
VCC = Max., IOUT = 0 mA,
Outputs Disabled
Com’l
160
230
150
230
Ind
160
260
150
260
Standby Current
(Both Ports TTL Levels)
CEL and CER ≥ VIH,
f = fMAX[11]
Com’l
30
50
20
50
Ind
30
65
20
65
Standby Current
(One Port TTL Level)
CEL or CER ≥ VIH,
f = fMAX[11]
Com’l
85
135
75
135
Ind
85
150
75
150
Standby Current
(Both Ports CMOS
Levels)
Both Ports CE and CER ≥
VCC – 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[11]
Com’l
3
15
3
15
Ind
3
15
3
15
Standby Current
(Both Ports CMOS
Levels)
One Port CEL or
CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
Active Port Outputs, f = fMAX[11]
Com’l
80
120
70
120
Ind
80
135
70
135
mA
mA
mA
mA
mA
Capacitance[12]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25×C, f = 1 MHz,
VCC = 5.0V
Unit
10
pF
10
pF
AC Test Loads and Waveforms
5V
5V
R1 = 893Ω
C = 30 pF
RTH = 250Ω
OUTPUT
OUTPUT
R1 = 893Ω
OUTPUT
C = 30pF
R2 = 347Ω
C = 5 pF
R2 = 347Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPUT
3.0V
C = 30 pF
GND
10%
90%
90%
10%
≤ 3 ns
≤ 3 ns
Load (Load 2)
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06035 Rev. *C
Page 8 of 21
CY7C024/0241
CY7C025/0251
Switching Characteristics Over the Operating Range [13]
7C024/0241–15
7C025/0251–15
Parameter
Description
Min.
Max.
7C024/0241–25
7C025/0251–25
Min.
Max.
7C024/0241–35
7C025/0251–35
Min.
Max.
7C024/0241–55
7C025/0251–55
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold From Address
Change
tACE[14]
CE LOW to Data Valid
15
25
35
55
ns
tDOE
OE LOW to Data Valid
10
13
20
25
ns
tLZOE[15, 16, 17]
tHZOE[15, 16, 17]
tLZCE[15, 16, 17]
tHZCE[15, 16, 17]
tPU[17]
tPD[17]
tABE[14]
OE Low to Low Z
15
3
CE LOW to Power-Up
25
3
ns
25
ns
25
ns
3
20
0
ns
ns
3
3
0
55
20
15
ns
3
3
3
0
35
15
10
55
3
3
10
CE HIGH to High Z
35
3
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
0
ns
CE HIGH to Power-Down
15
25
25
55
ns
Byte Enable Access Time
15
25
35
55
ns
Write Cycle
tWC
Write Cycle Time
15
25
35
55
ns
tSCE[14]
CE LOW to Write End
12
20
30
35
ns
tAW
Address Set-Up to Write End
12
20
30
35
ns
tHA
Address Hold From Write
End
0
0
0
0
ns
tSA[14]
Address Set-up to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
35
ns
tSD
Data Set-Up to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[16, 17]
tLZWE[16, 17]
tWDD[18]
tDDD[18]
R/W LOW to High Z
R/W HIGH to Low Z
10
0
15
0
20
0
25
0
ns
ns
Write Pulse to Data Delay
30
50
60
70
ns
Write Data Valid to Read
Data Valid
25
35
35
45
ns
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
16. Test conditions used are Load 3.
17. This parameter is guaranteed but not tested.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document #: 38-06035 Rev. *C
Page 9 of 21
CY7C024/0241
CY7C025/0251
Switching Characteristics Over the Operating Range (continued)[13]
7C024/0241–15
7C025/0251–15
Parameter
Busy Timing
Description
Min.
Max.
7C024/0241–25
7C025/0251–25
Min.
Max.
7C024/0241–35
7C025/0251–35
Min.
Max.
7C024/0241–55
7C025/0251–55
Min.
Max.
Unit
[19]
tBLA
BUSY LOW from Address
Match
15
20
20
45
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
40
ns
tBLC
BUSY LOW from CE LOW
15
20
20
40
ns
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-up for Priority
5
15
5
20
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
(Slave)
13
20
30
40
ns
tBDD[20]
BUSY HIGH to Data Valid
Note 20
20
Note 20
35
Note 20
Note 20
ns
ns
[19]
Interrupt Timing
tINS
INT Set Time
15
20
25
30
ns
tINR
INT Reset Time
15
20
25
30
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE
or SEM)
10
12
15
20
ns
tSWRD
SEM Flag Write to Read Time
5
10
10
15
ns
tSPS
SEM Flag Contention
Window
5
10
10
15
ns
tSAA
SEM Address Access Time
15
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
25
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5V).
55
ns
Timing
Data Retention Mode
VCC
4.5V
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
35
VCC > 2.0V
4.5V
VCC to VCC – 0.2V
CE
Parameter
ICCDR1
Test Conditions[21]
@ VCCDR = 2V
tRC
V
IH
Max.
Unit
1.5
mA
Notes:
19. Test conditions used are Load 2.
20. tBDD is a calculated parameter and is the greater of tWDD– tPWE (actual) or tDDD– tSD (actual).
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06035 Rev. *C
Page 10 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[22, 23, 24]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[22, 25, 26]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[22, 24, 25, 25, 26]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes:
22. R/W is HIGH for read cycles
23. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
24. OE = VIL.
25. Address valid prior to or coincident with CE transition LOW.
26. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06035 Rev. *C
Page 11 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[27, 28, 29, 30]
tWC
ADDRESS
tHZOE [33]
OE
tAW
CE
[31,32]
tPWE[30]
tSA
tHA
R/W
tHZWE[33]
DATA OUT
tLZWE
NOTE 34
NOTE 34
tSD
tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 35]
tWC
ADDRESS
tAW
CE
[31,32]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
29. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30. If OE is LOW during a R/W-controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W-controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tPWE.
31. To access RAM, CE = VIL, SEM = VIH.
32. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06035 Rev. *C
Page 12 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[36]
tOHA
tAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[37, 38, 39]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
38. Semaphores are reset (available to both ports) at cycle start.
39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06035 Rev. *C
Page 13 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[40]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note:
40. CEL = CER = LOW.
Document #: 38-06035 Rev. *C
Page 14 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[41]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSY L
Busy Timing Diagram No.2 (Address Arbitration)[41]
Left Address Valid First
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note:
41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06035 Rev. *C
Page 15 of 21
CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE FFF (1FFF CY7C025)
tHA[42]
CE L
R/W L
INT R
tINS [43]
Right Side Clears INT R :
tRC
READ FFF
(1FFF CY7C025)
ADDRESSR
CE R
tINR [43]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE FFE (1FFE CY7C025)
tHA[42]
CE R
R/W R
INT L
tINS[43]
Left Side Clears INT L:
tRC
READ FFE
(1FFE CY7C025)
ADDRESSR
CE L
tINR[43]
R/W L
OE L
INT L
Notes:
42. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06035 Rev. *C
Page 16 of 21
CY7C024/0241
CY7C025/0251
Ordering Information (4K x16 Dual-Port SRAM)
Speed
(ns)
15
25
35
55
Ordering Code
Package
Name
Package Type
CY7C024–15AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-15AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–15JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-15JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-25AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–25JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-25JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C024-25AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–25JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-25JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-35AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–35JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-35JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C024-35AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–35JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-35JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C024-55AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–55JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-55JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C024–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C024-55AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C024–55JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C024-55JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Ordering Information (8K x 16 Dual-Port SRAM)
Speed
(ns)
15
Ordering Code
Package
Name
CY7C025–15AC
A100
CY7C025-15AXC
A100
CY7C025–15JC
CY7C025-15JXC
Package Type
100-Pin Thin Quad Flat Pack
Commercial
100-Pin Lead Free Thin Quad Flat Pack
J83
84-Lead Plastic Leaded Chip Carrier
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–15AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-15AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *C
Operating
Range
Industrial
Page 17 of 21
CY7C024/0241
CY7C025/0251
Ordering Information (8K x 16 Dual-Port SRAM) (continued)
Speed
(ns)
25
35
55
Ordering Code
Package
Name
Package Type
CY7C025–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-25AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–25JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-25JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-25AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–25JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-25JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-35AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–35JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-35JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-35AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–35JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-35JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C025-55AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–55JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-55JXC
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
CY7C025–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C025-55AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C025–55JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C025-55JXI
J83
84-Lead Lead Free Plastic Leaded Chip Carrier
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Ordering Information (4K x 18 Dual-Port SRAM)
Speed
(ns)
15
25
35
55
Ordering Code
Package
Name
Package Type
CY7C0241–15AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-15AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–15AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-15AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-25AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-25AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-35AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-35AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C0241-55AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0241–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C0241-55AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *C
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 18 of 21
CY7C024/0241
CY7C025/0251
8K x 18 Dual-Port SRAM
Speed
(ns)
15
25
35
55
Ordering Code
Package
Name
Package Type
CY7C0251–15AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251–15AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–25AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251-25AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–25AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–25AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–35AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251–35AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–35AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–35AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–55AC
A100
100-Pin Thin Quad Flat Pack
CY7C0251–55AXC
A100
100-Pin Lead Free Thin Quad Flat Pack
CY7C0251–55AI
A100
100-Pin Thin Quad Flat Pack
CY7C0251–55AXI
A100
100-Pin Lead Free Thin Quad Flat Pack
Document #: 38-06035 Rev. *C
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 19 of 21
CY7C024/0241
CY7C025/0251
Package Diagrams
100-Pin Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
84-Lead Lead Free Plastic Leaded Chip Carrier J83
51-85006-*A
All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-06035 Rev. *C
Page 20 of 21
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C024/0241
CY7C025/0251
Document History Page
Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06035
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
110177
09/29/01
SZV
Change from Spec number: 38-00255 to 38-06035
*A
122286
12/27/02
RBI
Power-up requirements added to Maximum Ratings Information
*B
236754
See ECN
YDT
Removed cross information from features section
*C
279132
See ECN
RUY
Added Lead (Pb)-Free packaging information
Document #: 38-06035 Rev. *C
Page 21 of 21
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